JP5000859B2 - Generation apparatus and program capable of causing computer to execute generation method - Google Patents

Description

The present invention, generator, and generates either or both of the test program and the test pattern program used in each generation method related to program capable of causing a computer to execute the, in particular program language is different semiconductor test device It is related with the production | generation apparatus etc. to perform.

  FIG. 5 is a schematic block diagram of a conventional test program generation system for semiconductor test equipment.

  The generation system 1 includes a storage unit 3, an intermediate data group 5, a plurality of test program generation units 7A to 7n, a plurality of translation units 9A to 9n, a library extraction / intermediate data generation unit 11, and an intermediate data library. Registration means 13. The storage unit 3 includes a library 15 and a product information file 17.

  The library 15 registers information common to each type of LSI tester, such as the measurement method and the content of the measurement sequence. The product information file 17 stores product information unique to each LSI type, such as various LSI package standards, pin arrangements and names. The library extraction / intermediate data generation means 11 reads data necessary for generating the test program for each model LSI tester from the library 15 and the product information file 17 of the storage means 3, and data in a common language independent of various test program languages. The files 19 to 37 of the intermediate data group 5 are generated.

  Here, the test flow file 19 is a file describing measurement items and measurement order, and the first, second,..., Nth template files 21A to 21n describe a measurement sequence for each type of LSI to be measured. It is a file. The waveform file 23 is a file describing the waveform mode and timing value of the signal waveform input / output to / from the measurement target LSI, and the level file 25 is a file describing the voltage of the signal input / output to / from the measurement target LSI. The pin file 27 is a file describing the connection relationship between the contact of the LSI to be measured and the contact of the LSI tester, and the DC measurement condition file 29 is a file describing the measurement conditions of the DC measurement. The power sequence file 31 is a file describing the order of power on / off of the units and the time, and the variable file 33 is a file describing variables and arithmetic expressions. The pattern list file 35 is a file that describes information on the execution start address and stop address of the test pattern, and the instance file 37 is a file that describes the association between the template and each parameter.

  The intermediate data / library registration unit 13 registers the intermediate data included in the generated files 19 to 37 of the intermediate data group 5 in the library 15 of the storage unit 3.

  The first, second,..., Nth test program generation means 7A to 7n are provided for each type of LSI tester, and from the necessary files 19 to 37 of the intermediate data group 5. By converting the read intermediate data, first, second,..., Nth test programs 39A to 39n corresponding to each type of LSI tester are created as ASCII (American Standard Code for Information Interchange) files.

  The first, second,..., Nth program translating means 9A to 9n are provided for each type of LSI tester, and compile and link each test program 39A to 39n. First, second,..., Nth test programs 41A to 41n of binary files, which are executable programs corresponding to each model of the tester, are generated.

JP 2000-163278 A

  However, in the test program generation described above, test program generation means and the like are provided for each type of LSI tester, which requires many processing steps and is wasteful, resulting in a large and complicated system configuration.

  In addition, as another method of executing a test of a device under test with other types of semiconductor test equipment with the same test contents, an engineer manually edits an existing program. Enormous programming language knowledge for editing is required for engineers, and the possibility of human error cannot be denied, and the equivalence of test contents has not been verified.

Thus, the present invention is not a human approach with the above problem, the process is simple generation method by removing the waste in executable by a computer program, and generating device to simplify the system configuration I will provide a.

A generation apparatus according to a first aspect of the present invention is a generation apparatus that generates one or both of a test program and a test pattern program used in each of a plurality of semiconductor test apparatuses having different program languages, and for the semiconductor test apparatus The hardware setting information and the test program acquired by executing the test program or acquired by executing the test program for the virtual semiconductor test apparatus are in a program language different from the program language in the plurality of semiconductor test apparatuses. Reverse conversion means for reverse conversion to intermediate data in a common format, and either or both of a test program and a test pattern program according to the programming language of each semiconductor test apparatus using the intermediate data reversely converted by the reverse conversion means and a generation capable of generating means, before Inverse conversion means, comparison means for comparing the intermediate data converted back from the hardware configuration information the intermediate data is converted back from the test program, using the comparison result of the comparing means, the hardware settings A merge means for merging the intermediate data reversely converted from the information and the intermediate data reversely converted from the test program ;

The invention according to claim 2 is a program capable of causing a computer to execute a generation method for generating either or both of a test program and a test pattern program used in each of a plurality of semiconductor test apparatuses having different program languages. The generation method includes the hardware setting information and the test obtained by the inverse conversion means obtained by executing the test program for the semiconductor test apparatus or by executing the test program for the virtual semiconductor test apparatus. A reverse conversion step of reversely converting the program into intermediate data in a common format in a program language different from the program language in the plurality of semiconductor test devices; and a generation unit using the intermediate data reversely converted by the reverse conversion unit Test programs according to the programming language of the semiconductor test equipment A step of generating either or both of the program and the test pattern program, and the reverse conversion step includes a step of comparing the intermediate data reversely converted from the hardware setting information and the intermediate data reversely converted from the test program. A program capable of causing a computer to execute a generation method including a step of comparing data.

According to a third aspect of the present invention, in the second aspect of the present invention, the reverse conversion step is performed by using the intermediate data reversely converted from the hardware setting information by the merge means using the comparison result of the comparison means and the test program. A program capable of causing a computer to execute a generation method, further comprising a step of merging with the inversely converted intermediate data.

According to the present invention, the hardware configuration information and the test program, the inverse transform unit and the programming language in a plurality of semiconductor testing device is converted back to the intermediate data of the common format by different programming languages. Then, either or both of a test program and a test pattern program corresponding to the program language of each semiconductor test apparatus can be generated using the inversely converted intermediate data. Therefore, it is possible to convert the program into a multi-model that is not an artificial method, and by reusing the intermediate data, the processing process can be made simple and simple. In particular, in the reverse conversion process, the intermediate data reversely converted from the hardware setting information is compared with the intermediate data reversely converted from the test program, and the intermediate result reversely converted from the hardware setting information using the comparison result. It is also possible to merge the data with the intermediate data reversely converted from the test program.

  FIG. 1 is a schematic block diagram of a generation apparatus according to an embodiment of the present invention. The configuration will be described below with reference to FIG.

  The generation device 51 includes an intermediate data generation engine 53, an intermediate data storage unit 55, a constraint file 57, a GUI (graphical user interface) 59, a program generation engine 61 as a generation unit, and a constraint check unit 67. , A reverse conversion engine 69 as a conversion means, a notification unit 75, and a template storage unit 81.

  The intermediate data generation engine 53 receives VCD (Value Change Dump) data, HDL (Hardware Description Language) data, layout data, and the like. Here, the VCD data is one of vector files output by logic simulation performed when HDL or C language is used for logic design in semiconductor development, and conforms to the format of the IEEE standard. The intermediate data generation engine 53 automatically generates intermediate data based on the above data. The language of the pattern data may be, for example, WGL (Wave Generation Language) or STIL (Standard Test Interface Language).

  The intermediate data storage unit 55 stores and saves the intermediate data as an intermediate file. Note that the constraint check unit 67 described later determines whether or not the intermediate data stored in the intermediate data storage unit 55 meets the constraint conditions set in advance for each semiconductor test apparatus stored in the constraint file 57. Can be checked. The notification unit 75 can notify the user of the check result, and the user can edit or modify intermediate data for the data portion that cannot be automatically generated using the GUI 59, or the intermediate based on the check result notified from the notification unit 75. Edit and modify data.

  The intermediate data that has been edited, corrected, etc. is input to the program generation engine 61. The program generation engine 61 includes a test program generation unit 63 and a test pattern program generation unit 65. The test program generation unit 63 also receives the template code of the test program stored in the template storage unit 81. Here, the template is a model of a test program, and the template is prepared for each model and for each test item because the program language specification differs depending on the model of each semiconductor test apparatus. A predetermined variable is embedded in the template in order to incorporate a parameter that exists as intermediate data. These templates are created manually by the user and shared by being registered in the library. It should be noted that the template storage unit 81 and the intermediate data storage unit 55 exist as independent libraries so that the template can be shared not only as intermediate data but also in test application development for other devices. . The test program generator 63 generates a test program 77, and the test pattern program generator 65 generates a test pattern program 79. Here, the test program means a control program (main program).

  FIG. 2 is a flowchart specifically showing the operations of the inverse conversion engine 69, the constraint check unit 67, the notification unit 75, and the template storage unit 81 of FIG.

  The test program 77 and the test pattern program 79 are input to the inverse conversion engine 69. In addition, the hardware setting information 82 and the template information stored in the template storage unit 81 are also input to the inverse conversion engine 69. Here, the hardware setting information 82 is a general term for information obtained from each module of hardware such as a driver control module, a comparator module, a power supply control module, and a DC measurement module. The inverse conversion engine 69 includes an extraction unit 71, a processing unit 73, a comparison unit 83, and a merge unit 84. The extraction unit 71 decodes the test program 77 and the test pattern program 79 and extracts at least information about the pins. The processing unit 73 performs a reformatting process on the extracted information according to the intermediate data format. The comparison unit 83 and the merge unit 84 will be described in detail later.

  This will be described more specifically with reference to FIG. In step S1, the inverse conversion engine 69 selects a model of the test program 77 and the test pattern program 79 to be inversely converted or the hardware setting information 82. Next, in step SA1, the test pattern program 79 is read into the reverse conversion engine 69, in step SB1, the test program 77 is read into the reverse conversion engine 69, and in step SC1, the hardware setting information 82 is read into the reverse conversion engine. Note that it is not always necessary to select and execute the processes in step SB1 and step SC1, and either one may be selected.

  The extraction unit 71 extracts pattern data for each pin in each cycle in step SA2, and extracts pin attribute information in steps SB2 and SC2. Here, pin attribute information includes timing set, waveform mode, change timing, DC measurement related information of each pin of the device, voltage level information determined by high level value and low level value, physical connection between device pin and tester Information and driver unit type information connected to each pin of the device. For each unique pin name, the timing set is determined by the cycle width and signal change timing. The cycle width is determined by the fundamental frequency. The definition of the signal change timing is determined by the delay of each signal change point from the cycle base point, and the change point of the signal of each pin is expressed by the delay from the base point. The waveform mode is determined by NRZ (None Return Zero), RZO (Return Zero / One), and XOR (Exclusive OR). Further, the extraction unit 71 extracts a timing set in each cycle in step SA3, and also extracts a test category, a power-on sequence, and a test flow in step SB3. The extraction unit 71 extracts a power-on sequence in step SC3.

  In step S3, the processing unit 73 performs a reformatting process on the intermediate file.

  In step S4, it is determined whether or not the test program 77 and the hardware setting information 82 are inversely converted to extract intermediate data. When the intermediate data is extracted from both, the process proceeds to step S5, where the comparison unit 83 extracts the data extracted at steps SB1 to SB3 and reformatted at step S3, and extracted at steps SC1 to SC3 and then reset at step S3. Compare with formatted data. In step S6, the notification unit 75 notifies the user of the comparison result in step S5. Based on the comparison result, the user can perform a merge (integration) process in which the intermediate data converted from the test program 77 is supplementally corrected with unextracted items using the intermediate data converted from the hardware setting information 82. Recognized and can recognize inconsistent parts. Then, the editing part and the correction part necessary for the program generation engine 61 to generate the test program 77 for the conversion destination which is another model are clarified, and the user can edit and correct it using the GUI 59. In step S7, the merging unit 84 performs processing for merging the intermediate data converted from the test program 77 and the intermediate data converted from the hardware setting information 82 based on the comparison result in step S5. Here, assuming that conversion is performed only from the test program 77, it is highly possible that the hardware settings not specified in the test program 77 are set to initial values for each semiconductor test apparatus. From 82, the set value can be reliably extracted including these initial values. Therefore, it is possible to extract information on intermediate data that is equivalent as a test condition when converting to another model. If no intermediate data is extracted from both in step S4, the process proceeds to step S8.

  In step S8, it is determined whether or not the test program 77 is inversely converted to extract intermediate data and a template, or only the template is extracted. In any case, in step S9, the processing unit 73 performs a process of replacing the parameter portion extracted as intermediate data in the template code with a predetermined variable. The template storage unit 81 stores the template information obtained by the processing unit 73. The information stored in the template storage unit 81 is information that can be reused as a library when generating a test program for another semiconductor device.

  Following step S9 or when not in any of the above cases at step S8, the process proceeds to step S10. In step S <b> 10, the constraint checking unit 67 checks whether the intermediate data obtained by the inverse transformation matches a constraint condition predetermined for each semiconductor test apparatus stored in the constraint file 57. I do. The check is performed in particular regarding whether or not the scope of restrictions of the hardware specification is satisfied. Here, the constraint check may be performed simultaneously on a plurality of semiconductor test apparatuses, or may be performed only on one type of semiconductor test apparatus selected in advance by the user using the GUI 59.

  In step S11, the notification unit 75 notifies the user of the result related to the conversion process. In particular, the user can recognize a correction point for the intermediate data after the reverse conversion using the GUI 59 based on the result of the element that cannot be converted. In step S11, the notification unit 75 also notifies the user of the check result. In particular, a result obtained by simultaneous checking for a plurality of models is an index for optimally selecting a conversion destination model. Then, the information obtained by the notification unit 75 clarifies the editing part and the correction part necessary for the program generation engine 61 to generate the test program 77 or the test pattern program 79 for the conversion destination which is another model. The user can edit and modify the GUI 59.

  Since the intermediate data storage unit 55 stores and stores the intermediate data reversely converted by the reverse conversion engine 69 as an intermediate file, the program generation engine 61 uses the intermediate data to create a new test program and test pattern. A program can be generated. Therefore, the test program and the test pattern program can be reused in the form of intermediate data, and the test program and the test pattern program for a plurality of models can be easily generated.

  By the way, when the test program 77 is executed on the semiconductor test apparatus, there is information set in each module of hardware in the test apparatus as debug information of the program, and the engineer can obtain this information. Moreover, the engineer can obtain the same information in the virtual system of the test apparatus. As a result, the engineer can confirm the contents of the program by confirming whether the correct information is set as the hardware setting information 82 for the semiconductor test apparatus or the virtual system. The hardware setting information 82 is also input to the inverse conversion engine 69, so that intermediate data can be extracted. That is, the extraction unit 71 can decode only the hardware setting information 82 to extract at least information about the pins, and the processing unit 73 can perform reformatting processing on the extracted information according to the intermediate data format.

  FIG. 3 is a processing flowchart focused on the case where a template is used when the extraction unit 71 extracts intermediate data from the test program 77 in the inverse transformation.

  In step T1, a template is selected. In steps T2 and T3, a template is read. The reading is performed in the form of function A (% sv,% sr); function B (% im,% mr); In step T3, the program is read. The reading here is performed in the form of function A (5 V, 8 V); function B (100 mA, 300 mA), for example, as a # test program. In step T4, the template variable part is referred to from the program and element extraction is performed. That is, when the test program 77 and the test pattern program 79 are generated by the program generation engine 61 and the template storage unit 81, the template used at the time of generation is also read by the reverse conversion engine 69 and the variables in the template are read. The part corresponding to the part is recognized as an element serving as intermediate data, and is separated from the test program 77 and extracted. For example, 5V is extracted for% sv, 8V is extracted for% sr, 100 mA is extracted for% im, and 300 mA is extracted for% mr. Note that the processing of steps T1 to T4 is processing corresponding to steps SB1 to SB3 of FIG.

  In step T5, the extracted element is reformatted into intermediate data. For example, considering the above example, 5 V, 8 V, 100 mA, and 300 mA are stored in the intermediate data storage unit 55. The process at step T5 corresponds to the process at step S3 in FIG.

  Thus, by generating intermediate data by reverse conversion from the test program 77 generated by the program generation engine 61, even when the test program 77 itself is edited, the edited portion is automatically and accurately reflected in the intermediate data. Can do. In addition, by using the template at the time of creation, since the inverse conversion is only the comparison process and the extraction process, the process is simplified and the conversion can be performed at high speed.

  FIG. 4 is a processing flow diagram when the extraction unit 71 does not use a template when extracting intermediate data from the test program 77 in the inverse transformation.

  In step U1, a program reading process is performed. This process corresponds to step SB1 in FIG. In step U2, parsing is performed, and in step U3, intermediate data elements are extracted. Steps U2 and U3 correspond to steps SB2 and SB3 in FIG. Step U4 corresponds to step S3 in FIG. In step U5, it is determined whether to extract a template code. When extracting, the test program is replaced with a variable in step U6. This replacement is performed by, for example, #function A (5V, 8V); function B (100 mA, 300 mA) as a test program; function A (% sv,% sr); function B (% im,%); mr); is output. In step U7, storage in the template storage unit 81 is performed. These steps U6 and U7 correspond to step S9 in FIG. In summary, even if the test program 77 input to the inverse conversion engine 69 is generated by the program generation engine 61, the template storage unit 81 does not exist, or the program generation engine 61 is not used. In the case of the test program 77 created automatically, the inverse conversion process cannot be performed using the template existing in the template storage unit 81. Therefore, the inverse conversion engine 69 extracts an element as intermediate data after performing syntax analysis based on the program language specification. Compared to the process extracted using the template shown in FIG. 3, the process is more complicated, but the existing test program 77 can be separated into an intermediate data element and a template element by replacing the extracted element part as a predetermined variable. It is. Therefore, as described above, the template is created artificially in principle, but the intermediate data element and the template element are automatically generated from the existing test program 77 via the inverse transformation engine 69, so that In addition to improving efficiency, conventional software assets can be accumulated in the intermediate data storage unit 55 and the template storage unit 81 and inherited. In the case of this inverse transformation, either the intermediate data generation or the template generation processing may be performed.

  In the above embodiment, the intermediate data is generated using the intermediate data generation engine 53. However, from the viewpoint of reverse conversion of the program generated by the program generation engine 61 by the reverse conversion engine 69, the intermediate data generation engine 53 is used. Is not always necessary.

  Moreover, in the said embodiment, although the test program 77 and the test pattern program 79 were produced | generated using the program production | generation engine 61, either one may be sufficient.

  Furthermore, in the above-described embodiment, the test program and the test pattern program converted into intermediate data for reuse are generated by the program generation engine 61. However, the present invention is not limited to this. In addition to the test program and the test pattern program, the test program and the test pattern program generated by an existing generation device that does not have the inverse conversion engine 69 may be used.

  Furthermore, in the above-described embodiment, the constraint check unit 67 performs only the check. However, the automatic correction function that corrects the extracted element that does not satisfy the hardware constraint condition within the constraint range based on the check result. You may make it have.

  Furthermore, in the above-described embodiment, the generation device 51 and the generation method have been described with reference to FIGS. 1 and 2, but a use mode in which the generation method can be executed by a computer and a recording medium on which the program is recorded may be used. .

It is a schematic block diagram of the production | generation apparatus which concerns on embodiment of this invention. FIG. 7 is a flowchart specifically showing operations of an inverse conversion engine 69, a constraint check unit 67, a notification unit 75, and a template storage unit 81 in FIG. FIG. 10 is a processing flow diagram focusing on a case where a template is used when an extraction unit 71 extracts intermediate data from a test program 77 in inverse transformation. FIG. 10 is a processing flow diagram when an extraction unit 71 does not use a template when extracting intermediate data from a test program 77 in inverse transformation. It is a schematic block diagram of the conventional test program generation system for semiconductor test equipment.

Explanation of symbols

51 Generating Device 61 Program Generating Engine 67 Constraint Checking Unit 69 Inverse Conversion Engine 75 Notification Unit 81 Template Storage Unit

Claims (3)

A generation device that generates one or both of a test program and a test pattern program used in each of a plurality of semiconductor test devices having different program languages,
Hardware setting information and test program acquired by executing a test program for a semiconductor test apparatus or acquired by executing a test program for a virtual semiconductor test apparatus are program languages in the plurality of semiconductor test apparatuses. Reverse conversion means for performing reverse conversion to intermediate data in a common format in a different programming language,
A generation unit capable of generating either or both of a test program and a test pattern program according to a program language of each semiconductor test apparatus using the intermediate data reversely converted by the reverse conversion unit;
The inverse conversion means includes
Comparing means for comparing the intermediate data inversely converted from the hardware setting information and the intermediate data inversely converted from the test program;
A generating apparatus , comprising: a merging unit that merges the intermediate data inversely converted from the hardware setting information and the intermediate data inversely converted from the test program using the comparison result of the comparing unit. A program capable of causing a computer to execute a generation method for generating either or both of a test program and a test pattern program used in each of a plurality of semiconductor test apparatuses having different program languages,
The generation method is:
The inverse conversion means acquires the hardware setting information and the test program acquired by executing a test program for a semiconductor test apparatus or acquired by executing a test program for a virtual semiconductor test apparatus. A reverse conversion step for performing reverse conversion to intermediate data in a common format in a programming language different from the programming language in the test apparatus;
A generating step that can generate either or both of a test program and a test pattern program according to a program language of each semiconductor test apparatus using the intermediate data that has been inversely converted by the inverse conversion unit;
The reverse conversion step includes causing the computer to execute a generation method, wherein the comparison unit includes a step of comparing the intermediate data reversely converted from the hardware setting information and the intermediate data reversely converted from the test program. Possible program. The reverse conversion step further includes a step in which the merging unit merges the intermediate data reversely converted from the hardware setting information and the intermediate data reversely converted from the test program using the comparison result of the comparison unit. A program capable of causing a computer to execute the generation method according to claim 2.

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