JP2006119922A - Functional verification system, control method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a function verification system efficiently generating high quality test items, test specifications, and test groups for function verification of a logic circuit. <P>SOLUTION: A function verification system 1 comprises a data input/editing part 10, a database part 20, a verification element extraction part 30, a verification element group 40, a verification environment constructing part 50, and a verification environment 60. ELectronic data of verification object DUT specifications 21, a various DUT specification libraries 26, a test item library 22, a test specification library 27, a verification library 24, a test template group 25, correspondence information 28, and a DUT library 29 are stored in the database part 20. The verification element extraction part 30 compares the verification object DUT specifications 21 with function specifications of individual DUTs in the various DUT specification library 26 to extract function specifications having a prescribed degree of approximation or higher, test items corresponding to the extracted function specifications are extracted on the basis of the correspondence information 28, and thus a test item group relating to all function specifications of a verification object DUT is generated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a function verification system, a control method, and a program for setting necessary and sufficient function verification items of a logic circuit and performing function verification related to the function verification items.

  Conventionally, in functional verification of logic circuits such as interrupt circuits and timer circuits mounted on various electronic devices (hereinafter referred to as functional verification of DUT (Design Under Test)), the DUT is described in the functional specification. Functional verification was carried out by a dynamic or static verification method to check whether it functions according to the functional specifications. Usually, a verifier who performs functional verification of a DUT to be verified examines the state of a signal at a terminal that can be observed in the DUT without going into the part of how each function of the DUT is actually implemented. Thus, it is verified in a black box whether the DUT functions according to the functional specification.

  When verifying the function of the DUT, the verifier extracts the test items to be verified from the functional specifications of the DUT and creates the test specifications, and the designer fails to extract the test items for the created test specifications. After confirming whether or not there was a review, the verifier created a test based on the completed test specification and performed functional verification.

  When extracting test items that should be verified, it may be possible to check whether there are any missing test items by referring to a list of test items that are prepared in advance for each function to be extracted. there were. In addition, when the designer receives a review of the test items from the verifier, it may be confirmed whether there are any missing test items extracted by the verifier. In these cases, some effects were found in avoiding missing test items.

  In recent years, in the field of software development, it has become possible to automatically generate programs from specifications based on structured methods and object-oriented methodologies. In addition, a technique for automatically generating software code based on software requirement specifications input via a graphical user interface is disclosed (for example, see Patent Document 1).

In addition, the author of the present invention can effectively use the test item list, parameterized model and monitor verification module, and test template corresponding to the test item for functional verification of the DUT. We have proposed a function verification system and method that can create test items, test specifications, and tests for DUT function verification with high quality and high efficiency.
JP 2002-073336 A

  However, as described above, when verifying the function of a conventional DUT, the process of extracting test items to be verified from the function specification of the DUT, the process of creating the test specification, the process of reviewing the test specification, and the test There is a problem that the load required for the step of creating and the step of executing the test is greatly increased as the DUT becomes larger in scale, resulting in an increase in the functional verification period of the DUT.

  In addition, there is a problem that the extraction of test items to be verified from the function specification depends on the skill of the verifier in charge and greatly affects the quality of the function verification.

  Even if the verifier performs the work of referring to the test item list that covers the test items prepared for each function prepared in advance in order to avoid missing the test items to be verified. The verification omission caused by caution etc. could not be avoided.

  Moreover, even if the designer and the verifier perform a test review after extracting the test items by the verifier, there are not a few cases where a part of the test items to be functionally omitted is missing.

  In addition, among the processes related to function verification described above, how to extract necessary and sufficient test items in the process of extracting the test items to be verified, which is the most upstream process, greatly affects the subsequent verification quality. Therefore, it has been a big challenge to achieve both the reliability of extracting test items to be verified and the improvement of productivity.

  In addition, creating an appropriate test for the extracted test items is also an important point from the viewpoint of verification quality, and it is a major issue to achieve both improvement in reliability and productivity.

  In addition, as described above, it has become possible to automatically generate a program from specifications, and the application field is mainly the field of application or embedded software development, but it is also partly in the field of hardware development. Application has been attempted. That is, a program that automatically generates a program of the software from the specifications of the software to be realized, or a program that describes the functions of the hardware in the extended C language for hardware description from the functional specifications of the hardware to be realized Is automatically generated.

  In addition, a technique for automatically generating a test item of a software and a test program from a specification or program of the software to be realized has been proposed.

  However, in the field of functional verification of hardware, there is no disclosure of technology for automatically generating test specifications and test programs for functional verification. From the functional specifications of the DUT, test items and test specifications for functional verification related to the functions. There is a growing need to improve the quality of the test creation process.

  The above-described function verification system and method proposed by the author of the present invention is based on a list of test items related to functional verification of various logic circuits, and does not consider test execution and feedback of test execution results. There was a problem.

  An object of the present invention is to provide a function verification system, a control method, and a program capable of creating test items, test specifications, and test groups for functional verification of logic circuits with high quality and high efficiency. is there.

  In order to achieve the above object, the present invention provides a functional verification system for performing functional verification of a logic circuit, comprising a functional specification of a logic circuit to be verified, a set of functional specifications of various logic circuits, and the various logics. Storage means for storing a set of test items to be functionally verified with respect to the functional specifications of the circuit, individual functional specifications of the logic circuit to be verified, and individual functional specifications in the set of functional specifications of the various logic circuits A test item extracting means for comparing and extracting a functional specification having a degree of approximation equal to or greater than a predetermined value and a test item corresponding to the functional specification and generating a test item group relating to all functional specifications of the logic circuit to be verified; Features.

  In order to achieve the above-described object, the present invention is a functional verification system for performing functional verification of a logic circuit, which is a test item to be verified with respect to the functional specifications of the logic circuit to be verified and the functional specifications of various logic circuits. A storage means for storing a set of property specifications of properties to be functionally verified with respect to the functional specifications of the various logic circuits, a set of property templates to be functionally verified with respect to the functional specifications of the various logic circuits, and the verification target The individual functional specifications of the logic circuit and the individual functional specifications in the set of functional specifications of the various logic circuits are compared, and the functional specifications with a predetermined degree of approximation or more and test items related to the functional specifications are extracted, and the verification is performed. Test item extraction means for generating a test item group for all functional specifications of the target logic circuit, the test item group, and the verification target logic circuit A property specification generating means for analyzing a performance specification and generating a property specification group; and a function specification of the logic circuit to be verified, the test item group, the property specification group, and a set of the property template are analyzed, and the verification target is analyzed. And property group generation means for generating a property group necessary for functional verification of the logic circuit.

  According to the present invention, the individual functional specifications of the logic circuit to be verified are compared with the individual functional specifications in the set of functional specifications of the various logical circuits, and the functional specifications having a predetermined degree of approximation or higher are supported. The test items for all functional specifications of the logic circuit to be verified are generated and test items for functional verification of the logic circuit can be created with high quality and high efficiency. There is a remarkable effect that man-hour reduction, verification period shortening, and verification quality improvement can be realized at the same time.

  Further, according to the present invention, a test specification group is generated by analyzing the functional specifications of the test item group and the logic circuit to be verified, and the set of the functional specification, test item group and test template of the logic circuit to be verified The test group necessary for functional verification of the logic circuit to be verified is generated by analyzing the test, so that test specifications and tests can be created with high quality and high efficiency in addition to the test items for functional verification of the logic circuit It is possible to reduce the verification man-hours, shorten the verification period, and improve the verification quality at the same time.

  In addition, according to the present invention, since the test to be executed is controlled based on the analysis result of the coverage analysis means for analyzing the coverage of the execution result of the executed test, the quality of the test execution is improved to achieve the verification goal. And the remarkable effect that efficiency can be achieved is achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the function verification system according to the first embodiment of the present invention.

  In FIG. 1, a functional verification system 1 performs functional verification of a logic circuit, and includes a data input / editing unit 10, a database unit 20, a verification element extraction unit 30, a verification element group 40, a verification environment construction unit 50, and verification. It consists of an environment 60.

  In the present embodiment, each component of the function verification system 1 is stored in a main storage device or an auxiliary storage device on a workstation or a personal computer (PC) and functions based on control of the central processing unit. . In the present embodiment, it is assumed that the DUT and the test bench for DUT verification and the test are performed dynamically by executing simulation on a software simulator.

  The data input / editing unit 10 inputs and edits various data in the database unit 20, and includes a GUI (Graphical User Interface) configured from a workstation or a PC connected to the database unit 20 via a network. It is a man-machine interface having

  The database unit 20 includes a verification target DUT specification 21, various DUT specification libraries 26, a test item library 22, a test specification library 27, a verification library 24, a test template group 25, DUT specification / test item correspondence information 28, and a DUT library 29. Stores electronic data. Specifically, the database unit 20 is configured as an electronic data storage device such as a hard disk on a workstation or PC that stores the electronic data, and performs version management of the electronic data.

  The various DUT specification libraries 26 are libraries (collections) of existing various DUT functional specifications (specifications of various logic circuits such as interrupt circuits and timer circuits classified for each function). The test item library 22 is a library of test items whose functions should be verified with respect to the functional specifications of the existing various DUTs. The test specification library 27 is a library of test specifications related to test items whose functions should be verified with respect to the functional specifications of the existing various DUTs.

  The verification library 24 is a library of verification modules such as models and monitors that are prepared in advance and are necessary for functional verification of various DUTs. The test template group 25 is test template data prepared in advance corresponding to each test item in the test item list. The correspondence information 28 between the DUT specifications and the test items is information regarding the correspondence between the function specifications of the existing various DUTs and the corresponding test items. The DUT library 29 is a library including information on the following DUT 61.

  The verification element extraction unit 30 includes a test item extraction unit 31, a test specification generation unit 32, a verification module group extraction unit 33, and a test group generation unit 34. The verification element extraction unit 30 analyzes various data in the database unit 20, and A verification element group 40 necessary for functional verification of the DUT is extracted.

  As shown in FIG. 2, the test item extraction unit 31 includes an individual function specification extraction unit 301, a data structure analysis unit 302, a keyword extraction unit 303, an approximation degree evaluation unit 304, a similar specification extraction unit 305, and a test item selection unit 306. It is configured.

  The individual function specification extraction unit 301 inputs the verification target DUT specification 21 and various DUT specification libraries 26, and for each, for example, a keyword ("specification" or the like) described in the description part of each function specification or data By judging based on the identifier ("1.1") indicating the structure, the data structure is analyzed and the description of each individual function specification is extracted. For example, keywords (“name”, “contents”, etc.) indicating the characteristics of each part of the data structure for the description of each individual function specification extracted by the individual function specification extracting unit 301, Alternatively, the data structure of each functional specification is analyzed by making a determination based on the identifier (“1.1.1”) indicating the data structure.

  The keyword extraction unit 303 indicates a category (“arbiter”, etc.) and a feature (“one hot”, etc.) of the function specification for each part of the data structure of each individual function specification analyzed by the data structure analysis unit 302. An identifier ("A-1-1" or the like) corresponding to the keyword itself or a keyword indicating a category or feature is extracted. The degree-of-approximation evaluation unit 304 evaluates the degree of approximation between the verification target DUT specification 21 and the functional specifications in the various DUT specification libraries 26 with respect to the keywords (or identifiers corresponding to the keywords) extracted by the keyword extraction unit 303.

  The similar specification extraction unit 305 extracts the functional specifications in the various DUT specification libraries 26 when the degree of approximation evaluated by the approximation degree evaluation unit 304 is equal to or greater than a predetermined value. It should be noted that the similar specification extraction unit 305 extracts an appropriate functional specification for a certain functional specification of the verification target DUT specification 21 when none of the functional specifications of the various DUT specification libraries 26 has a degree of approximation exceeding a predetermined level. It is assumed that the user is notified through the workstation or the display unit of the PC, and information on the function specification for which a function specification with a degree of approximation equal to or greater than a predetermined value cannot be extracted is registered in the database unit 20.

  The test item selection unit 306 uses the test item library 22 and the DUT specification / test item correspondence information 28 to test items corresponding to the functional specifications in the various DUT specification libraries 26 extracted by the similar specification extraction unit 305. Are extracted from the test item library 22.

  The functions of the test specification generation unit 32, the verification module group extraction unit 33, and the test group generation unit 34 of the verification element extraction unit 30 will be described after the verification element group 40.

  The verification element group 40 includes a test item group 41, a test specification 42, a verification module group 43, and a test group 44.

  The test item group 41 is a set of test items necessary for functional verification of the verification target DUT specification 21 extracted by the test item extraction unit 31. The test specification 42 is obtained by extracting a test specification in consideration of the constraint condition based on the DUT specification for each test item necessary for functional verification of the DUT. The verification module group 43 is a set of verification modules necessary for functional verification of the DUT. The test group 44 is a set of tests necessary for functional verification of the DUT.

  The test item extraction unit 31 compares the DUT specification 21 to be verified with the functional specifications of the individual DUTs in the various DUT specification libraries 26, extracts functional specifications that are equal to or higher than a predetermined degree of approximation, and tests the DUT specifications and tests. Based on the item correspondence information 28, test items corresponding to the extracted functional specifications are extracted, and a test item group related to all functional specifications of the verification target DUT is generated.

  The test specification generation unit 32 analyzes the relevant verification target DUT specification 21 for each test item of the test item group to be implemented as the function verification of the DUT, and adds each constraint specification of the corresponding DUT specification. And test specifications 42 corresponding to all test item groups are generated.

  The verification module group extraction unit 33 analyzes the related verification target DUT specification 21 and the test specification 42 for each test item of the test item group to be implemented as the functional verification of the DUT, and performs functional verification regarding the test item. Sometimes, a part to be mounted on the test side is separated from a part to be mounted as a function of a verification module such as a model or a monitor, and a verification module such as a model or a monitor necessary for function verification related to the test item is verified library 24 If necessary, parameter information to be set in the verification module at the time of test execution is held, and verification module groups 43 corresponding to all test item groups are extracted.

  The test group generation unit 34 analyzes the test template group 25 for each test item of the test item group, extracts a corresponding test template, and relates to the verification target DUT specification 21, the test specification 42, and the verification module extraction unit. 33, the parameter information to be set in the verification module is analyzed from the test side, the necessary parameters are added to the test template, and the test to be performed as the functional verification of the DUT is generated. A test group 44 corresponding to the test item group is generated by executing the test item. Further, the test group generation unit 34 generates a test for acquiring the following coverage for a predetermined test item.

  The verification environment construction unit 50 constructs the following verification environment 60 by combining the verification element groups 40 described above.

  The verification environment 60 includes a test group 44, a DUT 61, a test bench 63, a verification unit / simulator interface (hereinafter abbreviated as I / F) 64, a software simulator 65, a test execution control unit 67, and a coverage analysis unit 68. . Since the verification module group 43 and the test group 44 in the verification environment 60 constitute the verification element group 40, the same reference numerals are given in the verification environment 60 and the verification element group 40 in FIG. Shall.

  The test bench 63 includes a verification module group 43 extracted by the verification module group extraction unit 33 and base hardware (hereinafter abbreviated as H / W) 62 necessary for functional verification of the verification target DUT. The base H / W 62 is a H / W top layer including the DUT 61, and is connected to the verification module group 43 to constitute a test bench 63, which can execute a simulation on the software simulator 65. A test group 44 and a DUT 61 are connected to the verification module group 43.

  The software simulator 65 is a logic simulator capable of executing a hardware program whose function is described in a hardware description language or the like. The verification unit / simulator I / F 64 is an interface for causing the verification unit described in a verification language or the like such as the test group 44 and the verification module group 43 to be executed on the software simulator 65.

  The test execution control unit 67 activates the software simulator 65 in the verification environment 60 and manages the execution of the test group 44 on the test bench 63. Further, the test execution control unit 67 receives the analysis result of the coverage analysis unit 68 described below, and executes a corresponding test after controlling the constraint conditions and the like when a predetermined coverage condition is not satisfied. Whether the coverage analysis unit 68 analyzed the coverage acquired at the time of test execution by the coverage acquisition mechanism described in the corresponding test in relation to the predetermined test item in the test group 44, and satisfied the predetermined condition It is determined whether or not the test execution control unit 67 is notified of the analysis result.

  Next, operations of the verification element extraction unit 30 and the verification environment construction unit 50, which are main components of the function verification system of the present embodiment having the above-described configuration, will be described.

  In the present embodiment, the database unit 20 includes a verification target DUT specification 21, various DUT specification libraries 26, a test item library 22, a test specification library 27, a verification library 24, a test template group 25, DUT specifications and test items. In addition to the correspondence information 28 and the DUT 61, a configuration is assumed in which a test specification 42, a verification module group 43, and a test group 44 that are extracted / generated are held.

  3 and 4 are flowcharts showing operations of the verification element extraction unit 30 and the verification environment construction unit 50 of the function verification system.

  3 and 4, first, the verification element extraction unit 30 performs the test item No. of the test item group corresponding to the DUT as the first step. Initialization processing (i = 1) is performed (step S100). Next, the verification element extraction unit 30 compares the verification target DUT specification 21 with the various DUT specification libraries 26, picks up the functional specifications in the various DUT specification libraries 26 that have been evaluated to be equal to or higher than a predetermined degree of approximation, and performs the DUT. The test item corresponding to the picked-up function specification is extracted with reference to the specification / test item correspondence information 28 (step S113).

  Next, the verification element extraction unit 30 analyzes the verification target DUT specification 21 related to the test item, adds a constraint condition of the verification target DUT specification 21, and generates a test specification 42 (step S101). Next, the verification element extraction unit 30 analyzes the verification target DUT specification 21 and the test specification 42 related to the test item, and implements the portion to be mounted on the test side and the verification module side when performing functional verification on the test item. After separation from the portion to be performed, a necessary verification module is extracted from the verification library 24, and parameter information to be set in the verification module at the time of test execution is held as necessary (step S102).

  Next, the verification element extraction unit 30 analyzes the test template group 25 and extracts a test template corresponding to the test item. The verification element extraction unit 30 stores the verification target DUT specification 21, the test specification 42, and the verification module extraction unit 33. The stored parameter information is analyzed, and necessary test conditions are added to the test template to create a test group 44 (step S103). Next, the verification element extraction unit 30 increments the test item No. (i) to select the next test item (i = i + 1) (step S104).

  Next, the verification element extraction unit 30 sets the test item No. When (i) is less than or equal to the total number n of test items in the test item group of the DUT (i ≦ n) (NO in step S105), the process proceeds to step S101 and the verification element extraction process is continued. On the other hand, the verification element extraction unit 30 has a test item No. When (i) exceeds the total number n of test items in the test item group of the DUT (i> n) (YES in step S105), the verification element extraction process is terminated, and the process proceeds to step S106. The verification element extraction unit 30 stores the test specification 42 generated in step S101 in the database unit 20 (step S106), and stores the verification module group 43 extracted in step S102 in the database unit 20 (step S107). The test group 44 generated in step S103 is stored in the database unit 20 (step S108).

  Next, as a first step, the verification environment construction unit 50 generates a base H / W 62 that is a module in the upper layer of the DUT 61 for connecting the DUT 61 to the test bench 63, and connects the DUT 61 (step S109). Next, the verification environment construction unit 50 connects the verification module group 43 extracted in step S102 to the base H / W 62 and the DUT 61 to configure the test bench 63 (step S110). Next, the verification environment construction unit 50 connects the test group 44 generated in step S103 to the test bench 63 (step S111). Finally, the verification environment construction unit 50 stores all connection information in the database unit 20, and constructs the verification environment 60 by incorporating the test group 44, the test bench 63, and the DUT 61 into the simulator environment (step S112).

  The test execution control unit 67 activates the software simulator 65 in the verification environment 60 and manages the execution of the test group 44 on the test bench 63 (step S114). Whether the coverage analysis unit 68 analyzed the coverage acquired at the time of test execution by the coverage acquisition mechanism described in the corresponding test in relation to the predetermined test item in the test group 44, and satisfied the predetermined condition (Step S115), and notifies the test execution control unit 67 of the analysis result. The test execution control unit 67 receives the analysis result of the coverage analysis unit 68, and executes a corresponding test after controlling the constraint conditions and the like when a predetermined coverage condition is not satisfied.

  In the above, a verification module such as a model or a monitor required for functional verification regarding each test item of the verification target DUT is included in the verification library 24, and similarly, required for functional verification regarding each test item of the DUT. It is assumed that a test template corresponding to the test is also included in the test template group 25.

  If the model, monitor, or test template required for functional verification related to each test item of the verification target DUT cannot be extracted, edit the required model, monitor, or test template by editing a new or similar module. It is created and additionally registered in the database unit 20 via the data input / editing unit 10.

  Also, if the functional specification of the verification target DUT does not have a degree of approximation higher than a predetermined level with any of the individual functional specifications in the various DUT specification libraries 26, a test item related to the functional specification is newly created and data is input. / Additional registration to the database unit 20 via the editing unit 10 is assumed.

  In this embodiment, as an operation example of the verification element extraction unit 30, a test item extraction process, a test specification extraction process, a verification module extraction process, and a test generation process are executed for each test item, and the next test item is obtained. Although the case of shifting is described, the present invention is not limited to this, and the following method is conceivable.

  For example, after all test items are extracted, the test specification extraction process for all test items is executed, then the verification module extraction process for all test items is executed, and the test generation process for all test items is further performed Or a method for performing a test specification extracting step, a verification module extracting step, a test generating step, etc. by collecting predetermined test items. That is, it is needless to say that various methods can be used to proceed with the internal processes of the verification element extraction unit 30 and are not limited to the methods described with reference to FIGS.

  Next, based on the specific examples of the DUT, test bench, and test group of the function verification system shown in FIG. 5, extraction of test item group, test specification, verification module, and test group necessary for functional verification of the verification target DUT The method of generation will be described with a specific example.

  FIG. 5 is a block diagram showing detailed configurations of the DUT 61, the test bench 63, and the test group 44 of the function verification system.

  In FIG. 5, only the bus arbiter 601 connected to the bus 602 is shown in the DUT 61, but other four masters connected to the bus 602, an address decoder, a bus multiplexer, and the like (not shown) are also provided. . The test bench 63 shows bus master models 1 and 201, bus master models 2 and 202, bus master models 3 and 203, bus master models 4 and 204, bus slave model 205, and bus monitor 206 as verification module groups. In addition, a verification module (not shown) necessary for functional verification of other components of the DUT is also provided. Although only the bus arbiter test 501 is shown in the test group 44, other tests (not shown) necessary for functional verification of other components of the DUT are also provided.

  Each of the bus master models 1, 201 to 4, and 204 is a verification module that functions as a bus master of the bus 602. The bus arbiter 601 is a verification module that arbitrates the bus rights of the four bus master models 1, 201 to 4, and 204 on the bus 602. The target DUT. The bus slave model 205 is a verification module that receives accesses such as write / read from the bus master models 1, 201 to 4, 204. The bus monitor 206 monitors the state of the bus 602 (signal level and change) and the time relationship between the plurality of signal states. The bus arbiter test 501 is a test program for setting necessary data for each verification module in the test bench 63, collecting necessary output data, and performing functional verification of the bus arbiter 601 in simulation by a logic simulator.

  FIG. 6 is a diagram illustrating an example of the DUT specification of the arbiter to be verified and the DUT specification library of various logic circuits.

  In FIG. 6, Spec.xxx_2 “only one grant signal is hot. Ieg_k = 1 & g_i = 0 (i ≠ k) when k is granted (k∈ {0,1,2,3 })"It is shown. The test item extraction unit 31 analyzes the data structure of each functional specification in the DUT specification 21 to be verified and the various DUT specification libraries 26. As a functional specification having a predetermined approximation degree or more, the aaa_Bus_Arbiter specification on the right side of FIG. Spec.aaa_10 “only one grant signal is hot. Ieg_k = 1 & g_i = 0 (i ≠ k) when k is granted (k∈ {0,1,2,3})” and Spec.aaa_1 “supports master_Ii ( An example in which “0 ≦ i ≦ k)” is extracted is shown.

  FIG. 7 is a diagram illustrating an example of a DUT specification library and a test item library.

  FIG. 7 shows an example in which a DUT test item corresponding to the functional specification extracted by the test item extraction unit 31 is extracted by the correspondence information 28 between the DUT specification and the test item. Number and test item number correspond to each other. In the present embodiment, the test item aaa is picked up, and the following test specification generation, verification module extraction, and test group extraction will be described focusing on the test item aaa.

  In the test item aaa, the summary “check if only one grant signal is hot. Ie g_k = 1 & g_i = 0 (i ≠ k) when k is granted)” means that only one grant signal is 1 (permission) at the same time. It is to check that it becomes. As related modules, bus_master_model, bus_slave_model, and bus_monitor are listed.

  FIG. 8 is a diagram showing an example of the DUT specification to be analyzed in the verification element extraction unit 30 when focusing on the test items shown in FIG.

  In FIG. 8, when the test item to be verified is determined, the test specification generation unit 32, the verification module group extraction unit 33, and the test group generation unit 34 in the verification element extraction unit 30 directly correspond to the DUT specifications shown in the figure. And related DUT specifications.

  Spec.xxx_2 “only one grant signal is hot. Ieg_k = 1 & g_i = 0 (i ≠ k) when k is granted (k∈ {0,1,2,3) of X_Bus_Arbiter specification as directly applicable DUT specification })"It is shown. As related DUT specifications, Spec.xxx_1 “support master0, master1, master2, master3.” Of X_Bus_Arbiter specifications and Spec.yyy_1 “signal path = / system0 /… /… / xbusarb0” of X_Bus_Master0 specifications It is shown.

  FIG. 9 is a diagram illustrating an example of generating test specifications from the test item group 41.

  In FIG. 9, the test specification generating unit 32 generates a test specification in which the constraint condition of the DUT specification shown in FIG. 8 is added to the test item aaa shown in FIG. As a test specification for the DUT corresponding to the test item aaa, the number of bus masters is limited to 4 according to the DUT specification (Spec.xxx_1 of the specification of X_Bus_Arbiter), and the bus type of the DUT (using x_bus) Accordingly, related modules are restricted to the master model x_bus_master_model, slave model x_bus_slave_model, and monitor x_bus_monitor of x_bus.

  Also, as test specification details for test item aaa “Check that bus arbiter is set to 1 (permitted) only one grant signal at the same time”, test step “1. Issue write access from all x_bus_master_model to x_bus_slave_model0 simultaneously with ramdom delay 2. Check if only one grant signal is hot by x_bus_monitor. ”Is shown.

  FIG. 10 is a diagram illustrating an example of extracting the verification module group 43 from the verification library 24.

  In FIG. 10, the verification library 24 includes a verification module related to a_bus in addition to x_bus. The verification module group extraction unit 33 extracts x_bus_master_model, x_bus_slave_model, and x_bus_monitor from the verification library 24 as verification module groups necessary for verification of the test item aaa.

  FIG. 11 is a diagram illustrating a generation example of the test group 44 from the test template group 25.

  In FIG. 11, a test template “grant_signal_for_arbitration” is included as a test template for the test item aaa “the bus arbiter checks that only one grant signal is 1 (permitted) at the same time”. In this embodiment, it is assumed that the test is described using a verification-specific language, and n bus master models from 0 to n-1 simultaneously access the bus slave model with a random delay. The content of performing is described.

  In the test group generation unit 34, a test to which the DUT specification and test specification constraints are added is generated from the test template as a test for verifying the test item aaa. Specifically, the test name is changed to “sys0_x_grant_signal_for_arbitration”, and “x_” is added to the struct name, clock name, and each field name, for example, “clk” is changed to “x_clk”. The number of calls to the function write () to be accessed is changed from n to 4 according to the number of masters of the DUT specification.

  FIG. 12 is a diagram illustrating a grant signal check description example in x_bus_monior.

  In FIG. 12, “x_bus_monitor” describes the check function of “check if only one grant signal is hot”, which is necessary for performing functional verification on the test item aaa, as shown in the test specification of FIG. This is an example. In the present embodiment, the master number is described so as to be able to support a maximum of 16 master numbers in order to be compatible with various DUT specifications in which the number of connected masters varies depending on the specifications. That is, the number of bits of xgrant is 16.

  The contents of the grant signal check include the function bitsum (x: int (bits: 16)) that calculates the arithmetic sum of the values of each bit of the 16-bit signal x. Check that bitsum (xgrant) = 1 in the event “grant”. Further, xgrant is a sample of a DUT signal according to Spec.yyy_1 “signal path = / system0 /... / Xbusarb0” of the X_Bus_Master0 specification of the DUT specification.

  Then, the verification environment construction unit 50 extracts the verification module groups x_bus_master_model, x_bus_slave_model, and x_bus_monitor shown in FIG. 10 according to the test bench configuration shown in FIG. Four instances are instantiated, one x_bus_slave_model0 is instantiated for the slave model, one x_bus_monitor0 is instantiated for the bus monitor, and the test bench 63 is constructed with the base H / W 62 generated as an interface with the DUT, and the simulator is built with the above test Built into the environment, it is possible to execute a test for verifying the function of the test item aaa.

  As described above, the DUT specification 21 to be verified and the various DUT specification libraries 26 that are verification assets are compared to extract individual DUT specifications in the various DUT specification libraries 26 having a predetermined approximation degree or more, and the DUT specifications are extracted. The test items corresponding to the specifications are extracted by referring to the correspondence information 28 indicating the correspondence between the individual DUT specifications in the various DUT specification libraries 26 and the individual test items in the test item library 22. It becomes possible.

  Furthermore, based on the test specification library 27, the verification library 24, and the test template group 25, which are verification assets, a test specification for performing functional verification of the target test item is generated, and necessary verification module groups are extracted. Then, it becomes possible to generate the necessary tests.

  Furthermore, by constructing a verification environment 60 including the DUT 61, the verification module group 43, and the test group 44, it is possible to execute functional verification for the test item.

  To summarize the features of the present embodiment described above, the test item extraction unit 31 compares the DUT specification 21 to be verified with various DUT specification libraries 26, extracts functional specifications having a degree of approximation equal to or higher than a predetermined value, and the functional specifications. Are extracted from the test item group 41. The test specification generation unit 32 generates a test specification 42 by analyzing the relevant verification target DUT specification 21 for each test item in the test item group 41. The verification module group extraction unit 33 analyzes a test item, a test specification, a DUT specification, and a verification library, and extracts a verification module group 43 necessary for functional verification of the DUT. The test group generation unit 34 analyzes test items, test specifications, DUT specifications, and test template groups, and generates a test group 44 necessary for functional verification of the DUT.

  The verification environment construction unit 50 constructs a verification environment 60 by incorporating a test bench 63 and a test group 44 composed of the DUT 61, the base H / W 62 necessary for verification of the verification target DUT, and the extracted verification module group 43. . The coverage analysis unit 68 analyzes the coverage acquired at the time of test execution, determines whether or not a predetermined condition is satisfied, and notifies the test execution control unit 67 of the analysis result. The test execution control unit 67 receives the analysis result of the coverage analysis unit 68, and executes a corresponding test after controlling the constraint conditions and the like when a predetermined coverage condition is not satisfied.

  With the above control, a set of proven functional specifications of DUT, a set of test items, a set of test specifications, verification modules such as parameterized models and monitors, and test templates corresponding to test items can be used effectively. Test items, test specifications, and tests for functional verification of the DUT can be created with high quality and high efficiency. It is also possible to perform necessary and sufficient tests to achieve the verification goal by performing coverage analysis.

  As described above, according to the present embodiment, regarding the functional verification of the DUT, it is assumed that there is a minimum of two design assets including specifications with various DUT results and corresponding test items. Make use and use it effectively. As a result, test items, test specifications, and tests for functional verification of DUT can be created with high quality and high efficiency, and verification man-hour reduction, verification period shortening, and verification quality improvement can be realized at the same time. Has a remarkable effect. Furthermore, with regard to test execution, there is a remarkable effect that high quality and efficiency can be achieved to achieve the verification goal.

[Second Embodiment]
In the second embodiment of the present invention, in contrast to the fact that the first embodiment described above performs dynamic function verification by simulation, static function verification by property check is performed, The configuration of the verification system is different in the point shown in FIG.

  FIG. 13 is a block diagram showing the configuration of the function verification system according to the present embodiment.

  In FIG. 13, a function verification system 100 performs functional verification of a logic circuit, and includes a data input / editing unit 10, a database unit 120, a verification element extraction unit 130, a verification element group 140, a verification environment construction unit 50, and verification. It consists of an environment 160.

  In the present embodiment, each component of the function verification system 100 is stored in a main storage device or an auxiliary storage device on a workstation or PC and functions based on control of the central processing unit. In this embodiment, it is assumed that static function verification is performed by property check.

  The database unit 120 stores electronic data of the verification target DUT specification 21, the test item list 17, the property specification library 18, the property library 19, and the DUT library 29. The verification element extraction unit 130 includes a test item extraction unit 31, a property specification generation unit 35, and a property group generation unit 36. The verification element group 140 includes a test item group 41, a property specification 45, and a property group 46. The verification environment 160 includes a property group 46, a DUT 61, a property checker 66, a coverage analysis unit 68, and a property execution unit 69.

  Other elements of the present embodiment (the data input / editing unit 10, the verification environment construction unit 50, and other components having the same reference numerals) correspond to those of the above-described first embodiment (FIG. 1). Since it is the same, explanation is omitted.

  The test item list 17 is a list (set) of test items whose functions should be verified with respect to the functional specifications of various DUTs. The property specification library 18 is a property specification library of properties whose functions are verified with respect to the functional specifications of the DUT. The property library 19 is a library of property templates (property templates for function verification regarding the functional specifications of the DUT) for various property specifications prepared in advance. The DUT library 29 is a library including information on the following DUT 61.

  The property specification 45 is a property specification extracted in consideration of the constraint condition based on the DUT specification for each test item necessary for functional verification of the DUT. The property group 46 is a set of properties necessary for functional verification of the DUT.

  The property specification generation unit 35 analyzes each verification target DUT specification 21 for each test item of the test item group to be implemented as functional verification of the DUT, and adds each constraint specification of the corresponding DUT specification. Is generated based on the property specification library 18, and a property specification group 45 corresponding to all test item groups is generated.

  The property group generation unit 36 analyzes the property library 19 for each test item of the test item group, extracts a corresponding property template, analyzes the related verification target DUT specification 21 and the property specification 45, and necessary parameters. Are added to the property template, a property to be implemented as function verification of the DUT is generated, this is executed for all test items, and a property group 46 corresponding to the test item group is generated. .

  The verification environment construction unit 50 constructs the following verification environment 60 by combining the verification element groups 40 described above.

  The verification environment 60 includes a property group 46, a DUT 61, a property checker 67, a coverage analysis unit 68, and a property execution control unit 69.

  The property checker 66 is a static verification tool that statically verifies the validity of hardware functions described in a hardware description language or the like based on properties described in a property-dedicated language or the like. The property execution control unit 69 activates the property checker 66 in the verification environment 60 and manages the execution of the property group 46. Also, the property execution control unit 69 receives the analysis result of the coverage analysis unit 68 described below, and executes the corresponding property after controlling the constraint condition and the like when a predetermined coverage condition is not satisfied.

  Whether the coverage analysis unit 68 analyzed the coverage acquired at the time of property execution by the coverage acquisition mechanism described in the corresponding property in relation to the predetermined property item in the property group 46, and satisfied the predetermined condition It is determined whether or not the property execution control unit 69 is notified of the analysis result.

  As described above, according to this embodiment, it is possible to create test items, test specifications, and tests for DUT function verification with high quality and high efficiency, as in the first embodiment described above. It is possible to reduce the verification man-hours, shorten the verification period, and improve the verification quality at the same time, and achieve a remarkable effect that high quality and efficiency can be achieved to achieve the verification goal.

[Other embodiments]
In the first embodiment, the correspondence information 28 indicating the correspondence between the individual DUT specifications in the various DUT specification libraries 26 and the individual test items in the test item library 22 is used, but the correspondence between the DUT specifications and the test items is used. It is not limited to. All or part of DUT specifications, test items, test specifications, verification libraries, and test templates are held in the database unit 20 as correspondence information, and the verification target DUT specifications 21 and individual DUT specifications in various DUT specification libraries 26 are predetermined. Needless to say, in the case of the above approximation, the test specification, verification library, and test template corresponding to the DUT specification may be determined based on the correspondence information.

  Further, in the first embodiment, the functional verification related to the grant signal of the bus arbiter in FIGS. 5 to 12 described above is an example, and the present invention is not limited to this. It goes without saying that the verification element extraction and verification environment construction method described above can be applied to other DUT specifications and test items, and is not limited to this example.

  In the first embodiment, the item identification number: name, outline, and related module name are described as the contents of each item of the test item list. (In the example, “#”) is described so as to be identifiable by the added keyword, but is not limited to this. The test item description format is not limited to the above, and other formats may be used as long as identification is possible for each sub-item, such as a table format or a tag added to each sub-item. Needless to say.

  In the first embodiment, the test item and the test specification are associated by the item identification number and the item name. However, the present invention is not limited to this. The method of handling each item is not limited to the above, and it is needless to say that other formats may be used as long as the item identification code or a predetermined keyword or tag can be identified.

  In the first embodiment, the association between the test item and the DUT specification is analyzed using a keyword. However, the present invention is not limited to this. The analysis of the relationship between the two is not limited to the above, and it is needless to say that other formats may be used as long as the identification code alone or a predetermined tag can be identified.

  In the first embodiment, the DUT specification, test specification, and the like are described in a format close to a natural language for each fine item, but the present invention is not limited to this. Needless to say, those described in a specification description language such as UML (Unified Modeling Language) may be analyzed.

  In the first embodiment, the test specification is generated by adding the constraint condition of the DUT specification to the picked-up test item. However, the present invention is not limited to this. It goes without saying that a test specification template for a test item prepared in advance may be generated by adding a constraint condition of the DUT specification.

  The present invention supplies a software program (flowcharts in FIGS. 3 and 4) for realizing the functions of the above-described embodiments to a computer or CPU, and the computer or CPU reads and executes the supplied program. Can be achieved.

  In this case, the program is directly supplied from a storage medium storing the program, or downloaded from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like. Supplied.

  The form of the program may be in the form of object code, program code executed by an interpreter, script data supplied to an OS (operating system), and the like.

  The present invention also supplies a computer or CPU with a storage medium storing a software program that implements the functions of the above-described embodiments, and the computer or CPU reads and executes the program stored in the storage medium. Can also be achieved.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for storing the program code, for example, ROM, RAM, NV-RAM, floppy (registered trademark) disk, hard disk, optical disk (registered trademark), magneto-optical disk, CD-ROM, MO, CD-R, CD -RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW, magnetic tape, nonvolatile memory card, etc.

  The function of the above-described embodiment is not only by executing the program code read from the computer, but the OS or the like running on the computer performs part or all of the actual processing based on the instruction of the program code. Can also be realized.

  Furthermore, the present invention can be achieved by downloading a software program for realizing the above-described embodiment from a database on a network or a homepage by a communication program, and reading and executing this program.

  The above program can also be supplied by connecting to a homepage on the Internet using a browser of a client computer and downloading the computer program itself or a compressed file including an automatic installation function from the homepage to a storage medium such as a hard disk. .

  The above program distributes a storage medium such as a CD-ROM stored after encrypting the program code to the user, and provides a key for decrypting the encryption from the homepage via the Internet to the user who has cleared a predetermined condition. It can also be provided by downloading the information and using the key information to execute the encrypted program code and install it on the computer.

  The functions of the embodiments described above can also be realized by dividing the program code into a plurality of files and downloading each file from a different home page. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer also constitutes the present invention.

  Further, the functions of the above-described embodiment are obtained by writing a program read from a storage medium into a function expansion board inserted in a computer or a memory provided in a function expansion unit connected to the computer, and It can also be realized by the CPU or MPU provided in the function expansion board or function expansion unit executing part or all of the actual processing based on the instructions of the program.

It is a block diagram which shows the structure of the function verification system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the database part and test item extraction part of a function verification system. It is a flowchart which shows operation | movement of the verification element extraction part and verification environment construction part of a function verification system. FIG. 4 is a continuation of the flowchart of FIG. 3. It is a block diagram which shows the detailed structure of DUT of a function verification system, a test bench, and a test group. It is a figure which shows the example of the DUT specification of the arbiter to be verified, and the DUT specification library of various logic circuits. It is a figure which shows the example of a DUT specification library and a test item library. It is a figure which shows the example of the DUT specification which should be analyzed in a verification element extraction part, when paying attention to the test item shown in FIG. It is a figure which shows the example of a production | generation of the test specification from a test item group. It is a figure which shows the example of extraction of the verification module group from a verification library. It is a figure which shows the example of the production | generation of the test group from a test template. It is a figure which shows the grant signal check description example in x_bus_monior. It is a block diagram which shows the structure of the function verification system which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

1 Functional verification system (supports functional verification system)
20 Database section (corresponding to storage means)
30 verification element extraction unit 31 test item extraction unit (corresponding to test item extraction means)
32 Test specification generator (corresponds to test specification generator)
33 Verification module group extraction unit (corresponding to verification module group extraction means)
34 Test group generation unit (corresponding to test group generation means)
35 Property specification generator (corresponds to property specification generator)
36 Property group generator (corresponds to property group generator)
50 Verification Environment Construction Department (corresponds to construction means)
60 Verification environment 62 Base H / W
67 Test execution control unit (corresponding to execution means)
68 Coverage analysis unit (corresponding to coverage analysis means)
69 Property execution control unit (corresponding to execution means)
301 Individual function specification extraction unit (corresponding to function specification extraction means)
302 Data structure analysis unit (corresponding to analysis means)
303 Keyword extraction unit (corresponds to keyword extraction means)
304 Approximation degree evaluation unit (corresponding to evaluation means)
305 Similar specification extraction unit (corresponding to similar specification extraction means)

Claims (18)

A functional verification system for performing functional verification of a logic circuit,
A storage means for storing a functional specification of a logic circuit to be verified, a set of functional specifications of various logic circuits, and a set of test items to be functionally verified with respect to the functional specifications of the various logic circuits;
The individual functional specifications of the logic circuit to be verified are compared with the individual functional specifications in the set of functional specifications of the various logic circuits, and the functional specifications having a predetermined degree of approximation or more and test items corresponding to the functional specifications A function verification system comprising: test item extraction means for extracting and generating test item groups related to all functional specifications of the logic circuit to be verified. The test item extraction means includes
Functional specification extraction means for analyzing the data structure of the functional specification of the logic circuit and extracting individual functional specifications;
Analyzing means for analyzing the data structure of each functional specification of the extracted logic circuit;
A keyword extracting means for extracting a keyword indicating a feature of the functional specification for each portion of the data structure of the analyzed functional specification;
The function verification system according to claim 1, further comprising: an evaluation unit that evaluates the degree of approximation with respect to the extracted keyword; and a similar specification extraction unit that extracts a functional specification having a predetermined degree of approximation or more.   3. The function verification system according to claim 2, wherein the test item extraction unit registers, in the storage unit, information on a functional specification for which a functional specification having a predetermined degree of approximation or more could not be extracted. The storage means further stores correspondence information between the functional specifications and test items,
The function verification system according to claim 1, wherein the test item extraction unit extracts a test item corresponding to the extracted functional specification based on the correspondence information. The storage means further stores a set of test specifications of test items to be functionally verified with respect to the functional specifications of the logic circuit, a set of verification modules necessary for functional verification, and a set of test templates corresponding to the test items. And
Analyzing the functional specifications of the test item group, the logic circuit to be verified, and generating a test specification group;
A verification module group for analyzing a functional specification of the logic circuit to be verified, the test item group, the test specification group, and a set of the verification modules, and extracting a verification module group necessary for functional verification of the logic circuit to be verified Extraction means;
Test group generation means for analyzing a functional specification of the logic circuit to be verified, the test item group, and a set of the test templates, and generating a test group necessary for functional verification of the logic circuit to be verified. The function verification system according to claim 1.   Construction means for constructing a verification environment in which the verification module group is connected to base hardware necessary for verification of the verification target logic circuit and the verification target logic circuit and the test group are connected to the verification module group. The function verification system according to claim 5, further comprising:   6. The test specification generation unit analyzes a specification of the logic circuit to be verified related to the test item, and generates a test specification to which a constraint condition of the specification of the logic circuit is added. Functional verification system.   The verification module group extraction means analyzes the specification of the logic circuit to be verified and the test specification related to the test item, and installs the part to be installed on the test side and the verification module side during functional verification related to the test item. 6. The parameter information to be set in the verification module at the time of test execution is retained as needed by extracting the necessary verification module from the storage means and separating the portion from the portion to be mounted. Functional verification system.   The test group generation unit extracts a test template corresponding to the test item by analyzing a set of test templates in the storage unit, and relates the specification of the logic circuit to be verified, the test specification, and the parameter information. 9. The function verification system according to claim 5, wherein a test group is generated by analyzing and adding necessary parameters to the test template.   10. The function verification system according to claim 5, further comprising execution means for executing the test group generated by the test group generation means. Coverage analysis means for analyzing coverage of an execution result of the test executed by the execution means,
The test group generation unit generates a test for acquiring coverage for a predetermined test item, and the execution unit controls a test to be executed based on an analysis result of the coverage analysis unit. Item 13. The function verification system according to Item 10. A functional verification system for performing functional verification of a logic circuit,
The functional specification of the logic circuit to be verified, the set of test items to be verified with respect to the functional specifications of the various logic circuits, the set of property specifications of the properties to be verified with respect to the functional specifications of the various logic circuits, and the various logic circuits Storage means for storing a set of property templates for functional verification with respect to the functional specifications of
Compares the individual functional specifications of the logic circuit to be verified with the individual functional specifications in the set of functional specifications of the various logic circuits, and extracts the functional specifications having a degree of approximation equal to or higher than the predetermined value and test items related to the functional specifications. Test item extraction means for generating a test item group related to all functional specifications of the logic circuit to be verified;
Analyzing the functional specifications of the test item group, the logic circuit to be verified, and generating a property specification group;
Property group generation means for analyzing a functional specification of the logic circuit to be verified, the test item group, the property specification group, and a set of the property templates, and generating a property group necessary for functional verification of the logic circuit to be verified A function verification system comprising:   The property specification generation means analyzes a specification of the logic circuit to be verified related to the test item, and generates a property specification to which a constraint condition of the specification of the logic circuit to be verified is added. Item 13. The function verification system according to item 12.   13. The function verification system according to claim 12, further comprising execution means for executing the property group generated by the property group generation means. Control of a function verification system comprising a storage means for storing a functional specification of a logic circuit to be verified, a set of functional specifications of various logic circuits, and a set of test items to be verified with respect to the functional specifications of the various logic circuits A method,
The individual functional specifications of the logic circuit to be verified are compared with the individual functional specifications in the set of functional specifications of the various logic circuits, and the functional specifications having a predetermined degree of approximation or more and test items corresponding to the functional specifications A control method comprising: extracting and generating a test item group related to all functional specifications of the logic circuit to be verified. The functional specification of the logic circuit to be verified, the set of test items to be verified with respect to the functional specifications of the various logic circuits, the set of property specifications of the properties to be verified with respect to the functional specifications of the various logic circuits, and the various logic circuits A function verification system control method comprising a storage means storing a set of property templates for function verification with respect to the functional specifications of
Compares the individual functional specifications of the logic circuit to be verified with the individual functional specifications in the set of functional specifications of the various logic circuits, and extracts the functional specifications having a degree of approximation equal to or higher than the predetermined value and test items related to the functional specifications. And generating a test item group related to all functional specifications of the logic circuit to be verified,
Analyzing the functional specifications of the test item group and the logic circuit to be verified, and generating a property specification group,
Analyzing a set of functional specifications of the logic circuit to be verified, the test item group, the property specification group, and the property template, and generating a property group necessary for functional verification of the logic circuit to be verified Control method to do. Control of a function verification system comprising a storage means for storing a functional specification of a logic circuit to be verified, a set of functional specifications of various logic circuits, and a set of test items to be verified with respect to the functional specifications of the various logic circuits A program for causing a computer to execute a method,
A module for comparing individual functional specifications of the logic circuit to be verified with individual functional specifications in the set of functional specifications of the various logic circuits;
A module that extracts a function specification having a degree of approximation equal to or greater than a predetermined value and a test item corresponding to the function specification;
And a module for generating a test item group relating to all functional specifications of the logic circuit to be verified. The functional specification of the logic circuit to be verified, the set of test items to be verified with respect to the functional specifications of the various logic circuits, the set of property specifications of the properties to be verified with respect to the functional specifications of the various logic circuits, and the various logic circuits A program that causes a computer to execute a control method of a function verification system including a storage unit that stores a set of property templates for function verification with respect to the functional specifications of
Compares the individual functional specifications of the logic circuit to be verified with the individual functional specifications in the set of functional specifications of the various logic circuits, and extracts the functional specifications having a degree of approximation equal to or higher than the predetermined value and test items related to the functional specifications. A module for generating a test item group related to all functional specifications of the logic circuit to be verified;
A module that analyzes the functional specifications of the test item group, the logic circuit to be verified, and generates a property specification group;
A module that analyzes a functional specification of the logic circuit to be verified, the test item group, the property specification group, and a set of the property templates, and generates a property group necessary for functional verification of the logic circuit to be verified. A program characterized by that.

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