JP2006190085A - Modeling method and design method for digital circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance simulation speed, to improve readability and maintenability of a source code so as to shorten a design period, and to inspect for errors in a design stage by a means other than the simulation. <P>SOLUTION: By elimination of bit width designation from RTL (register transfer level) description, the simulation speed is increased, and the readability and maintenability are improved. A means for automatic conversion from RTL without bit width designation to RTL with bit width designation is provided to automate a process for bit width decision and shorten the design period. Furthermore, the source code is made operable with an existing logic synthesis tool and simulator. A means for manually designating a bit width is provided, and a means which automatically collates the manually designated bit width with an automatically estimated bit width and issues an alert if any contradiction therebetween is found. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital circuit modeling method and design method, and more particularly, to a register transfer level (RTL) description, logic synthesis, and verification method.

  RTL descriptions are widely used as inputs for digital circuit simulators and logic synthesis devices. VHDL, Verilog-HDL, and C language-based SystemC, which are known as hardware description languages, are widely used as RTL descriptions. However, due to the language specification of the hardware description language or due to restrictions of the logic synthesis apparatus, it is necessary to assign a bit width to all variables in advance.

FIG. 11 shows a flowchart of a conventional design example.
Of the steps in the design flow of FIG. 11, step 102 and step 103 are the center of circuit design.

  In this conventional design flow, step 103 must be performed manually. It is necessary for humans to carefully consider the state transition rule and the bit width definition so that no contradiction arises. Therefore, an exchange occurs between step 102 and step 103. Also, errors are likely to occur during this process. In addition, it is necessary to define a variable that holds an intermediate result of the calculation. In this case as well, it is necessary for a human to calculate the range of values that the intermediate result can take and assign a necessary minimum bit width. Unexpected behavior will occur if the bit width definition is too small than is actually required. Moreover, neither circuit simulators nor logic synthesis devices warn of such errors.

  The circuit simulator handles quaternary logic as standard. That is, 0, 1, X (undefined), and Z (high impedance). However, there are not so many parts that require quaternary logic especially in the early design stage. The calculation of quaternary logic takes more than twice as long as a normal operation. Also, arithmetic processing is necessary to limit the bit width. For this reason, the simulation of the RTL description has an advantage that the operation of the hardware can be completely simulated, but there is also a disadvantage that it takes time due to an unnecessarily arithmetic processing.

  Therefore, there is a method for automatically calculating the bit width by analyzing the logical structure of the circuit while minimizing the manual supply of the bit width information (for example, Patent Document 1).

  There is also a method of determining the bit width immediately before behavioral synthesis (for example, Patent Document 2). In Patent Document 2, by describing the hardware using the C language with an operation description having a higher abstraction level than the RTL, the C language bit width specification (16, 32, or 64 bits) is directly reflected in the hardware. Therefore, it points out the problem that the bit becomes redundant, and states that it is possible to use a non-redundant bit width by using C ++.

JP-A-5-54098 JP 2003-216678 A (see page 13, FIG. 9, FIG. 10)

However, according to the method of Patent Document 1, an input bit width, a bit width of a storage element, and a bit width calculation library are required. The method of Patent Document 1 is a method of estimating from the bit width of a variable, and is not a method of strictly analyzing the domain of the variable. Therefore, even if an n-bit variable does not take all 2 ⁿ types of cases, estimation is performed. The result can be wasted.

  Patent Document 2 does not provide means for automatically determining a bit width without redundancy.

  Therefore, an object of the present invention is to provide a digital circuit modeling method, a bit width determination method, a digital circuit design device, and a bit width conversion device that can simplify RTL description and increase the simulation speed. There is to do.

  Another object of the present invention is to provide a digital circuit modeling method and design method capable of automating the process for determining the bit width and shortening the design period.

  The present invention is a digital circuit modeling method, characterized in that the source code of a digital circuit is described at a register transfer level including a variable whose bit width is undefined.

  The variable whose bit width is uncertain may be simulated by aligning the bit width to the same width.

  The present invention is a digital circuit design method, in which a state transition rule defining step for describing a source code of a digital circuit at a register transfer level including a variable whose bit width is undefined, and after compiling the source code, A simulation step for performing a simulation for confirming circuit operation, and determining the bit widths of the plurality of variables to desired values based on the source code that has undergone the simulation step, and having the variables for which the bit widths have been determined A bit width defining step for generating a source code; and a logic synthesis step for performing logic synthesis based on the source code having the variable for which the bit width is determined, and converting the logic into a gate level digital circuit. And

  In the state transition rule definition step, among the variables, a variable having true and false binary logic may have a bit width of 1 bit, and variables other than the variable may have a bit width of multiple bits.

  The bit width defining step is based on a parsing step for parsing a digital circuit source code described at the register transfer level including a variable whose bit width is undefined, and a parsing result of the parsing An initial state and a state transition function extracting step for extracting an initial state of a register in the source code and a state transition function of the source code, and the state transition based on the state of the input signal and the initial state A state search step of repeatedly performing image calculation by a function until the state set does not change, a bit width allocation step of determining a bit width of the variable to a desired value based on the result of the image calculation, and the parsing Based on the analysis result and the bit width information obtained from the bit width allocation step, the variable for which the bit width is determined It may include a source code output step for generating a source code.

  A step of comparing the bit width value determined in the bit width defining step with a predetermined bit width value and verifying whether or not the two values match by the comparison may be provided.

  The present invention relates to a method for determining a bit width, a parsing step for performing parsing on a source code of a digital circuit described in RTL including a variable whose bit width is not defined, and an analysis result of the parsing Based on the initial state of the register in the source code and the initial state and state transition function extracting step for extracting the state transition function of the source code, based on the state of the input signal and the initial state, A state search step of repeatedly performing image calculation by a state transition function until the state set does not change, a bit width allocation step of determining a bit width of the variable to a desired value based on the result of the image calculation, and the syntax Based on the analysis result of the analysis and the bit width information obtained from the bit width assignment step, the source having the variable for which the bit width has been determined. Characterized in that comprises a source code output step for generating a Sukodo.

  Means for comparing the value of the bit width determined by the bit width defining means with the value of the bit width specified in advance and verifying whether the two values match by the comparison may be provided.

  The present invention provides a program capable of executing the above-described bit width determination method by a computer.

  The present invention provides a computer-readable recording medium that records the above-described program executed by a computer.

  The present invention relates to a logic synthesis method, a parsing step for parsing a source code of a digital circuit described at a register transfer level including a variable whose bit width is undefined, and an analysis of the parsing Based on the result, the initial state of the register in the source code and the state transition function extraction step for extracting the state transition function of the source code, based on the state of the input signal and the initial state, A state search step of repeatedly performing image calculation by the state transition function until a state set does not change; a bit width allocation step of determining a bit width of the variable to a desired value based on a result of the image calculation; Based on the analysis result of the syntax analysis and the bit width information obtained from the bit width allocation step, the variable whose bit width is determined A source code output step of generating a source code to be performed, and a logic synthesis step of performing a logic synthesis based on the source code having the variable whose bit width is determined and converting it into a gate level digital circuit. Features.

  The present invention provides a program capable of executing the above-described logic synthesis method by a computer.

  The present invention provides a computer-readable recording medium that records the above-described program executed by a computer.

  The present invention relates to a bit width conversion apparatus, a syntax analysis means for performing syntax analysis on a source code of a digital circuit described in RTL including a variable whose bit width is not defined, and an analysis result of the syntax analysis. Based on the initial state of the register in the source code and the state transition function extracting means for extracting the state transition function of the source code, and based on the state of the input signal and the initial state, State search means for repeatedly performing image calculation by a state transition function until the state set no longer changes, bit width assignment means for determining a bit width of the variable to a desired value based on the result of the image calculation, and the syntax Based on the analysis result of the analysis and the bit width information obtained from the bit width allocating means, a source code having a variable whose bit width is determined is generated. Characterized in that comprises an Sukodo output means.

  Means for comparing the value of the bit width determined by the bit width defining means with the value of the bit width specified in advance and verifying whether the two values match by the comparison may be provided.

  The present invention provides a logic synthesis apparatus comprising the bit width conversion apparatus described above.

  According to the present invention, the state transition rules are defined, and based on the source code that has undergone the simulation step, the bit widths of a plurality of variables are respectively determined as desired values, and the source code having the variables for which the bit widths are determined Is generated and converted into a gate-level digital circuit by performing logic synthesis based on the source code having a variable whose bit width is determined, so that the description is simpler than the RTL description specifying the bit width. In addition, since the level of abstraction is high, the simulation speed can be increased, and the same numerical strictness as when the bit width is specified can be maintained. Therefore, maintainability can be improved, the design period can be shortened, and errors at the design stage can be inspected by a method other than simulation.

  Also, according to the present invention, the RTL that does not specify the bit width of each variable is defined, and the conventional RTL description that specifies the bit width from the RTL description that does not specify the bit width is applied. It is possible to eliminate the process of designating the bit width of the variable with the action description having a high abstraction level in the process further upstream than the RTL.

  Furthermore, according to the present invention, even when the bit width of the input has to be changed, the bit widths of all the variables can be automatically adjusted to the optimum values in accordance with the change, and necessary information can be input. Only the state set and the initial state set can eliminate the bit width of the storage element and the bit width calculation library.

  Furthermore, according to the present invention, when the bit width of the storage element is specified in advance, it is possible to provide a function for checking whether there is a contradiction with the bit width estimated from the state transition rule. Therefore, it is possible to estimate a bit width having a small redundancy compared to an estimation method in which only the bit width is specified.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First example]
A first embodiment of the present invention will be described with reference to FIGS.
(Constitution)
FIG. 1 shows a configuration of a bit width conversion apparatus 1 according to the present invention.

  The apparatus 1 includes a bit width definition unit 4, a logic synthesis unit 5, and a verification unit 6. Other configurations include a CPU 10 that performs overall control of the entire apparatus, a ROM 11 that stores a main control program, a RAM 12 that stores arithmetic processing and a control program according to the present invention, a data input / output unit 13, and the like. It also has.

  The bit width defining unit 4 determines the bit widths of the variables whose bit width is not defined based on the source code including the variables whose bit width is undefined after the simulation step, and the bit width is determined. It has a function to generate source code having variables.

  The logic synthesis unit 5 has a function of performing logic synthesis based on a source code having a variable whose bit width is determined and converting it into a gate level digital circuit.

  The verification unit 6 compares the value of the bit width determined by the bit width definition unit 4 with the value of the bit width specified in advance, and verifies whether they match. In addition, this verification part 6 is arbitrarily equipped according to the necessity of a system configuration.

(Operation)
Here, a digital circuit modeling method will be described.
In this example, RTL description is performed using C ++ language, but the present invention does not limit the language used.

FIG. 2 is a flowchart showing a digital circuit modeling method according to the present invention.
First, in the state transition rule definition 202 step, the source code of the digital circuit is described in RTL (Register Transfer Level, register transfer level) including a variable whose bit width is undefined. In this step, it is not necessary to carry out in parallel with the variable bit width definition 204 found in the conventional method, and there is no need to be aware of the bit width. The design without regard to bit width is as follows.

  Here, in the process of defining the state transition rule in step 202, among variables, a variable that takes true and false binary logic has a bit width of 1 bit, and other variables have a bit width of multiple bits. .

  For example, when RTL is described in C ++, when declaring a variable, a variable that clearly takes only two values, “true” or “false”, is declared as a “bool” type, and otherwise, it is declared as an “int” type. Thus, a variable declared as an int type depends on the specification of the C ++ compiler, but many compilers secure 32 bits.

  When describing RTL in C ++, there are not many cases where it is necessary to be aware of the bit width of a variable declared with an int type. When describing state transition rules in RTL, the design is based on the assumption that in most cases the bit width is unlimited. It can be performed.

  If it is likely to exceed 32 bits, the 64-bit type (_int64 type when using Microsoft Visual C ++) is used. By using the int type, the calculation is performed with the bit width most suitable for the CPU used for the simulation, so that the simulation can be performed at high speed.

  In the simulation process of step 203, after compiling the source code, a simulation for confirming the circuit operation is performed. For example, a circuit described in C ++ creates an execution image by compiling with a normal C ++ compiler, and executes a simulation without determining the bit width.

  If a simulation is performed and correct operation is obtained, the apparatus 1 is used to execute the variable bit width defining step of step 204.

  Based on the source code that has undergone the simulation step, the bit widths of the plurality of variables are respectively determined as desired values, and source code including the variables for which the bit widths are determined is generated. For example, the source code described in the state where the bit width is undefined in C ++ is input, and the RTL source code described in Verilog with all the bit widths specified is output.

  Thereafter, the circuit is converted into a gate level circuit through the logic synthesis process of step 205, and the design is completed.

  The register transfer level (RTL) is an abstraction level at which a circuit is described as a synchronous transfer between functional units such as a multiplier, an arithmetic logic unit, and a register file.

  The gate level is an abstraction level at which a circuit is described by a combination of AND, OR, NOT, or flip-flop, and is equivalent to a circuit diagram.

<Specific example>
Next, a specific example of a digital circuit modeling method will be described.
Hereinafter, a description will be given in comparison with conventional processing.

  As a specific example, a design example of an infinite impulse response (IIR) digital filter will be described. The language used was SystemC.

  FIG. 3 shows an example of the program 100 corresponding to the flowchart of FIG. 11 of the prior art described above, and compares the design of an infinite impulse response (IIR) digital filter described using SystemC as a language. It is an example shown.

  In the program of FIG. 3, the part corresponding to step 102 of FIG. 11 is the sentence on the 420th to 425th lines.

  Here, arithmetic processing or mapping is performed on the input signal in and the signal zreg representing the internal state, and the obtained value is substituted into zreg as a value representing the next state. This sentence is designated by the 411st line to be driven at the rising edge of the clock signal clk. Therefore, it represents a change in zreg before and after the rising edge of the clock clk, and this corresponds to the state transition rule.

  The portion corresponding to step 103 in FIG. 11 is a sentence on lines 405 to 407, and is a portion declared as sc_uint <10> or sc_uint <20>.

The value that can be taken by the variable zreg representing the state can be a value from 0 to 2 ²⁰ −1 as a result of careful tracing by the designer looking at the sentences in the 420th to 425th lines.

  Therefore, a determination is made that 20 bits are necessary and sufficient to express these values, and a 20-bit unsigned code is declared. Then, since the output variable “out” is obtained by shifting zreg to the right by 10 bits, it can be understood that there is no 10-bit code.

  If the sentence on the 420th to 425th lines is rewritten, the designer again evaluates the range that zreg can take, and if it is determined that the bit width needs to be changed, the bit in the related sentence on the 405th to 407th lines Correct the width.

  Thus, step 102 and step 103 in FIG. 11 have feedback from each other.

  Next, FIG. 4 shows an example of the program 200 corresponding to the flowchart of FIG. 2 according to the present invention, and an infinite impulse response (IIR) digital filter design example described using SystemC as a language. Indicates.

  In the conventional program example of FIG. 3 described above, the variables out and zreg are declared by specifying the bit width and the sign, whereas in the program example of FIG. 4 according to the present invention, all are declared in the int type.

  In the program of FIG. 4, the process corresponding to step 202 of FIG. 2 is a sentence on lines 520 to 525, and formally, there is no change from steps 420 to 425.

  However, in the conventional program of FIG. 3, when the sentence of the 420th to 425th lines, which is the state transition rule, is modified, it may be necessary to modify the bit width of the variable in the sentence of the 405th to 407th lines. On the other hand, in the program of FIG. 4 of the present invention, it is only necessary to correct the sentence on the 520th to 525th lines.

  In the conventional program shown in FIG. 3, if the sentence in the lines 405 to 407 is forgotten to be corrected, an unexpected operation is performed. On the other hand, the program shown in FIG.

  However, since the conventional program of FIG. 3 and the program of FIG. 4 of the present invention both express the digital circuit to be designed and are a C ++ program, they are compiled using an existing C ++ compiler, Can be done with.

  The process of executing the compiled C ++ program is a simulation corresponding to the conventional step 104 in FIG. 11 or the step 203 in FIG. 2 of the present invention.

  Although the program of FIG. 4 of the present invention does not contain bit width information, the same simulation result as that of the conventional program of FIG. 3 in which the bit width is specified can be obtained.

  If the simulation result is analyzed and the expected operation is obtained, the conventional technique goes to the logic synthesis step of step 105 in FIG. This is converted to the gate level using a commercially available logic synthesis device. There are a number of further steps such as layout until an actual LSI is obtained, but it is omitted because it is not related to the present invention.

  At the end of step 104 in FIG. 11, there is the source code in FIG. 3 that operates correctly, and the bit width is defined for all variables. Logic synthesis apparatuses capable of processing such source code are commercially available.

  On the other hand, there is the source code of FIG. 4 that operates correctly at the end of step 203 of FIG. 2, but out and zreg are not fixed. Existing logic synthesizers either reject the processing or interpret the same as the C ++ compiler and often interpret the int type as signed 32 bits. However, since zreg only needs 20 bits, a wasteful circuit of 12 bits is generated.

  Step 204 of FIG. 2 exists to solve this problem. That is, in step 204, the source code represented by the program of FIG. 4 of the present invention is automatically converted into the conventional program format of FIG. At that time, a necessary and sufficient bit width capable of expressing each variable is automatically determined. The input and output of step 204 is SystemC in this example, but may be output in another language such as Verilog-HDL. Thereby, logic synthesis can be performed by an existing logic synthesis device.

  It is necessary to specify the bit width for the input variable in on the 505th line. This is because in does not depend on any variable, and therefore the range that in can take cannot be estimated. However, if in is connected to the output of another module and the range of the output variable of that module can be estimated, there is no need to specify the bit width in the declaration of in.

[Second example]
A second embodiment of the present invention will be described with reference to FIGS. In addition, about the same part as the 1st example mentioned above, the description is abbreviate | omitted and the same code | symbol is attached | subjected.

(Constitution)
FIG. 5 shows a configuration example of the bit width conversion device 50. The bit width conversion apparatus 50 corresponds to the processing of the bit width defining unit 4 in the digital circuit design apparatus 1 shown in FIG. 1 of the first example.

  The bit width conversion device 50 includes a source code input unit 52 to which a source code 51 whose bit width is not determined, a syntax analysis unit 53, a state transition rule extraction unit 54, a state search unit 55, and a bit width allocation unit. 56, a source code output unit 57 that outputs a source code 62 with a determined bit width, an parse tree storage unit 58, a symbol table storage unit 59, a state transition function storage unit 60, and a reached state set storage unit 61. It consists of.

(Operation)
Next, the operation of the apparatus 50 will be described.
Here, a bit width determination method will be described.

  FIG. 6 is a flowchart showing an example of processing for converting an RTL description not specifying a bit width into an RTL description specifying a bit width.

  The flowchart of FIG. 6 shows details of step 204 in the flowchart of FIG. 2 described above.

  The reason for converting this RTL description that does not specify the bit width to the RTL description that specifies the bit width is that there is no logic synthesis device that can synthesize RTL that does not specify the bit width, so the bit width is specified when performing logic synthesis. This is because the process of step 204 in FIG. 2 for generating the RTL description is required.

  Hereinafter, a procedure for estimating the bit width in the process of generating the RTL specifying the bit width from the RTL not specifying the bit width will be described with reference to FIG.

  What is needed for bit width estimation is the C ++ source code of step 302.

  First, in the process of step 303, syntax analysis is performed on the source code of the digital circuit described in the RTL shown in step 302 including a variable whose bit width is undefined.

  In the process of extracting the initial state and the state transition function in step 304, the initial state of the register in the source code and the state transition function of the source code are extracted based on the analysis result of the syntax analysis.

  Here, the extracted state transition function represents a mapping from a Cartesian product set of the current state and the input state to a state one clock ahead. The initial state of the register immediately after reset is obtained from an assignment statement at the time of reset by designating a reset signal in the source code. If the reset state is not defined, it is obtained from an assignment statement that assigns a constant. If there is no assignment statement that assigns a constant, 0 is set as the initial state.

  In the state search step of step 306, based on the state of the input signal and the initial state, image calculation using the state transition function is repeated until the state set does not change.

  That is, the initial state set definition obtained in step 304 is used as the first reached state set, and an image set obtained by mapping the reached state set with the state transition function is repeatedly added to the reached state set. Continue until the reached state no longer changes.

  In the step 307, as a result of the image calculation of the state search in the step 306, possible states of all the variables are obtained as numerical values. Therefore, a necessary minimum bit width capable of expressing these numerical values is assigned.

  Finally, in the step of outputting the RTL source code with the bit width in step 308, the variable having the bit width determined based on the analysis result of the parsing and the bit width information obtained from the bit width allocation step is included. Generate source code.

For example, the result of parsing the C ++ source code in step 303 and the bit width information assigned in step 307 are combined and output as C ++ source code.
When performing logic synthesis, it may be output as VHDL source code or Verilog source code.

  Here, it is not uncommon for the register to be able to determine the bit width due to specifications. In this case, since the state set can be given in advance, the processing for the state search can be omitted, and the bit widths of all the variables can be estimated at higher speed.

  Even in this case, if a state search is performed, compared with a bit width specified in advance and a warning is issued if they do not match, a verification device corresponding to the verification unit 6 of the first example described above can be obtained. It can also be configured.

  Further, the data output by the present invention can be taken into a logic synthesis device corresponding to the logic synthesis unit 5 of the first example described above.

  That is, the data processed and output in the flowchart of FIG. 6 according to the present invention corresponding to the variable bit width definition process of step 204 of FIG. 2 is taken into the logic synthesis process of step 205 in the flowchart of FIG. Thus, the specification of the conventional logic synthesis device can be expanded so that RTL source code whose bit width is not fixed can be input. As a result, state search and optimization can be performed at the same time, and as shown in this example, logic synthesis can be completed in a short time compared to the conventional method in which the bit width is once determined and then logic synthesis is performed. Can do.

<Specific example>
Next, a specific example of the bit width determination method will be described.
FIG. 7 shows a flowchart of processing for converting a source code including a variable whose bit width is undetermined into a source code whose bit width is all fixed.

  The designer creates source code including a variable whose bit width is uncertain in step 501 shown in FIG. 7 and performs simulation to confirm that it operates as expected (see steps 202 and 203 in FIG. 2). ).

  In the syntax analysis process of step 502 in FIG. 7, the source code of step 501 created through steps 202 and 203 is parsed to generate a parse tree and a symbol table, which are stored in 58 and 59 of FIG.

  For example, the parse tree obtained by syntactically analyzing the sentences in lines 520 to 525 of the program shown in FIG. 4 has a structure as shown in FIG. Similarly, the symbol table generated by parsing the source code of FIG. 4 has a structure as shown in FIG.

  In the clock edge driving function extraction process in step 503 in FIG. 7, the analysis tree stored in the analysis tree storage unit 58 in FIG. 5 is traced, and the functions registered in the symbol table stored in the symbol table storage unit 59 in FIG. A function driven by a clock edge is searched from among them.

  Referring to the examples of FIGS. 8 and 9, first, an item 704 whose type is registered as “module” is extracted from the global symbol table 701.

  The local symbol table 702 belonging to the item 704 is further searched, and the item 706 whose type is registered as “function” is extracted.

  A part corresponding to the sentence on the 510th to 511th lines of the program of FIG. 4 in the analysis tree is searched for an item having the name clock_event of the item 706, and it can be seen that clock_event is registered there.

  Furthermore, since the description in the eleventh line of the program of FIG. 4 indicates that the clock is driven at the rising edge of the clock variable clk, the item 706 is determined as a clock edge driving function.

  In the assignment statement extraction process in step 504 of FIG. 7, all functions determined as clock edge driving functions in the clock edge extraction process in step 503 are searched from the parse tree, and all assignment statements are extracted.

  In the state transition rule extraction process in step 505 in FIG. 7, a part representing the state transition rule is extracted from the analysis tree from the source code, and data suitable for the state search process in the next step 509 is extracted as a state transition function. It converts into a structure and stores it in the state transition function storage part 60 of FIG.

  In the state variable extraction process in step 506 of FIG. 7, the type registered as “variable” is extracted from the local symbol table belonging to each module.

  Here, the operation of the state variable extraction process in step 506 will be described with reference to the examples of FIGS.

  First, the item 704 of the variable name IIRFfilter whose type is registered as “module” is selected from the global symbol table 701, and the local symbol table 702 belonging to it is further searched. Since there is an item 705 of zreg registered as a “variable” among the items 702, it is extracted. Next, the assignment statement extracted in step 504 is analyzed to analyze whether zreg appears on the left side. In the program of FIG. 4, the statements on the 521 and 524th lines and the corresponding analysis trees 602 and 603 have zreg appearing on the left side. Rewrite as "state variable". A state variable is a variable that is ultimately assigned to a storage element.

  In the initial state extraction process in step 507 of FIG. 7, the assignment statement extracted in the assignment statement extraction process in step 504 is checked for all the state variables extracted in step 507, and if a constant is substituted, The constant is stored as an initial state set in the reached state set storage unit 61 of FIG. If there are a plurality of constant assignments, all are stored in the reached state set storage unit 61 of FIG. 5 as the initial state set. If there is a signal designated as a “reset signal”, a sentence assigned by the search is searched, and the state set of the right-hand side value is set as the initial state set. However, if the state set of the right-side value is unknown, a warning is issued and 0 is added to the initial state set.

  The “reset signal” is designated by the #pragma command. An example is shown in line 504. If neither constant substitution nor substitution by “reset signal” exists, a warning is issued and only 0 is added to the reached state set storage unit 61 of FIG. 5 as an initial state set. In the example of FIG. 4, the 521st line satisfies both the constant substitution and the substitution by the “reset signal”, so 0 is the initial state set.

  In the dependency relationship analysis process in step 508 of FIG. 7, all assignment statements extracted in the assignment statement extraction process in step 504 are analyzed and stored as a dependency relationship graph.

  FIG. 10 shows a dependency graph of variables appearing in the source code in the program of FIG.

  Since the variable that appears on the left side depends on all the variables that appear on the right side, the dependency is expressed as a dependency branch. In addition, if the assignment statement is in the selection statement, it also depends on the variable that appears in the conditional expression. So add that to your dependencies. In the program example of FIG. 4, zreg is dependent on in because zreg is on the left side of the assignment statement on line 524 and in is on the right side. Furthermore, since the assignment statement on the 524th line is included in the condition selection statement on the 520th line, it also depends on the variable reset in parentheses in the if statement on the 520th line. The 519st line is treated as an assignment in the interpretation of SystemC, and out depends on zreg.

  In the state search process in step 509, the reached state stored in the reached state set storage unit 61 in FIG. 5 is extracted by the state transition rule extraction process in step 505 and stored in the state transition function storage unit 60 in FIG. Mapping is performed using the stored state transition function, and the sum of the image set obtained as a result and the reached state set before mapping is obtained and written back to the reached state set storage unit 61 in FIG. The above process is repeated, and the search is terminated when the reached state set stored in the reached state set storage unit 61 of FIG.

  In some cases, a shortage may occur in the storage area. In this case, the processing is stopped as an error (state explosion).

  Further, the dependency relationship of the variables by the dependency relationship analysis processing in step 508 of FIG. 7 determines the order of the variables for performing the state search when there are a plurality of state variables. That is, the state search is sequentially performed such that the state search is performed from the variable at the root of the dependency relationship, and when the state is determined, the state search is performed for the next rank variable.

  In some cases, the dependency relationship may be a loop. In this case, the state search is performed for the variables in the loop. There is also a method in which all the state variables are collectively searched, and a more accurate state search can be performed, but a necessary storage area increases.

  When the state search process in step 509 in FIG. 7 finishes processing all variables extracted in the state variable extraction process in step 506, all the reached state sets stored in the reached state set storage unit 61 in FIG. The range of possible state variables is recorded.

  In the bit width allocation process in step 510 of FIG. 7, a necessary minimum bit width capable of expressing all possible ranges by analyzing the reached state set stored in the reached state set storage unit 61 of FIG. 5 is assigned.

  In the bit width allocation processing in step 510 of FIG. 7, the variable registered with the type int in the symbol table is rewritten to sc_int <n> or sc_uint <n>.

  In the source code output process in step 511 of FIG. 7, the source code 62 with a determined bit width is output from the symbol table with the determined bit width and the parse tree.

(Comparison with conventional example)
Regarding the bit width determination method, the method of Patent Document 1 needs to give the input, output, and bit width of the storage element in advance. It is also necessary to prepare a library for bit width calculation.

  On the other hand, the present invention only needs to give the input bit width or a range of possible values.

  As for the optimization method, the method of Patent Document 1 is based on the output bit width when the output bit width estimated from the given input and the bit width of the storage element is larger than the predetermined output bit width. This is a method of recalculating the necessary bit width by back calculation.

  On the other hand, the present invention performs a state search from the input bit width and the initial state specified or estimated from the source code, and enumerates all reachable states to accurately determine the range that all variables can take. This is a method of assigning a bit width based on this.

  Since the output depends on the input and state variables, the bit width of the output need not be known. If an output bit width is given, if there is a difference between the estimated bit width and the given bit width, the output variable will overflow or there will be wasted bits. In particular, overflow is a design error. In the method of Patent Document 1, since it is a necessary condition to provide the output bit width, such a mistake cannot be detected.

The method of Patent Document 1 is intended for behavioral description.
On the other hand, the present invention is directed to an RTL description having a lower abstraction level than the behavioral description. The behavioral description is once converted into an RTL description by the behavioral synthesis device.

  On the other hand, according to the present invention, designation of the bit width in the RTL description is not necessary except for some input variables, so that it is not necessary to consider the bit width in the operation description, and the necessity of Patent Document 1 disappears.

It is a block diagram which shows the structure of the bit width conversion apparatus of this invention. 3 is a flowchart illustrating a digital circuit modeling method. It is explanatory drawing which shows an example of the program corresponding to the flowchart of FIG. 11 of a prior art. It is explanatory drawing which shows an example of the program corresponding to the flowchart of FIG. 2 which concerns on this invention. It is a block diagram which shows the example of a process which is the 2nd Embodiment of this invention, and converts into the RTL description which designated the bit width from the RTL description which does not designate the bit width. It is a flowchart which shows the example of a process which converts into the RTL description which designated the bit width from the RTL description which does not designate a bit width. It is a flowchart of the process which converts the source code containing the variable whose bit width is undetermined into the source code where all the bit widths are fixed. FIG. 5 is an explanatory diagram illustrating a structure of an analysis tree obtained by performing syntax analysis on the program sentence of FIG. 4. FIG. 5 is an explanatory diagram showing a structure of a symbol table generated by parsing the source code of FIG. 4. It is explanatory drawing which shows the dependency relation of the variable which appeared in the source code in the program of FIG. It is a flowchart which shows the example of a conventional design.

Explanation of symbols

1 bit width conversion device 4 bit width definition unit 5 logic synthesis unit 6 verification unit 10 CPU
11 ROM
12 RAM
50 bit width conversion device 51 source code 52 source code input unit 53 syntax analysis unit 54 state transition rule extraction unit 55 state search unit 56 bit width allocation unit 57 source code output unit 58 parse tree storage unit 59 symbol table storage unit 60 state transition Function storage 61 Reached state set storage 62 Source code

Claims (16)

A digital circuit modeling method,
A digital circuit modeling method, wherein a source code of a digital circuit is described at a register transfer level including a variable whose bit width is not determined.   The digital circuit modeling method according to claim 1, wherein the simulation is performed with the bit width indefinite variable having the same bit width. A digital circuit design method,
State transition rule definition step describing the source code of the digital circuit at a register transfer level including a variable whose bit width is uncertain,
After compiling the source code, a simulation step for performing a simulation for checking the circuit operation;
A bit width defining step for determining a bit width of each of the plurality of variables to a desired value based on the source code that has undergone the simulation step, and generating a source code having the variable for which the bit width has been determined;
A digital circuit design method comprising: a logic synthesis step of performing a logic synthesis based on a source code having a variable whose bit width is determined and converting it into a gate level digital circuit.   4. The digital circuit design method according to claim 3, wherein the simulation is performed with the bit width indefinite variable having the same bit width. The bit width defining step includes:
A parsing step for performing parsing on the source code of the digital circuit described at the register transfer level including the variable whose bit width is not determined;
An initial state and a state transition function extracting step for extracting an initial state of a register in the source code and a state transition function of the source code based on an analysis result of the parsing;
Based on the state of the input signal and the initial state, a state search step of repeatedly performing image calculation by the state transition function until the state set no longer changes,
A bit width assignment step for determining a bit width of the variable to a desired value based on the result of the image calculation;
A source code output step for generating a source code having a variable whose bit width is determined based on the analysis result of the parsing and information on the bit width obtained from the bit width assignment step;
The digital circuit design method according to claim 3, further comprising: The method further comprises the step of comparing the bit width value determined in the bit width defining step with a predetermined bit width value and verifying whether the two values match by the comparison. 6. The digital circuit designing method according to claim 3, wherein the digital circuit is designed. A bit width determination method,
A parsing step for parsing the source code of a digital circuit described at a register transfer level including a variable whose bit width is uncertain,
An initial state and a state transition function extracting step for extracting an initial state of a register in the source code and a state transition function of the source code based on an analysis result of the parsing;
Based on the state of the input signal and the initial state, a state search step of repeatedly performing image calculation by the state transition function until the state set no longer changes,
A bit width assignment step for determining a bit width of the variable to a desired value based on the result of the image calculation;
A source code output step for generating a source code having a variable for which the bit width is determined based on the analysis result of the parsing and the bit width information obtained from the bit width assignment step. How to determine the bit width. Comparing a bit width value determined by the bit width defining means with a bit width value designated in advance, and means for verifying whether the two values match by the comparison The bit width determination method according to claim 7.   A program capable of executing the bit width determination method according to claim 8 by a computer.   A computer-readable recording medium having recorded thereon the program according to claim 9 executed by a computer. A logic synthesis method,
A parsing step for parsing a digital circuit source code described at a register transfer level including a variable whose bit width is undefined;
An initial state and a state transition function extracting step for extracting an initial state of a register in the source code and a state transition function of the source code based on an analysis result of the parsing;
Based on the state of the input signal and the initial state, a state search step of repeatedly performing image calculation by the state transition function until the state set no longer changes,
A bit width assignment step for determining a bit width of the variable to a desired value based on the result of the image calculation;
A source code output step for generating a source code having a variable whose bit width is determined based on the analysis result of the parsing and information on the bit width obtained from the bit width assignment step;
A logic synthesis method comprising: a logic synthesis step of performing logic synthesis based on a source code having a variable whose bit width is determined and converting it into a gate level digital circuit.   A program capable of executing the logic synthesis method according to claim 11 by a computer.   A computer-readable recording medium having recorded thereon the program according to claim 12 executed by a computer. A bit width converter,
Parsing means for parsing the source code of a digital circuit described at a register transfer level including a variable whose bit width is undefined,
An initial state and state transition function extracting means for extracting an initial state of a register in the source code and a state transition function of the source code based on an analysis result of the syntax analysis;
Based on the state of the input signal and the initial state, state search means for repeatedly performing image calculation by the state transition function until the state set no longer changes,
A bit width allocating means for determining a bit width of the variable to a desired value based on a result of the image calculation;
Source code output means for generating source code having a variable whose bit width is determined based on the analysis result of the syntax analysis and the bit width information obtained from the bit width allocation means. Bit width conversion device. Comparing a bit width value determined by the bit width defining means with a bit width value designated in advance, and means for verifying whether the two values match by the comparison The bit width conversion device according to claim 14. 16. A logic synthesis apparatus comprising the bit width conversion apparatus according to claim 14.

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