JPH0778195A - Data updating system in circuit design cad - Google Patents

Abstract

PURPOSE:To automatically reflect the updating information of a circuit logic master file without lacking information added to an updated simulation file in respect to a data updating system for a circuit logic simulation file prepared by a circuit design CAD. CONSTITUTION:A data updating part 1 prepares a pin table for an updated circuit from an updated circuit logic master file 2 updated in accordance with a change in circuit logic, retrieves the pin table corresponding to a scanning pin in an unupdated old simulation file 3, and at the time of detecting a pin matching with the contents of the pin table by the retrieval, the pin information is stored in a new simulation file 5 for simulating updated circuit logic. Matching/unmatching results based upon retrieval are marked and data corresponding to the existence of a mark in the pin table are stored in the file 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data updating method in CAD for circuit design. In recent years, logic design of digital circuits such as LSI has come to be generally performed by CAD (Computer Aided Design).
In this circuit design CAD, a circuit logic master file is created, and a simulation master file used to verify the circuit is also created. However,
The circuit logic master file was updated due to circuit design changes, etc., and it was necessary to reflect the updated contents in the simulation master file.

[0002]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional example. In circuit design, various files are created for each process. Figure 8
A. In the example shown in (1), a circuit logic master file MF having all information for creating an actual LSI circuit and board is created by the circuit logic design 80 by CAD. Simulation is required to verify the designed circuit operation. Therefore, the simulation file (SF) creation 81 is performed by the simulation file creation program. Next, in addition to the information for simulation, the designer manually inputs information that is not in the circuit logic master file. The input information is information for displaying the state of the circuit to be simulated on the screen, such as the name of each circuit terminal, the display position of the terminal, a comment, etc., and the specifications of the designed circuit. Input is performed by referring to the table that represents.

A simulation master file SMF containing the data thus input is created, and a simulation 83 for generating an output state corresponding to the input condition while observing the display screen is performed using this simulation master file SMF. The result 84 of whether the result of this simulation is correct is given, and if it is correct, the process ends. If it is not correct, the cause is analyzed and work such as reworking the circuit logic is performed.

FIG. 9 shows an example of a simulation of a digital logic circuit. By simulation master file SM
When F is created, the simulation system of the computer simulates while viewing the screen of the graphic terminal. In this case, names (or numbers) are set for a large number of input terminals (or pins) included in the designed digital logic circuit, intermediate terminals between the circuits, and output terminals (pins).

Reference numeral 90 in FIG. 9 is an example of a digital logic circuit, and it is assumed that three terminal numbers of an input terminal (1), an intermediate terminal (2) and an output terminal (3) are set as terminal numbers. Simulation is performed by scanning the electrical states of the terminals between circuits and the output terminals when an electrical signal that changes with time is given to the input terminals of such terminals. In the case of FIG. 9, a state 92 at arbitrary time and time series information 93 are displayed on the screen of the graphic terminal as shown in a display example 91. The time-series information 93 displays information that changes the signals of the terminals (1) to (3) of the digital logic circuit at regular time intervals, and when the state of the input terminal is changed, the information at the corresponding time is displayed. Each state of the intermediate terminal and output terminal is displayed.

The state 92 displays the signal state of each terminal at any designated time point in the time series information 93. In the display example 91 of the figure, the terminal (1) is at a physically high level (H) at a specified time, the terminal (2) is at a logical “1”, and the terminal (3) is at a logical “0”. is there. By identifying these states, it is possible to evaluate whether or not the content of the logic design has the expected function.

A simulation is performed by scanning (identifying) the electrical states of the terminals between the circuits and the output terminals when an electrical signal that changes with time is given to a designated input terminal among them.

When the scheduled result cannot be obtained by the simulation as described above, the circuit logic design is reworked and the circuit logic master file MF is changed. Further, the circuit logic master file MF is also updated by improving the circuit or adding functions.

FIG. 8B. Is an example when the circuit logic master file is updated.
A. The circuit logic master file MF shown in is updated to create an updated circuit logic master file MF ′. When performing a simulation for this update circuit logic master file MF ′, a simulation file creation 86 is performed for the update circuit logic master file MF ′.
Is executed. As a result, the updated simulation file SF 'is obtained. Next, for the update simulation file SF ′, the above A. It is necessary to input data manually as in 83. Thus, the updated simulation master file SMF 'is obtained, and the simulation is executed on this file.

[0010]

As described above, it is necessary to reflect the contents of the circuit logic master file in the simulation master file every time the circuit logic master file is updated according to the change of the circuit. When updated, a simulation file is created using the updated circuit logic master file, so the data manually input in the simulation master file (SMF) before update must be manually input again by the designer. . Therefore, there is a problem that not only the designer is burdened, but also the work takes time.

The present invention provides a data updating method in a circuit design CAD which can automatically reflect the update information of the circuit logic master file in the simulation master file before updating without losing the information added for the simulation. The purpose is to do.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a data update part of a simulation file, 2 is an updated circuit logic master file that holds updated circuit logic data, and 3 is an old (before update) simulation file used for simulating circuit logic before update. , 4 is a pin list of the updated circuit created by taking out the scanning pins from the updated circuit logic master file, and 5 is a new (updated) simulation file created by the present invention. The scanning pins are pins that are displayed (scanned) when a circuit simulation is performed.

In the data updating unit 1, 10 is an updated pin list creating means for creating the scanning pins of the updated circuit,
Reference numeral 11 is an updated pin list search means, 12 is a pin data update storage means, 13 is a pin list mark means, and 14 is a pin list selection storage means.

According to the present invention, after updating the circuit logic file,
Create a circuit pin list based on the updated contents, search the contents of the pin list corresponding to the pins of the old simulation file, set the update data in the new simulation file according to the correspondence relationship, and update The simulation file is updated by selecting the one included only in the selected circuit logic and outputting it to the new simulation file.

[0015]

The updated circuit logic master file 2 stores circuit logic data which is modified from the previous circuit logic by improvements or addition of functions. When the data updating unit 1 is activated, the updated pin list creating means 10 is driven to extract the scanning pins in the updated circuit logic master file 2 and create the updated pin list 4 of the updated circuit. Next, when the updated pin list search means 11 is driven, for each of the many pins for scanning in the old simulation file 3 in which the data for simulating the circuit logic before the update is stored, Search the pin list 4 for the same. The pin data update storage unit 12 is driven according to each result of this search operation, and if the matching pin is in the pin list 4, it is checked whether or not there is a change in the data related to that pin (the information necessary for checking is The pin list 4 of the circuit after the update has), if there is a change, the data is updated and stored in the new simulation file 5, and if there is no change, the pin data of the old simulation file is stored in the new simulation file 5. To do. In addition to this storing operation, a mark is added to the corresponding pin data in the pin list 4. If there is no matching pin in the pin list 4, add a mark indicating that it is a deleted pin and use the new simulation file 5
To store.

Thus, the old simulation file 3
When the searching and storing operations for all the scanning pins of (3) are completed, the unmarked pins are selected from the pin list 4 and output to the new simulation file 5. As a result, the new simulation file 5 stores the simulation file corresponding to the updated circuit logic master file 2, and the information added when the old simulation file 3 is created can be reflected. Therefore, it is not necessary to manually add to the new simulation file 5 the same information that was added when the old simulation file was created.

[0017]

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a processing flow chart of the embodiment.

In FIG. 2, reference numeral 20 is a new circuit logic master file (corresponding to 2 in FIG. 1) composed of 20a and 20b, and 20a is a layout of components (LSI) mounted on each board (printed circuit board). Is stored in the board data, and 20b is LSI data formed by information of scanning pins of each LSI mounted on the board. Reference numeral 21 is an old simulation file (corresponding to 3 in FIG. 1), and 22 is a processing device. The processing device 22 includes a CPU 23 and a memory 2.
4 and the like, a program is stored in the memory 24, data to be processed is read from each file, and a pin list (corresponding to 4 in FIG. 1) created by the present invention is stored. To be done. 25 is a new simulation file (5 in FIG. 1) in which the updated simulation data corresponding to the new circuit logic master file is stored.
It corresponds to).

The processing flow of the embodiment shown in FIG. 3 is executed by the configuration of FIG. FIG. 3 will be described with reference to specific examples of circuit logic designs shown in FIGS. Figure 4 shows an example of board mounting after design change.
It is assumed that various types of LSIs 1 to 5 are mounted as shown in the figure.

FIG. 5 shows the data of the new circuit logic master file (20 in FIG. 2) corresponding to the configuration of FIG.
Is an example of board data (20a in FIG. 2), B. Are examples of LSI data, and only some of them are shown.

FIG. 5A. In the board data of
“11” and “L12” represent component numbers, respectively, and represent the same type of LSI, “LSI1”.
“L2” represents an LSI of the type “LSI2”. Similarly, "L3" is an L type of "LSI3".
It represents SI, and "L41" and "L" (not shown)
42 "represents the same type of LSI, LSI4.

B. of FIG. Shows the pin names (pin numbers) for scanning in each LSI, and in the case of LSI1,
It has three pins "A1", "A2", and "A4". In the case of LSI2 and LSI3, "B1", "B2",
This means that three scanning pins "B3" are provided.

In FIG. 3, first, the used LSI is acquired from the logic master file of the board, and a list thereof is created (S1 in FIG. 3). A list of this LSI is shown in FIG. Created using the example board data shown in. Each LS is created using the LSI list created next.
The data of I is obtained (S2 in FIG. 3). An example of the data relating to the pins in the data of this LSI is shown in FIG. Is shown in.

A list of scanning pins of each LSI is created using this LSI data. At this time, the LSI identification name is added to the pin name (S3 in FIG. 3). next,
It is determined whether all the LSIs on the board have been processed (at step S4).

FIG. 6 shows a concrete example of scanning pin comparison and creation of a new master file. The contents of the scanning pin list are shown in FIG. 6, and the pin name and its attributes (not shown) are shown.
have. This example is shown in FIG. And B. It is an example created from the data of the circuit logic master file shown in FIG.

Returning to the processing of FIG. 3, when all the LSIs on the board are processed (pin list is created), the scanning pin is acquired from the simulation file before update (21 in FIG. 2) (FIG. 3 S5).

FIG. 6 shows a concrete example of the simulation master file before updating. It is composed of pin names and their attributes, display information entered by the designer, comments and the like (not shown). In step S5 of FIG. 3, one pin (data) is acquired from the top of the pins. After that, it is determined whether or not there is no scanning pin to be acquired (S6 in FIG. 3), and if there is, the acquired scanning pin is searched from the pin list (in FIG. 6) (S7 in FIG. 3). This search will be described using the example of FIG. 6. One pin acquired from the simulation master file before update shown in FIG. 6 is compared with the pin in the pin list shown in to detect whether or not they match. It is to be.

If the pin list is not found by this comparison, the pin is output as a dummy to the new (post-update) simulation file (25 in FIG. 2) (S in FIG. 3).
8). FIG. 6 shows a specific example of the new simulation master file. This includes the name of the pin, the attribute after the change, the display information input by the designer, and the comment information (not shown). In the case of the example of the simulation master file before updating, the pin "L11-A3" does not exist in the scanning pin list shown in, and is output to the new simulation master file as a dummy. In this case, a "?" Mark indicating that it is a dummy (meaning that it has been deleted due to a change in circuit logic) is added to the beginning of the mark.

In step S7 of FIG. 3, when it is determined that the pin list is present, it is checked whether or not there is a change in the attribute of this pin, and if there is a change, it is a new attribute. The attribute is output to the simulation file (21 in FIG. 2) (S9 in FIG. 3), and the pin found in the pin list is marked (S10 in FIG. 3).

In the example of FIG. 6, the pin "L11-A" shown in
1 "," L12-A2 "," L12-A1 "," L12
-A2 "," L2-B1 ", etc. match the pins in the scanning pin list of, so they are directly output to the new simulation master file shown in, and the corresponding pins of the scanning pin list of A mark (a mark of Δ in this example) is added to the beginning.

After executing the above step S8 or S11, the process returns to S5 and the next scanning pin is set to the old (before updating) simulation master file (21 in FIG. 2 and FIG. 6).
From step S7 to step S7 when all the pins are finally processed.
The processing shifts to 11. Here, the unmarked pins are added (marked) from the list and output to the simulation master file.

This processing will be described with reference to the example of FIG. 6. Only the pin data not marked with the mark (marked with Δ in S10 of FIG. 3) is selected from the scanning pin list of and output. Therefore, "L11-A4", "L12-A
4 ”data is output to the new simulation master file, and at that time mark (marked with ○ in this example)
Are added to these pins “L11-A4”, “L12-
"A4" indicates that the pin has been added by changing the circuit logic.

It is not necessary for the designer to manually input attribute data and the like to the new simulation file (25 in FIG. 2) created in this way. FIG. 7 shows an example of simulation of a digital circuit.

FIG. 7A shows a circuit logic configuration before updating, which is assumed to be configured by A, B, C, D, E, and X LSIs on the board as shown in the figure. It is assumed that a simulation master file (representing a part thereof) as shown in (b) is created corresponding to the circuit logic master file representing the configuration of (a). In (b), time-series information about (1), (2), and (3) among many pins included in the configuration of (a) is displayed.

It is assumed that the circuit is modified as shown in (c) with respect to the circuit logic of (a) above. This change is due to the LSI
B and X are deleted. A new circuit logic master file (corresponding to 20 in FIG. 2) having data corresponding to the configuration of (a) thus modified, and (b) before updating
By using the simulation file (corresponding to 21 in FIG. 2) having the pin data of
Simulation file pin (1) and pin (3) in (b)
Although there is no change for the pin (2), since the corresponding pin is not included in the new circuit logic master file (c) for pin (2), it is treated as a dummy (deleted) pin and the pin (2) The time series information is blank.

[0036]

According to the present invention, in a large-scale circuit design, when the designer who performs the circuit design and the person in charge of the simulation are different from each other, the person in charge of changing the circuit logic changes the result of the circuit logic The changed parts of can be automatically reflected in the simulation file, and manual input can be eliminated. Moreover, since the logic can be changed without being aware of the simulation, the work can be made efficient.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block configuration diagram of an embodiment of the present invention.

FIG. 3 is a processing flowchart of the embodiment.

FIG. 4 is a diagram showing a mounting example of a board after a design change.

5 is a diagram showing data of a new circuit logic master file corresponding to the configuration of FIG.

FIG. 6 is a diagram showing a specific example of scanning pin comparison and creation of a new master file.

FIG. 7 is a diagram illustrating an example of simulation of a digital circuit.

FIG. 8 is an explanatory diagram of a conventional example.

FIG. 9 is a diagram illustrating an example of simulation of a digital logic circuit.

[Explanation of symbols]

 1 data update unit 10 updated pin list creation means 11 updated pin list search means 12 pin data update storage means 13 pin list mark means 14 pin list selection storage means 2 updated circuit logic master file 3 old (update Before) Simulation file 4 Pin list of circuit after update 5 New (after update) simulation file

Claims (1)

[Claims] 1. In a data updating method of a simulation file for simulating a circuit logic created by a circuit design CAD, a data updating section updates from a post-update circuit logic master file updated in response to a change in circuit logic. A means for creating a pin list of the subsequent circuit, a means for searching the pin list corresponding to the scanning pin of the old simulation file before update, and a pin matching the pin list by the search. A means for storing the pin information in a new simulation file for updating circuit logic simulation, a means for adding a mark to the pin list to show the result of matching or non-matching by the search, and whether or not there is a mark from the pin list. Means for storing the corresponding data in the new simulation file. A data update method in a circuit design CAD, wherein simulation data corresponding to the updated circuit logic is stored in a file.