JPH03198159A - Logical inspecting device - Google Patents

Abstract

PURPOSE:To perform a logical inspection in a short time and with high accuracy by extracting an input pattern and the expected value of a function block to perform a logical inspection out of the result of the overall function simulation of a circuit held in a storage. CONSTITUTION:The result of the overall function simulation of a circuit containing a function block is stored in a function inspecting result storage 31, and the designation is inputted via an input device 1 to a function block which performs the inspection of the entire circuit. An input/output signal line selection means 21 selects the input and output signal lines of the function block inputted via the device 1. Based on the selecting result of the means 21, an input/output value extracting means 22 extracts the input and output values of the function block out of the storage 31. A logical simulation means 23 performs the logical simulation with the extracted input value and the connection information on the function block used as inputs. Then a comparison means 24 compares the result of simulation with the output value. Thus a logical inspection is carried out in a short time and with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic verification device that performs logic verification of a semiconductor integrated circuit for each functional block of the entire circuit.

[Conventional technology]

FIG. 3 is a block connection diagram showing a conventional logic verification device. In the diagram, 1 is an input device such as a keyboard or a mouse, which is used as an input value for the input signal line of a functional block as shown in FIG. The input cover turn and the expected value as the output value of the output signal line 66 are input to the control section 2. 25 is a pattern editing means for writing the input pattern and expected value of the functional block into the input pattern storage device 33 and the expected value storage device 34; 23 is a pattern editing device for writing circuit connection information from the connection information storage device 32; Logic simulation means 24 reads the input cover patterns and performs a logic simulation; 24 a comparison means 24 reads the expected value from the expected value storage device 34 and compares it with the result of the logic simulation; 4 a CRT or the like for displaying the comparison results. This is the display section.

Further, FIG. 4 is a schematic circuit diagram illustrating the entire circuit of the semiconductor integrated circuit, where 6 is the entire circuit, 61 to 64 are functional blocks constituting the entire circuit 6, and 65 and 66 are shown in FIG.
are an input signal line and an output signal line for one functional block 61.

Next, the operation will be explained according to the flowchart shown in FIG.

First, input patterns and expected values of a functional block whose logic is to be verified are inputted from the input device 1. The pattern editing means 25 edits these input pattern patterns and expected values, and then writes them into the input pattern storage device 33 and the expected value storage device 34, respectively (step 5TI). next,
The circuit connection information is taken out from the connection information storage device 32, the input cover pattern is read out from the input cover pattern storage device 33, and the logic simulation means 23 performs a logic simulation based on the circuit connection information and the input cover pattern (step 5T2). The comparing means compares this logical simulation result with the expected value read from the expected value storage device 34, and displays the result on the display section 4 (step 5T3).

[Problem to be solved by the invention]

Since conventional logic verification devices are configured as described above, it is necessary for the designer to create input patterns and expected values by considering the input/output timing of the functional block to be verified. There were problems such as it was time-consuming and prone to errors.

This invention was made to solve the above problems, and it is a method for extracting input patterns and expected values of functional blocks for logic verification from the results of functional simulation of the entire circuit stored in a storage device. It is an object of the present invention to provide a logic verification device that can perform highly accurate logic verification in a short period of time.

[Means to solve the problem]

The logic verification device according to the present invention stores the results of functional simulation of an entire circuit having functional blocks in a functional verification result storage device, and inputs the input values and output values of the functional blocks to be verified for the entire circuit into an input device. Enter from
The input signal line and output signal line corresponding to the input value and output value inputted from this input device are selected by the input/output signal line selection means, and according to the selection result of the input/output signal line selection means, the function verification result storage device The input value and the output value of the functional block are extracted by the input/output value extraction means, and the logic simulation means performs a logic simulation using the input value extracted by the input/output value extraction means and the connection information as input. The simulation result of the logic simulation means and the output value are compared by a comparison means.

[Effect]

The logic verification device of the present invention, when specifying a functional block inside a circuit to perform logic verification, extracts the input value and output value of the functional block from the result of functional simulation of the entire circuit, and extracts the input value and output value of the functional block, and calculates the circuit connection information of one functional block. Logic verification of circuits such as semiconductor integrated circuits is performed by performing logic simulation using the extracted input values and comparing the results with the output values of the extracted functional blocks.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input device such as a keyboard or mouse, and a functional block 6 as shown in FIG. 4 performs logic verification.
1 is input to the control unit 2. 21 is input/output signal line selection means that reads circuit connection information from the connection information storage device 32, selects the input signal line 65 and output signal line 66 of the function processor 61, and supplies each signal to the input/output value extraction means 22. , 22 extract the values of the input/output signal lines 65 and 66 given from the function verification result storage device 31, and the value of the input signal line 65 (input cover pattern) is stored in the input cover pattern storage device 3.
3, input/output value extraction means for writing the values (expected values) of the output signal line 66 into the expected value storage device 34, and 23 a connection information storage bag! ! Logic simulation means for reading circuit connection information from 32 and input cover patterns from input cover pattern storage device 33 and performing logic simulation;
24 reads the expected value from the expected value storage device 34, compares it with the result of the logic simulation, and displays it on the display unit 4 such as a CRT.
This is a comparison means that displays the comparison results.

Next, the operation will be explained according to the flowchart shown in FIG.

First, when the functional block 61 that performs logic verification is designated by the input device 1 (step 5T4), the input/output signal line selection means 21 selects the input signal line 65 and the output signal line 66 of the functional block 61 (step 5T5). ). Further, according to this selection result, the input/output value extraction means 22 extracts the value of the input signal line 65 (input cover pattern) from the function verification result storage device 31 and writes it into the input cover pattern storage device 33, and also extracts the value of the output signal line 66 ( Expected value) is extracted and written into the expected value storage device i34 (step 5T6).

Next, the circuit connection information of the functional block 61 is read from the connection information storage device 32, and at the same time
The input cover pattern is read from 3 and a logic simulation is performed (step 5T7).

Next, this simulation result and the expected value storage device 34
The comparing means 24 compares the expected value read out from the target value (step 5T8), and displays the result on the display section 4.

In this way, by automatically extracting the input pattern and expected value of the functional block for which logic verification is to be performed by the input/output value extracting means 22, logic verification can be performed in a short time without errors.

〔Effect of the invention〕

As described above, according to the present invention, the results of functional simulation of the entire circuit having functional blocks are held in the functional verification result storage device, and the input values and output values of the functional blocks to be verified for the entire circuit are stored. is input from an input device, the input signal line and output signal line corresponding to the input value and output value input from this input device are selected by the input/output signal line selection means, and according to the selection result of the input/output signal line selection means. , the input value and the output value of the functional block are extracted from the functional verification result storage device by the input/output value extraction means, and the input value and the connection information extracted by the input/output value extraction means are input to the logic simulation means. Since the configuration is configured such that a logic simulation is performed using the logic simulation method and the simulation results of this logic simulation method are compared with the above output value using a comparison means, it is necessary for the designer to create patterns and expected values in consideration of the timing of the functional blocks. This has the effect of eliminating the problem and being able to perform highly accurate logic verification in a short period of time.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram showing a logic verification device according to an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of logic verification by the logic verification device, and FIG. 3 is a block diagram showing a conventional logic verification device. FIG. 4 is a schematic circuit diagram showing the entire circuit to be subjected to logic verification, and FIG. 5 is a flowchart illustrating the operation of conventional logic verification. 1 is an input device, 21 is an input/output signal line selection means, 22 is an input/output value extraction means, 23 is a logic simulation means, 2
4 is a comparison means, 6 is an entire circuit, 61 to 64 are internal functional blocks, 65 is an input signal line, and 66 is an output signal line. In addition, in the figures, the same symbols indicate the same or equivalent parts. Figure 1 Figure 66: Amendment to registration number search procedure (voluntary)

Claims (1)

[Claims] A functional verification result storage device that holds functional simulation results of an overall circuit having functional blocks, an input device that inputs input values and output values of the functional blocks to be verified for the overall circuit, and inputs input from this input device. input/output signal line selection means for selecting input signal lines and output signal lines corresponding to values and output values; and input values of the functional block from the function verification result storage device according to the selection results of the input/output signal line selection means. and an input/output value extraction means for extracting an output value; a logic simulation means for performing a logic simulation using the input value extracted by the input/output value extraction means and the connection information as input; and a simulation result of the logic simulation means. and a comparison means for comparing the output value with the output value.