JPS6295473A - Display device for logic circuit diagram - Google Patents

Abstract

PURPOSE:To display fault information accurately in a short time by providing a logical connection information input means, a fault information input means, a synthesizing means, and a display means. CONSTITUTION:A logic circuit diagram display device 1 is equipped with the logical connection information input means 4 for inputting data from a logical connection information collecting means 2 with respect to a logical circuit to be tested, the fault information input means 5 for inputting fault information set in the object logical circuit from the fault information collecting means 3, the synthesizing means 6 for putting together the logical connection information and fault information inputted from the logical connection information input means 4 and fault information input means 5, and the display means 7 which generates a logical circuit diagram on the basis of the composite logical connection/fault information obtained by the synthesizing means 6 and displays the diagram together with the fault information. Consequently, the time required by an operator to trace the logic circuit diagram on the basis of the fault information is shortened, and the entry of a fault onto the circuit diagram is performed accurately, so the labor is saved and the profitability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit diagram display device for logic circuits, and in particular, generates a logic circuit diagram based on logic connection information and fault information set in the logic circuit, and displays fault information. The present invention relates to a logic circuit diagram display device that displays together with a logic circuit diagram.

(Prior Art) Conventionally, in functional testing of logic circuits, as a method for generating a test pattern that can sufficiently perform a functional test, a failure in 10# stuck-at mode or %11 stuck-at mode is used for the logic circuit under test. A test pattern was created to detect the failure, and a failure simulation method was used to evaluate the extent to which it was detected. As a result of the evaluation, if there are any undetected faults, a test pattern is generated to further detect the undetected faults, a fault simulation is performed and evaluated, and this process is repeated until satisfaction is achieved. It had been.

Regarding such techniques, see, for example, the %LS edited by the Institute of Electronics and Communication Engineers and published by Ohm Publishing in 1984.
Please refer to Part 3, Chapter 2 of I Handbook.

In such a method, the key is how to efficiently create test patterns for detecting undetected faults in a short time and with a small amount of test patterns.

Therefore, it is necessary to find out where the undetected fault exists on the logic circuit under test.The search methods include the location on the logic circuit, whether it is an input-side fault or an output-side fault, and the 10I stuck-at mode. It was necessary to manually trace the logic circuit diagram based on failure information such as whether the failure was in the 111 degeneracy mode or the failure in the 111 degeneracy mode to find the corresponding location.

(Problems to be Solved by the Invention) In the conventional functional test described above, when generating a test pattern that can sufficiently perform a functional test, a test pattern is manually traced on a logic circuit diagram based on failure information. Since it is necessary to find out where an undetected fault exists on the logic circuit under test, it takes a very long time, and it has the disadvantage that it is easy to write it down incorrectly when writing it on the circuit diagram.

An object of the present invention is to generate a logic circuit diagram showing where an undetected fault exists on the logic circuit under test based on the logical connection information and fault information of the logic circuit under test, and to When displayed together, the above drawbacks are removed,
An object of the present invention is to provide a logic circuit diagram display device configured to accurately display failure information in a short time.

(Means for Solving the Problems) A logic circuit diagram display device according to the present invention includes logic connection information input means, failure information input means, synthesis means, and display means.

The logic connection information input means is for inputting logic connection information of the logic circuit under test.

The fault information input means is for inputting fault information set in the logic circuit under test.

The synthesizing means is for synthesizing the logical connection information and the fault information to obtain logical connection/fault information.

The display means is for generating a logic circuit diagram from the logical connection/fault information obtained by the synthesis means and displaying it together with the fault information.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a main part of a logic circuit diagram display device according to the present invention. In FIG. 1, l is a logic circuit diagram display device, 2 is a logic connection information collection means, 3 is a failure information collection means, 4 is a logical connection information input means, 5 is a failure information input means, 6 is a synthesis means, and It is a display means.

In FIG. 1, a logic circuit diagram display device l includes a logic connection information input means 4 for inputting logic connection information collection means 2 of a logic circuit under test, and a failure information collection means 4 for inputting fault information set in the logic circuit under test. a fault information input means 5 for inputting from the means 3; a synthesizing means 6 for synthesizing the logical connection information and fault information input by the logical connection information input means 4 and the fault information input means 5; Generating a logic circuit diagram from the logical connection/fault information synthesized by the synthesis means 6 for synthesizing the logical connection information and the failure information,
A display means 7 is provided for displaying the failure information together with the failure information.

The operation of the logic circuit diagram display device 1 will be explained below.

FIG. 2 is a block diagram showing an example of a logic circuit under test. In Fig. 2, lO~12°15.16 are terminal type elements, 13 is an AND gate, and 14 is an AND/
It is a NAND gate.

The information collected by the logical connection information collection means 2 includes the position on the circuit diagram, the connection relationship between elements, the shape, and x-
Contains information such as the y-coordinate. These pieces of information are input to the logic circuit diagram display device 1 by the logic connection information input means 4.

On the other hand, the failure information collecting means 3 collects failure information of the logic circuit shown in FIG. This fault information includes the location on the logic circuit diagram, whether the fault is on the input side or the output side, pin number, and whether the fault is in %O1 degenerate mode or %1 degenerate mode. This includes the distinction of whether or not it is a failure. These pieces of information are input to the logic circuit diagram display device l by the failure information input means 5.

Synthesis means 6 for synthesizing logical connection information and failure information
For example, it operates according to the following first to fourth procedures to synthesize logical connection information and failure information.

First, in step 1, information for - elements is extracted from the logical connection information.

In the second step 2, the position on the circuit diagram is extracted from the extracted information and compared with the position information in all the failure information. If there is no match as a result of the comparison,
Logical connection/failure information is created assuming that there is no failure information for the corresponding element, and the process returns to step 1. As a result of the comparison, if there is a match, the process goes to the next step 8.

As a rule for describing logical connection information for one element,
Young number! 1 @ describes the first input/first output, the second input/second output, and then the n-th input/m n output. , In the third step 3, the information consisting of the distinction whether the failure is on the input side or the output side and the pin number is extracted from the failure information, and the corresponding logical connection information and failure information are found. and synthesize.

In the fourth step 4, the above steps 1 to 3 are repeated until there is no more logical connection information.

Figures 3 to 5 show logical connection information, failure information,
FIG. 4 is an explanatory diagram summarizing and logical connection/fault information.

To explain the element 10 as an example with reference to FIGS. 1 to 5, item number 8-1 in FIG. 8 is extracted in step 1.

In step 2, the position %OIA' of the element 10 on the circuit diagram is taken out, and failure information having the same position is searched among the failure information shown in FIG.

Therefore, item number 4-1 is sent out. Item number 8-1 in Figure 3
It is determined in step 3 that the circuit diagram information is a description of the first input/first output of the element 10, and at the same time the circuit diagram information of the fourth
It is determined by item number 4-1 in the figure that it is the first output of the element 10. Therefore, logical connection information and fault information are combined to obtain logical connection/fault information for element 10 in FIG. 5.

Thereafter, by repeating steps 1 to 4 in the same manner until there is no more logical connection information, the logical connection information and failure information for elements 10 to 16 are combined, resulting in a result as shown in FIG. Logical connection/fault information is generated.

The display means 7 for generating the logic circuit diagram and displaying it together with the fault information inputs the logic connection/fault information generated by the synthesis means 6 for synthesizing the logic connection information and the fault information. Display logic circuit diagram and fault values on the same screen. Regarding one element, its position on the screen, shape,
The position and failure mode to be displayed on the display means 7 is determined by the X coordinate inside the logical connection/failure information and the value entered in the X coordinate column, and the type of shape is determined by the model name in the shape column. It is determined whether the failure value is displayed on the right side or the left side of the shape depending on whether it is on the input side or the output side of the failure value column.

That is, if a fault value is written on the input side, the fault value is displayed on the left side of the shape, and if a fault value is written on the output side, the fault value is displayed on the right side of the shape.

According to Hata et al., the connection line between each element is determined by the X-coordinate/X-coordinate value of the connected element and its own .

Here, assume that element A1 is connected to element B. At this time, if the difference between the X coordinate of element A and the X coordinate of element B is Δy, then if Δy=Q, then the X coordinate of element/X
Draw a straight line connecting the coordinates and the X coordinate/X coordinate of element B.

If Δy = ±n, draw a straight line from the X coordinate / For example, draw a straight line that bends toward the top of the screen and connects to the X coordinate/X coordinate of element B.

By repeatedly performing the above operations, the logic circuit diagram and the failure information can be displayed together on the same screen.

A logic circuit diagram was created for the logic circuit in Figure 2 based on the logic circuit diagram in Figure 2 and the logical connection/fault information in Figure 5, and displayed on the same screen along with the failure information. An example is shown in FIG.

(Effects of the Invention) As explained above, the present invention provides a logic circuit diagram showing where an undetected fault exists on a logic circuit to be tested based on logical connection information and fault information of the logic circuit to be tested. By generating and displaying the fault information together with the fault information, it is possible to reduce the time it takes to manually trace the logic circuit diagram based on the fault information, and also to write down the fault on the circuit diagram. Since it can be carried out accurately, it has the effect of saving labor and improving economic efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic circuit diagram display device according to the present invention. FIG. 2 is a block diagram showing an example of a logic circuit under test. Figures 8 to 5 show logical connection information, failure information,
FIG. 4 is an explanatory diagram summarizing and logical connection/fault information. FIG. 6 is a diagram of a logic circuit under test created based on FIGS. 2 and 5. l...Logic circuit diagram display device 2...Logic connection information collection means 3...Failure information collection means 4...Logic connection information input means 5...Failure information input means 6...Synthesis means 7 ...Display means 10-12, 15.16-...Terminal type element 13・m-A
ND gate

Claims (1)

[Claims] a logical connection information input means for inputting logical connection information of a logic circuit under test; a failure information input means for inputting fault information set in the logic circuit under test; and the logical connection information and the failure information. and display means for generating a logic circuit diagram from the logical connection/fault information obtained by the synthesizing means and displaying it together with the fault information. A logic circuit diagram display device characterized by: