JPH02294843A - Logical verification device - Google Patents

Abstract

PURPOSE:To shorten the time required to a process for analyzing misdesigning of a logic circuit by outputting the drawing of a noncoincident circuit part after logical verification. CONSTITUTION:A simulation means 1 verifies the validity of the logic circuit to generate the noncoincident point information means 2 of an element where a noncoincident is generated on the logic circuit and an all-signal state value information means 3 which holds the states of all signals on the circuit. A circuit diagram input means 4 generates an element connection information means 6 which holds the connection relation between all elements and all signals on the circuit and a drawing output information means 5 which holds the positions of all the elements and all the signals on the drawing. Further, a noncoincident circuit output means 9 outputs the drawing together with the state values while regarding all signals and elements from the noncoincident element to an input terminal as the noncoincident circuit by using a noncoincident point relative signal state value information means 8 and the drawing output information means 5 which holds drawing output information. Consequently, such a fault that much time is spent for a process which analyzes the misdesigning of the logic circuit after the logical verification can be eliminated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic verification device for logic circuits.

[Conventional technology]

In today's rapidly developing computer society, computers themselves are required to be faster and more efficient. Along with this, elements that are the core elements of computers (in particular, LSIs are shown here) have also become more complex, and the large amount of cost and time required for modifications after LSI manufacture cannot be ignored. For this reason, the efficiency of LSI mounting circuit design has been improved by using a logic verification device that verifies the logical validity of a designed LSI mounting circuit prior to manufacturing the LSI.

Conventional logic verification equipment manually performs the entire process of analyzing design errors in logic circuits that may cause discrepancies between the designed LSI implementation circuit and the circuit obtained according to the functions of the LSI, after performing logic verification. I went there.

[Problem to be solved by the invention]

The above-described conventional logic verification apparatus has the disadvantage that it takes a lot of time to design the logic circuit because the process of analyzing design errors in the logic circuit is performed manually after the logic verification is performed.

[Means to solve the problem]

The logic verification device of the present invention comprises: a circuit diagram input means for inputting circuit diagram information; an element connection information means holding element connection information created by the circuit diagram input means; and a circuit diagram input means created by the circuit diagram input means. a drawing output information means holding drawing output information to be generated; a simulation means for simulating a logic circuit; a mismatch point information means holding mismatch point information created by the simulation means; All signal state value information means holding all signal state value information to be created; mismatch point information held in the mismatch point information means; and element connection information held in the element connection information means. , a mismatch point related signal information creation means for creating all signal information related to the mismatch point using the total signal state value information held in the total signal state value information means; and a mismatch point related signal information creation means. mismatch point related signal state value information means for holding state value information of all signals related to the created mismatch point; drawing output information held in the drawing output information means; and the mismatch point related signal state value information. and mismatch circuit output means for outputting a mismatch circuit based on the mismatch point related signal state value information held in the means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention.

First, the simulation means 1 verifies the validity of the logic circuit, and as a result of the simulation, the mismatch point information means 2 holds the mismatched elements on the logic circuit as mismatch point information, and the All-signal state value information means 3 for holding the state as all-signal state value information is created.

The circuit diagram input means 4 includes an element connection information means 6 which holds the connections of all the elements and all the signals on the circuit as element connection information based on the input circuit diagram information, and an element connection information means 6 for outputting the drawing of the circuit diagram. A drawing output information means 5 is created that holds the positions of each element and each signal on the drawing as drawing output information.

Then, the mismatch point related information creation means 7 uses the mismatch point information means 2 that holds the mismatch point information and the element connection information means 6 that holds the element connection information to determine the mismatch regarding the mismatched elements. The signals and elements are sequentially searched from the element where the mismatch occurs to the input side, and information on all the signals and elements from the element where the mismatch occurs to the input terminal is created. Furthermore, by using the all signal state value information means 3 that holds all signal state value information, all signals and state values from the element where the mismatch occurs to the input terminal are associated, and the input from the element where the mismatch occurs A mismatch-related signal state value information means 8 is created that holds the state values of all signals up to the terminal as mismatch point-related signal state value information.

Further, the mismatch circuit output means 9 can be connected to the mismatch points by using the mismatch point related signal state value information means 8 that holds the mismatch point related signal state value information and the drawing output information means 5 that holds the drawing output information. The position on the drawing is searched for each signal and element, and all signals and elements from the element where the mismatch occurs to the input terminal are output as a mismatch circuit in the form of a drawing with state values.

Next, the operation of this embodiment will be explained using the example circuit diagram of FIG. 2(a) and the example of the flow of information in the circuit diagram example of FIG. 2(b).

In FIG. 2(a), a to c and f to k each represent an element, d and e each represent an input terminal, and A to M each represent a signal connecting between the terminals.

In FIG. 2(b), m represents a discrepancy information means that holds information on discrepancies in simulation results, and n represents an all-signal state value information means that holds state values of all signals in the circuit diagram of simulation results. , p represents a drawing output information means that holds information on all signals and the positions of elements on the drawing (b-3.6 indicates that the position of element b is X coordinate 3, Y coordinate 6), and q is a circuit diagram. represents an element connection information means that holds information on connection relationships of all signals and elements in the disc, r represents mismatch point-related signal state value information that holds state value information of all signals related to the mismatch point, and t represents a mismatch point-related signal state value information that holds state value information of all signals related to the mismatch point. Represents a drawing of a circuit part.

First, the simulation means simulates the circuit shown in FIG. 2(a). As a result, a mismatch point information means m indicating that a mismatch has occurred in the element a;
All signal state value information means n indicating the state values of all signals in the circuit diagram is created.

On the other hand, by inputting the circuit shown in FIG. 2(a) using the circuit diagram input means, a drawing output information means m indicating where all signals and elements are located in the input drawing, and Element connection information means q indicating connection relationships between all signals and elements is created.

Then, the mismatch point related signal information creation means 7 sequentially searches from the element a to the input side using "a"' in the mismatch point information means m and the element connection information 1,000 stages q. That is, according to ``aA-B,C''' in the element connection information means q (this represents that element a inputs signal A and outputs signals B and C. This will be followed hereinafter), Signal A, signal B, and signal C are obtained as signal information related to element a,
Furthermore, the element connection information means q is searched based on the signal B,
By "b-B-D" in the element connection information means q, the signal D is obtained as signal information related to the signal B. Furthermore, the element connection information means q is searched based on the signal C, and the element connection information means q is searched. “c-C-E” in information search means q
”, signal E is obtained as signal information related to signal C. In this way, all signals A, B, C, D, E, from element a where mismatch occurs to input terminals d and e, are searched. I will do it.

Furthermore, the bad values of each of the signals A to E are collected from the total signal status value information means n, and ``A=IB=O, C=O,
A discrepancy point related signal status value information means r is created such that D=O and E=1"°.

The mismatch circuit output means 9 uses the mismatch point related signal state value information means r and the drawing output information means p to output the elements a to e corresponding to each of the signals A to E.
The position on the drawing is searched, and the drawing q of the mismatched circuit portion is output along with the state values of the signals A to E.

〔Effect of the invention〕

As explained above, in the present invention, after performing logic verification,
By outputting a drawing of the mismatched circuit portion, it is possible to significantly reduce the time spent in the process of analyzing design errors in logic circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the logic verification device of the present invention, FIG. 2(a) is a circuit diagram to be subjected to logic verification, and FIG. ) is a flowchart of information when performing logic verification on an example circuit diagram and outputting a drawing of a mismatched circuit part. DESCRIPTION OF SYMBOLS 1...Simulation means, 2...Unmatched point information means, 3...All signal state value information means, 4...Circuit diagram input means, 5...Drawing output information means, 6...Element connection information means, 7... mismatch point related signal information creation means;
8... Mismatch related signal state value information means, 9... Mismatch circuit output means.

Claims (1)

[Scope of Claims] Circuit diagram input means for inputting circuit diagram information; element connection information means for holding element connection information created by the circuit diagram input means; and element connection information created by the circuit diagram input means. A drawing output information means holding drawing output information; a simulation means for simulating a logic circuit; a mismatch point information means holding mismatch point information created by the simulation means; all signal state value information means holding all signal state value information held in the above-mentioned mismatch point information means; mismatch point information held in the mismatch point information means; element connection information held in the element connection information means; mismatch point related signal information creation means for creating all signal information related to the mismatch point based on the total signal state value information held in the total signal state value information means; mismatch point related signal state value information means for holding state value information of all signals related to the mismatch points; drawing output information held in the drawing output information means; 1. A logic verification device comprising: mismatch circuit output means for outputting a mismatch circuit based on held mismatch point related signal state value information.