JPH0512368A - Logic simulation system - Google Patents

Abstract

PURPOSE:To obtain all information which is required to analyze a circuit by performing resimulation by using a pattern which covers all conditions as to a circuit part which causes a noncoincidence after expected value simulation, and outputting all state values of the circuit part which causes the noncoincidence. CONSTITUTION:A simulation part 1 simulates a circuit description 5 by using an input pattern A6 and outputs information 8 on the noncoincidence regarding an expected value 7. A fine tracing part 2 finely traces the circuit description 5 by using the noncoincidence information 8 and outputs input terminal information 9. An input pattern generation part 3 generates the input pattern B10 which covers all the conditions as to circuit part which causes the noncoincidence by using the input terminal information 9. A resimulation part 4 performs the resimulation as to the circuit description 5 by using the input pattern 10 and outputs all state values 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to a logic simulation method for a large scale logic circuit.

[0002]

2. Description of the Related Art In the conventional logic simulation method,
Only the simulation was performed for the set input pattern.

[0003]

In the above-described conventional logic simulation method, it is not possible to obtain all the information necessary for analyzing the cause of the discrepancy with the expected value, so that a lot of man-hours are spent for circuit analysis. ..

[0004]

According to the logic simulation method of the present invention, a simulation section which performs a simulation and an expected value collation for a circuit description using a first input pattern and its expected value, and outputs mismatch information,
Based on the mismatch information output by the simulation unit and the circuit description, a fine trace unit that performs fine trace and outputs input terminal information, and based on the input terminal information output by the fine trace unit, An input pattern creating unit that creates a second input pattern that covers all conditions for the circuit part that is the cause and a circuit part that is the cause of the mismatch by performing simulation again using the created second input pattern. And a re-simulation section that outputs all state values regarding

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment comprises a simulation section 1, a fine trace section 2, an input pattern generation section 3 and a re-simulation section 4.

The simulation unit 1 has an input pattern A6.
Simulate the circuit description 5 using
The disagreement information 8 with the expected value 7 is output. The fine trace unit 2 fine-traces the circuit description 5 using the disagreement information 7 and outputs the input terminal information 9.
The input pattern generation unit 3 uses the input terminal information 9 to create the input pattern B10 for the circuit portion causing the mismatch. The re-simulation unit 4 re-simulates the circuit description 5 using the input pattern B10,
All state value 11 is output.

Next, the processing in this embodiment will be described.

2 to 8 are views showing specific examples of the main part of FIG. 1. FIG. 2 is a circuit description 5, FIG. 3 is an input pattern A6, FIG. 4 is an expected value 7, and FIG. Is an example of mismatch information 8, FIG. 6 is an example of input terminal information 9, FIG. 7 is an example of input pattern B10, and FIG.

First, the simulation unit 1 performs a simulation on the circuit description 5 (see FIG. 2) using the input pattern A6 (see FIG. 3), and the expected value 7 (see FIG. 4).
Compare with. Here, with respect to OUT2, the simulation result (OUT2 = 0,1,0) matches the expected value (OUT2 = 0,1,0), which is in agreement. However, regarding OUT1, the expected value (OUT1 = 0, 0,
0), the simulation result (OUT1 = 0,
1, 0), and they do not match. As a result, OUT1 is output as the mismatch information 8 (see FIG. 5).

The fine trace section 2 fine-traces the circuit description 5 by using the mismatch information 8 and, as the input terminal information 9 (see FIG. 6), all the input terminals (IN1, IN1, of the circuit portion causing the mismatch). (IN2, IN3)
Is output.

The input pattern generator 3 uses the input terminal information 9 to create an input pattern B10 (see FIG. 7) that covers all the conditions with respect to the circuit portion causing the mismatch.

The re-simulation unit 4 uses the input pattern B
10 is used to re-simulate the circuit description 5, and the total state value 11 for the circuit portion causing the mismatch
(See FIG. 8) is output.

[0015]

As described above, according to the present invention, regarding the circuit portion causing the mismatch, the re-simulation is performed using the pattern covering all the conditions, and all the state values of the circuit portion causing the mismatch are output. By doing so, all the information necessary for circuit analysis can be obtained, which has the effect of significantly reducing man-hours.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit description 5 in FIG.

FIG. 3 is a diagram showing an example of an input pattern A6 of FIG.

FIG. 4 is a diagram showing an example of an expected value 7 in FIG.

5 is a diagram showing an example of the disagreement information 8 in FIG.

6 is a diagram showing an example of input terminal information 9 of FIG.

FIG. 7 is a diagram showing an example of an input pattern B10 of FIG.

FIG. 8 is a diagram showing an example of all state values 11 in FIG.

[Explanation of symbols]

 1 Simulation part 2 Fine trace part 3 Input pattern part 4 Re-simulation part 5 Circuit description 6 Input pattern A 7 Expected value 8 Mismatch information 9 Input terminal information 10 Input pattern B 11 All state values IN1 to IN5 Input terminals OUT1, OUT2 Output terminals

Claims (1)

Claim: What is claimed is: 1. A circuit for performing simulation and expected value matching on a circuit description using a first input pattern and its expected value, and outputting a mismatch information.
Based on the mismatch information output by the simulation unit and the circuit description, a fine trace unit that performs fine trace and outputs input terminal information, and based on the input terminal information output by the fine trace unit, An input pattern creating unit that creates a second input pattern that covers all conditions for the circuit part that is the cause and a circuit part that is the cause of the mismatch by performing simulation again using the created second input pattern. And a re-simulation unit that outputs all state values regarding the logic simulation method.