JPH06139302A - Logic verifying system - Google Patents

Abstract

PURPOSE:To efficiently execute simulation of a circuit to easily verify the equivalence of the circuit at the time of logic verification of the circuit described in two different levels. CONSTITUTION:This system consists of a model generating part 21 which generates the simulation model where circuits in two levels exist together at the time of logic verification of circuits 25 and 26 described in two different levels and a common external input signal connected to input signals corresponding to two different levels and a logic element for comparison between state values of corresponding result comparison signals are automatically generated in accordance with files 27 and 28 where correspondence between input signals of two circuits and result comparison signals is described, a state value setting part 22 which sets the state value to the external input signal, a signal designating part 23 which designates a simulation result output signal, and a simulation part 24 which simulates the model where circuits in two levels exist together.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification system.

[0002]

2. Description of the Related Art In the conventional logic verification method, when verifying the equivalence of circuits of two different levels, each simulator can be treated from circuit information by using two simulators that simulate circuits of each level. I was creating a simulation model. Then, the same test pattern was given to the two simulators to perform two simulations, and then the two simulation results were compared to verify the equivalence of the circuits.

[0003]

However, since the above-mentioned conventional logic verification method uses the simulator of the circuit of two levels, it is necessary to create two simulation models and execute two simulations. Therefore, it takes a lot of time until the simulation results of the two-level circuits are obtained, and the simulation results of the two-level circuits must be compared, and it takes a lot of time to verify the equivalence. There was a drawback that it required a lot of man-hours.

[0004]

According to a first logic verification method of the present invention, circuits of two levels are mixed according to circuit information described in two different levels, and an input signal from the same external input signal is input. At the external input terminal of the simulation model in which the model creating means for creating a simulation model for connecting to the corresponding input signal of each level of the corresponding file and the circuit of different two levels created by the model creating means are mixed. A state value setting means for setting a test pattern, a signal designating means for designating a signal for outputting a simulation result, a simulation means for simulating a simulation model in which two different levels are mixed, and a simulation result of the output signal are compared. Result comparison comparing corresponding signals in the signal correspondence file Configured to include a stage.

Further, a second logic verification method of the present invention is a logic circuit for comparing the coincidence of corresponding output signals of respective levels from the comparison signal corresponding file in the first model creating means in the first logic verification method. And a state value setting means for creating a simulation model in which the output of the logic circuit is used as an external output signal.
It is configured to include simulation means and signal designating means.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention. Circuit described in level A and level B
Logic verification is performed on the circuit described in.

In the model creating section 11, the circuit description file 16 of level A and the circuit description file 17 of level B, and the input signal correspondence file 18 in which the correspondence between the input signals of level A and level B is described are input to input the input signals. The external input signals for the number of pairs of are automatically generated. Then, the automatically generated external input signal is connected to the corresponding input signal of level A and level B described in the input signal correspondence file 18,
A simulation model in which level A and level B are mixed is created.

In the state value setting unit 12, the model creating unit 11
Input the simulation model 19 created in step 1, and input the test pattern file 110 to the simulation model 19
Set to the external input signal of.

The signal designating section 13 sets the simulation model 19 so as to output the simulation results of the level A comparison signal and the level B comparison signal described in the comparison signal correspondence file 111.

In the simulation section 14, the simulation model 19 is simulated with the test pattern set by the state value setting section 12, and the state of the signal set by the signal designating section 13 is set every time one pattern of simulation is completed. The value is output to the simulation result 112, and simulation is performed for all patterns of the test pattern file 110. The comparison result section 15 compares the simulation results of the corresponding signals of the simulation result 112 based on the correspondence of the comparison signals described in the comparison signal correspondence file 111, and the comparison result file 113.
Output the comparison result to. Then, the comparison result file 11
From 3, it is verified whether the circuits of level A and level B are equal.

Next, FIG. 2 shows an application example of the embodiment shown in FIG.
Will be described with reference to.

FIG. 2 is a circuit for logic verification, where (a) is a circuit described at level A and (b) is a circuit described at level B.

FIG. 3 shows level A and level B used in FIG.
FIG. 5 is a file configuration diagram of an input signal correspondence file describing correspondence of the input signals of FIG.

FIG. 4 is a model diagram of a simulation model according to the embodiment shown in FIG. 1, which is a simulation circuit in which level A and level B circuits are mixed.

FIG. 5 is a pattern diagram of test patterns used during simulation with the simulation model shown in FIG.

FIG. 6 is a file configuration diagram of a comparison signal correspondence file describing the correspondence between the level A and level B comparison signals for comparing the simulation results shown in FIG.

FIG. 7 is a file configuration diagram of a comparison result file in which the simulation result of the signal in the simulation model shown in FIG. 4 is output.

FIG. 8 is a file configuration diagram of a comparison result file comparing the simulation results of the level A and level B circuits shown in FIG.

First, the level A circuit description file 16 of FIG. 2A, the level B circuit description file 17 of FIG. 2B, and the correspondence between the level A and level B input signals of FIG. The input signal correspondence file 18 described is input.

From the input signal correspondence file 18 of FIG. 3, "C" of level A, "C + 00" of level B, "D" of level A, "D + 00" of level B, "E" of level A and level B. There are four input signal pairs of “E + 00” of “A”, “F” of level A and “F + 00” of level B.
One external input signal W, X, Y, Z is generated. And
From the external input signal W, "C" of level A and "C" of level B
+00 ", external input signal X to level A" D "and level B" D + 00 ", external input signal Y to level A
A simulation model M is created in which circuits of level A and level B, which are respectively connected to "E" and "E + 00" of level B, and from the external input signal Z to "F" of level A and "F + 00" of level B, are mixed.

Next, by inputting the test pattern of FIG. 5, the external input signals W, X, Y and Z of the simulation model M are input.
Set the test pattern in sequence.

Further, "G" of level A and "G + 00" of level B described in the comparison signal correspondence file 11 of FIG.
Set to output the simulation result of.

Then, the simulation of the simulation model M is executed, and each time the simulation for one pattern is completed, the simulation result of the comparison target signal is output to obtain the simulation result of FIG.

The obtained simulation result of FIG. 7 is
Based on the correspondence of the comparison signal correspondence file 111 of FIG. 6, the result of “G + 00” of level A is determined to obtain the comparison result of FIG. 8, and the equivalence of the circuits of level A and level B is verified.

Next, the second embodiment will be described in detail with reference to the drawings.

FIG. 9 is a system configuration diagram showing a second embodiment of the present invention. Circuit described in level A and level B
Logic verification is performed on the circuit described in.

In the model creating unit 21, the level A circuit description file 25 and the level B circuit description file 26, the input signal correspondence file 27 in which the correspondence between the level A and level B input signals is described, and the correspondence between the comparison signals. The comparison signal correspondence file 28 in which is described is input. Then, as many external signals as the number of pairs of input signals described in the input signal corresponding file 27 are automatically generated, and the level A and the level B described in the input signal corresponding file 27 are automatically generated from the automatically generated external input signals. Connect to each corresponding input signal. In addition, as many logic elements as the number of pairs of comparison signals described in the comparison signal corresponding file 28 are automatically generated, and the comparison signals of level A and level B described in the comparison signal corresponding file 28 are instructed and generated. A simulation model in which level A and level B are mixed is created using the input as the input and the output of the logic element as the external output terminal. State value setting unit 2
In 2, the simulation model 29 created by the model creating unit B21 is input, and the test pattern file 210 is set as an external input signal of the simulation model 29. In the simulation unit 24, the simulation model 29 is simulated using the test pattern file 210 set by the state value setting unit 22, and the signal designating unit 23 is executed every time one pattern of simulation is completed.
The state value of the external output signal set in step 1 is output to the simulation result file 211. Then, it is verified from the output simulation result file 211 whether or not the level A and level B circuits are the same.

Next, an application example of the second embodiment will be described.

Logic verification of the circuit described at level A in FIG. 2A and the circuit described at level B in FIG. 2B is performed.

First, the level A circuit description file 25 of FIG. 2A, the level B circuit description file 26 of FIG. 2B, and the correspondence between the level A and level B input signals of FIG. The input signal correspondence file 27 described, and
The comparison signal correspondence file 28 in which the correspondence between the comparison signals of level A and level B in FIG. 6 is described is input. From the input signal correspondence file 27 of FIG. 3, "C" of level A and level B
"C + 00", level A "D" and level B "D +"
00 ", level" E "and level B" E + 00 ",
It is determined that there are four input signal bodies of "F" of level A and "F + 00" of level B, and four external input signals W,
Generate X, Y, Z. Then, from the external input signal W, the level A is “C” and the level B is “C + 00”, and from the external input signal X, the level A is “D” and the level B is “D + 00”.
From the external input signal Y, the level "E" and the level B "E"
+00 ”, and the external input signal Z is connected to“ F ”of level A and“ F + 00 ”of level B. Next, from the comparison signal corresponding file 28 of FIG. G + 00 ”comparison signal pair is required,
A logic element S4 that receives two signals as inputs and performs a logical operation of exclusive OR that can detect 1 when the two inputs are different
Is automatically generated, and "G" of level A and "G + 0" of level B
0 "is set to the input signal of the logic element S4. Further, the output signal of the logic element S4 is connected to the external output signal G '. In this way, the simulation model M in which the level A and level B circuits are mixed is provided. create.

Next, by inputting the test pattern of FIG. 5, the external input signals W, X, Y, Z of the simulation model M are input.
Set the test pattern in sequence.

The simulation result is set to be output to the external output signal G'of the simulation model M.

Then, the simulation of the simulation model M is executed, and the simulation result of the external output signal G'is output every time the simulation for one pattern ends, and the simulation result of FIG. 11 is obtained. Based on the obtained simulation result of FIG. 11, the equivalence of the level A and level B circuits is verified.

[0035]

According to the logic verification method of the present invention, when the logic verification of the circuits described in different two levels is performed, the simulation of the circuits described in different two levels is simultaneously performed by one simulation. Since the output simulation result can be obtained as a result of verifying the equivalence of the circuits described in different two levels, the time spent for simulation of the two circuits can be reduced and the two circuits can be reduced. Since it is possible to reduce the time for verifying the equivalence of the circuits by comparing the simulation results, it is possible to perform the logic verification in a short time.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention.

2A and 2B are circuit configuration diagrams showing one application example of the embodiment shown in FIG.

FIG. 3 is a file configuration diagram of an input signal correspondence file in which correspondence between level A and level B input signals used in FIG. 2 is described.

FIG. 4 is a model diagram of a simulation model according to the embodiment shown in FIG.

5 is a pattern diagram of a test pattern set as an input signal in the simulation model shown in FIG.

FIG. 6 is a file configuration diagram of a comparison signal correspondence file in which correspondence between level A and level B comparison signals shown in FIG. 2 is described.

7 is a file configuration diagram of a comparison result file that stores simulation results of comparison signals in the simulation model shown in FIG.

FIG. 8 is a file configuration diagram of a comparison result file comparing the simulation results of the level A and level B circuits shown in FIG.

FIG. 9 is a system configuration diagram showing a second embodiment of the present invention.

10 is a model diagram of a simulation model according to the embodiment shown in FIG.

11 is a file configuration diagram of a simulation result file based on the simulation model shown in FIG.

[Explanation of symbols]

11, 21 Model creation section 12, 22 State value setting section 13, 23 Signal specification section 14, 24 Simulation section 15 Result comparison section 16, 17, 25, 26 Circuit description file 18, 27 Input signal correspondence file 19, 29 Simulation model 110, 210 Test pattern file 111, 28 Comparison signal corresponding file 112, 211 Simulation result file 113 Comparison result file S1 to S3 Level logic elements C to I, C + 00, D + 00, E + 00, F + 00, G
+00, H + 00, I + 00 Level signal M Simulation model W ~ 1 External input signal G'External output signal S4 Exclusive OR element

Claims (2)

[Claims] 1. A simulation model in which circuits of two levels are mixed according to circuit information described in two different levels, and the same external input signal is connected to the corresponding input signal of each level of the input signal corresponding file. And a state value setting means for setting a test pattern to an external input terminal of a simulation model in which circuits of two different levels created by the first model creating means are mixed, and a simulation result. A signal designating means for designating a signal for outputting, a simulation means for simulating a simulation model in which two different levels are mixed, and a result of comparing the simulation result of the output signal with corresponding signals in the comparison signal corresponding file. A logic verification method including a comparison means. 2. The first model creating means according to claim 1, further comprising a logic circuit for comparing the coincidence of corresponding output signals of respective levels from the comparison signal corresponding file, and outputting the output of the logic circuit as an external output signal. A logic verification method comprising: a second model creating means for creating a simulation model, a state value setting means according to claim 1, a simulation means, and a signal designating means.