JPH056406A - Scan path logical verification system - Google Patents

Abstract

PURPOSE:To prevent the overlooking of verification for the connection of scan paths and to improve the efficiency in verification by producing automatically a control instruction for simulation to confirm the logical connection of the scan paths and the expected value of the simulation result and comparing the expected value with the actual simulation result. CONSTITUTION:The simulation model of a logic circuit, the wiring order of scan paths, and the information on the control signal which actuates the model are stored in a model information storing means 1. A simulation control instruction output means 2 outputs a control instruction in order to observe the state value of a flip-flop set on a scan path. A simulation executing means 3 performs the simulation of the logic circuit based on the simulation model and the control instruction. An expected value comparing means 5 compares the simulation result with the expected value of the flip-flop obtained by an expected value producing means 4. Then the information on the discordant flip-flops is outputted if no coincidence is obtained between the simulation result and the expected value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path logic verification method for verifying the operation of a logic circuit using a logic simulator.

[0002]

2. Description of the Related Art Conventionally, in this type of scan path logic verification method, the operation verification of a logic circuit is manually confirmed on a circuit diagram. Even when checking with a logic simulator, input patterns and expected values were created, and control commands for the simulator were created manually.

[0003]

In the conventional scan path logic verification method described above, since the proportion of manual work is large, the number of oversights increases as the scale of the logic circuit to be verified increases. It had a drawback that the efficiency of

An object of the present invention is to provide a scan path logic verification method capable of preventing oversight of scan path connection verification and improving the efficiency of verification.

[0005]

A scan path logic verification method of a first invention is a scan path logic verification method for verifying a scan path logic of a logic circuit having a scan path. A model information storage means for storing the simulation model, the wiring order of the scan path, and the information of the control signal for operating the scan path, and (B) the simulation model based on the information held by the model information storage means. , A simulation control command output means for outputting a control command in order to set an environment for operating the scan path and observe the state value of the flip-flop on the scan path during simulation, (C) storing the model information A simulation model of the logic circuit stored in the means, and the simulation control command output procedure There inputs the control command output,
An expected value of the flip-flop on the scan path at the time during the simulation based on the simulation order means for simulating the logic circuit and outputting the simulation result, and (D) the wiring order of the scan path held by the model information storage means. (E) The simulation result output by the simulation executing means and the expected value output by the expected value creating means are input, and the state values of the respective flip-flops are compared to find a mismatch. If it exists, expected value comparing means for outputting information about the flip-flop in which the mismatch exists is configured.

The scan path logic verification method of the second invention is a scan path logic verification method for verifying the scan path logic of a logic circuit having a scan path.
(A) Model information storage procedure for storing a simulation model of a logic circuit, a wiring order of scan paths, and information of control signals for operating the scan paths, (B)
Based on the information obtained in the model information storage procedure, the environment is set so that the scan path operates on the simulation model, and control is performed to observe the state value of the flip-flop on the scan path during simulation. Simulation control command output procedure to output commands,
(C) A simulation execution in which the simulation model of the logic circuit obtained in the model information storage procedure and the control command output in the simulation control command output procedure are input, the logic circuit is simulated, and the simulation result is output. Procedure, (D) an expected value creation procedure for creating an expected value of the flip-flop on the scan path at the time during simulation based on the wiring order of the scan path obtained in the model information storage procedure, (E) If the simulation result output in the simulation execution procedure and the expected value output in the expected value creation procedure are input and the state values of the respective flip-flops are compared and if there is a mismatch, the flip-flop with the mismatch exists. Consists of an expected value comparison procedure, which outputs information about That.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the scan path logic verification system of the present invention.

The scan path logic verification method of the present embodiment shown in FIG. 1 stores model information storing a simulation model of a logic circuit, a wiring order of the scan path, and information of control signals for operating the scan path. Means 1,
Based on the information stored in the model information storage means 1, a control command is set in order to set an environment for operating the scan path on the simulation model and observe the state value of the flip-flop on the scan path during the simulation. Is input, the simulation model of the logic circuit stored in the model control information output unit 2 and the control command output from the simulation control command output unit 2 is input, and the simulation of the logic circuit is performed. Simulation execution means 3 for outputting a result, expected value creation means 4 for creating the expected value of the flip-flop on the scan path at the time during the simulation based on the wiring order of the scan path held by the model information storage means 1, the simulation The system output by the execution means 3 Calculation result and the expected value output from the expected value generating means 4 are input, and the state values of the respective flip-flops are compared. It is composed of means 5.

Next, the operation will be described.

In FIG. 1, the model information storage means 1 is
The model information reference request 6 is received, the type of the requested information is determined, and various outputs corresponding to each information, that is, a simulation model output, a scan path wiring sequence information output, a scan path control signal information output, etc. Is done. Here, as the simulation model output, a simulation model is output from design data (for example, a netlist) of the logic circuit. The scan path wiring order information output outputs the order of flip-flops connected to the scan path, which is designated by the circuit designer, as the scan path wiring order information. The scan path control signal information output is the name of the control signal for operating the scan path specified by the circuit designer, the state value to be set for this signal to operate the scan path, and the scan value. The signal name of the clock signal that operates the flip-flop on the campus is output as scan path control information.

The simulation control command output means 2 first requests the model information storage means 1 for scan path wiring order information and receives it. Further, it requests and receives scan path control signal information. Next, referring to the scan path wiring order information and the scan path control signal information, in logic simulation, an instruction to set an initial value to each flip-flop on the scan path,
An instruction to set the state value for propagating the flip-flop on the scan path to the scan path input terminal, an instruction to set the state value for operating the scan path to the control signal of the scan path, and a clock for operating the flip-flop Create an instruction to set a clock pulse on a signal. Then, referring to the scan path wiring order information, an instruction for observing the state value of each flip-flop on the scan path is created during the simulation. Further, the number of flip-flops on the scan path included in the scan path wiring order information is calculated, and an instruction for performing simulation is created for a time corresponding to the number of flip-flops × clock pulse period. Then, each of the above commands is output.

Next, the simulation execution means 3 inputs the simulation model output from the model information storage means 1, performs simulation and observation of the state value of the signal, and outputs the observed state value.

Next, the expected value creating means 4 requests and receives the scan path wiring order information from the model information storing means 1. Next, the instruction output from the simulation control instruction output means 2 is input to obtain the initial value set in the flip-flop on the scan path and the state value set in the scan path input terminal in the simulation. Then, referring to the scan path wiring order information, in the simulation, the value of each flip-flop on the scan path is connected from the output of the flip-flop by the scan path for each cycle of the clock pulse input to the clock signal. Based on the initial value set in the flip-flop on the scan path and the state value set in the scan-path input terminal as a signal to be propagated to the next flip-flop, the scan-path on the scan path in each cycle of the clock pulse. Create and output the expected value of the flip-flop.

Finally, the expected value comparison means 5 inputs the simulation result output by the simulation execution means 3 and the expected value output by the expected value creation means 4.
Then, the simulation result is compared with the expected value, and if they match, the process ends without doing anything, and if they do not match, the signal name of the flip-flop whose state value did not match is output.

As described above, the simulation control command for confirming the logical connection of the scan path and the expected value of the simulation result are automatically created, and the simulation result and the expected value are compared to verify the connection of the scan path. Can be overlooked and the efficiency of verification can be improved.

Next, the operation will be specifically described with reference to the scan path configuration example shown in FIG.

In FIG. 2, it is assumed that the scan path operates when the state value "1" is set to the control signal input terminal 15 of the scan path.

The model information storage means 1 includes a netlist of logic circuits having scan paths and a scan path connection order designated by the designer of the circuit, that is, "scan path input terminal 14, register 11, register 12, register". 13, the information of the order of the scan path output terminal 17 ", the control signal of the scan path, the state value" 1 "of the control signal for operating the scan path, the clock signal for operating the flip-flop, and the request. This information is output according to.

Next, the simulation control command output means 2 receives from the model information storage means 1 the scan path wiring sequence "scan path input terminal 14, register 11, register 12, register 13, scan path output terminal 17" and the scan path wiring order. A state value “1” set for operating the scan path is input as a campus control signal, and a clock signal for operating the flip-flop is input to the clock input terminal 16. Then, based on this information, "1" is set as the state value for propagating on the predetermined scan path, and "0" is set in the signal 18 output from the register 11 as the initial value of each flip-flop. The signal 19 output from 12 is set to “0”, the signal 20 output from the register 13 is set to “0”, the scan path control signal is set to “1” as the environment setting for operating the scan path, and the clock terminal is set to the clock terminal. Create an instruction to set the clock parrel.

Further, the simulation control command output means 2 includes a scan path input terminal 14 on the scan path.
A command for observing the state value of the signal input to the signal, the signals 18 to 20, and the state value of the signal output from the scan path output terminal 17 is created. Then, the instruction for executing the simulation is created only for the time when the number of clocks for three times which is the number of flip-flops on the scan path is input, and the created instruction is output to the simulation executing means 3 and the expected value creating means 4.

Next, the simulation execution means 3 inputs the simulation model output by the model information storage means 1 and the instruction created by the simulation control instruction output means 2, and executes the simulation according to the instruction.
The state value of the signal on the scan path observed during the simulation is output as the simulation result.

Next, the expected value creating means 4 uses the model information storage means 1 to scan line wiring order "scan path input terminal 14, register 11, register 12, register 1".
3, the scan path output terminal 17 "is input, and the command output from the simulation control command output means 2 is input, and the initial state values of the signals described in the wiring order are" 1 ", “0”, “0”, “0”, “0” are calculated, and in the next clock cycle, “1”,
“1”, “0”, “0”, “0”, and in the next clock cycle, “1”, “1”, “1”, “0”,
An expected value is created and output assuming that the state value of the flip-flop on the scan path is propagated to the next flip-flop every clock cycle such as “0”.

Then, the expected value comparison means 5 and the simulation result output from the simulation execution means 3
The expected value output from the expected value creating means 4 is input, the two are compared, and if there is a mismatch, the signal name of the flip-flop that has a mismatch is output.

[0025]

As described above, according to the scan path logic verification method of the present invention, the simulation control command for confirming the logical connection of the scan path and the expected value of the simulation result are automatically created to obtain the simulation result. By comparing with the expected value, it is possible to prevent the connection verification of the scan path from being overlooked and to improve the verification efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a scan path logic verification method of the present invention.

FIG. 2 is an explanatory diagram showing an example of an operation in the scan path logic verification method of the present embodiment.

[Explanation of symbols]

1 Model information storage means 2 Simulation control command output means 3 Simulation execution means 4 Expected value creation means 5 Expected value comparison means 6 Model information reference request 11-13 registers 14 to 16 input terminals 17 output terminals 18 to 20 signals

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G06F 11/26 310 9072-5B

Claims (2)

[Claims] 1. A scan path logic verification method for verifying scan path logic of a logic circuit having a scan path, comprising: (A) a simulation model of a logic circuit, a scan path wiring order, and a scan path operation. Model information storage means for storing control signal information for
(B) In order to set an environment for operating the scan path on the simulation model based on the information stored in the model information storage means and to observe the state value of the flip-flop on the scan path during the simulation. ,
Simulation control command output means for outputting a control command, (C) A simulation model of the logic circuit stored in the model information storage means, and a control command output by the simulation control command output means are input to simulate the logic circuit. And (D) expecting to create the expected value of the flip-flop on the scan path at the time during the simulation based on the wiring order of the scan path held in the model information storing means. (E) a value creating means, (E) inputting the simulation result output by the simulation executing means and the expected value output by the expected value creating means, comparing the state values of the respective flip-flops, and if there is a mismatch, Information about flip-flops with mismatches Scan path logic verification method characterized by comprising the expected value comparing means for outputting. 2. A scan path logic verification method for verifying scan path logic of a logic circuit having a scan path, comprising: (A) a simulation model of a logic circuit, a scan path wiring order, and a scan path operation. Model information storage procedure for storing control signal information and
(B) To set an environment for operating the scan path on the simulation model based on the information obtained in the model information storage procedure and to observe the state value of the flip-flop on the scan path during the simulation. A simulation control instruction output procedure for outputting a control instruction, (C) a simulation model of the logic circuit obtained in the model information storage procedure, and a control instruction output in the simulation control instruction output procedure,
Based on a simulation execution procedure for simulating a logic circuit and outputting a simulation result, and (D) a scan path wiring order obtained in the model information storing procedure, the flip-flops on the scan path at the time during the simulation are An expected value creation procedure for creating an expected value, (E) The simulation result output in the simulation execution procedure and the expected value output in the expected value creation procedure are input, and the state values of each flip-flop are compared. Then, if there is a mismatch, an expected value comparison procedure for outputting information on the flip-flop with the mismatch, a scan path logic verification method.