JPH0863510A - Logical simulation device - Google Patents

Abstract

PURPOSE: To simultaneously execute function verification by a logical simulation model on LSI and the function verification of a verification object on a logical simulation device. CONSTITUTION: A logical simulator 2 executing the logical simulation model of LSI being a simulation object on a computer system, a package 4 loading an external logical circuit constituting the verification object and an interface 6 connecting the logical simulator 2 and the external logical circuit of a package 4 are provided. Test pattern data from the external logical circuit is supplied to the logical simulator 2 through an interface 6. Data of a simulation result on the logical simulation model is read into the external logical circuit and the operation verification of the logical simulation model and the external logical circuit is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a designed LSI simulated by a logic simulation model,
The present invention relates to a logic simulation device capable of simultaneously verifying an operation with a real circuit to be verified mounted in a package.

[0002] Today, with the progress of semiconductor technology, development of LSI having multiple functions has been advanced in order to reduce the price and the size. Even in such an LSI, it is necessary to verify the function of the designed LSI. The verification of the function requires a huge amount of time even for the function verification of one function with the multi-functionalization of the LSI, and it is impossible to verify all the functions on the computer system. By configuring the function with an actual circuit, verifying the function of this actual circuit, and verifying the residual function of the LSI with a logical simulation model that is executed on a computer system that is different from the actual circuit verification, the LSI We are verifying the function of.

[0003]

2. Description of the Related Art In a conventional logic simulation apparatus that also uses an actual circuit, a function having complicated state transitions in which it is difficult to verify all combinations on a computer system, or a verification result appears on a computer system. For functions etc. that seem to take enormous time to complete, we perform verification that shortened the time with a test circuit etc. on the computer system,
The actual operation consists of an actual circuit, and the verification is performed separately from the computer system.

[0004]

However, even if no abnormality is found in the verification of each part of the LSI by such a separate functional verification, it is possible to perform the functional verification by the logic simulation alone in the package in which the actual circuit is mounted. When a good LSI is mounted and comprehensive functional verification of both is performed, a successful result is not always obtained in the functional verification.

Therefore, in such a case, the LSI design must be redone from the beginning, and the result is that the verification time for functional verification cannot be shortened. The present invention was created in view of such technical problems,
It is an object of the present invention to provide a logic simulation device capable of simultaneously performing functional verification of a logic simulation model for an LSI and functional verification of a verification target.

[0006]

FIG. 1 shows a block diagram of the principle of the invention according to claim 1. FIG. 2 shows a block diagram of the principle of the invention according to claim 2. FIG. 3 shows a principle block diagram of the invention according to claims 3 to 5.

According to a first aspect of the present invention, as shown in FIG. 1, a logic simulator 2 for executing a logic simulation model of a simulation target LSI configured in a gate level description or a function level description format on a computer system, An external logic circuit of the package 4 is provided with a package 4 mounting an external logic circuit or LSI constituting the verification target, and an interface 6 connecting the logic simulator 2 and the external logic circuit of the package 4 or the LSI. By supplying test pattern data from a circuit or LSI to the logic simulator 2 via the interface 6 and operating an external logic circuit or LSI of the package according to data of a simulation result of the logic simulation model. The logical simulation External logic model and the package 4, or and performing operation verification of LSI.

According to a second aspect of the present invention, as shown in FIG. 2, in the logic simulation apparatus according to the first aspect, an external logic circuit or LSI on the package 4 and the logic simulation model are logically equivalent. And data of a simulation result obtained by supplying predetermined test data to the logic simulation motel, and output from an external logic circuit or LSI on the package 4 as an expected value for the simulation. The operation of the logic simulation model and the external logic circuit or the LSI of the package 4 is verified by comparing the data with the data.

According to a third aspect of the present invention, as shown in FIG. 3, in the logic simulation apparatus according to the first aspect, output data of a predetermined simulation element of the logic simulation model is stored in a storage device via the interface 6. 8, the read output data is input to a predetermined simulation element simulated by the logic simulation model, and the external logic circuit or LSI of the package is selected according to the simulation result data of the logic simulation model. Since it operates, the logic simulation model and the external logic circuit of the package 4 or LS
It is characterized in that the operation verification of I is performed.

According to a fourth aspect of the present invention, as shown in FIG. 3, in the logic simulation apparatus according to the third aspect, the storage device 8 is a file on a computer system.

According to a fifth aspect of the present invention, as shown in FIG. 3, in the logic simulation apparatus according to the third or fourth aspect, the output data of the stored simulation element is being verified during operation of the logic simulation model. To a predetermined simulation element of the logic simulation model, and by operating the external logic circuit or LSI of the package according to the data of the simulation result of the logic simulation model, the logic simulation model and the package. 4 is for verifying the operation of the external logic circuit or LSI.

[0012]

According to the first aspect of the present invention, the test pattern data is supplied from the minimum necessary external logic circuit or LSI mounted on the package 4 to the logic simulator 2 through the interface 6 to obtain the logic simulation model. By operating the external logic circuit or LSI of the package based on the data of the simulation result, the logic simulation model and the external logic circuit or LSI can be verified at the same time. Also in the invention described in claim 2, the logic simulation model and the external logic circuit or the LSI are simultaneously verified. However, the simulation result obtained by giving the test data to the logic simulation model is the same as the conventional one. This is performed by comparing the data with the data output as an expected value from the external logic circuit or LSI of the package that is logically equivalent to the logic simulation model. The same effect as the invention according to claim 1 is obtained.

According to the third aspect of the present invention, the output data of the predetermined simulation element of the logic simulation model is stored in the storage device, and the output data can occur in the predetermined simulation element of the logic simulation model in the simulation. As no data,
In other words, it is possible to input and simulate as abnormal state data, and perform simultaneous verification of the logic simulation model and the minimum necessary external logic circuit or LSI by comparing the simulation result data with the test pattern data. However, if there is no error in the verification, the abnormality of the logic simulation model is verified, and if there is an error, the normality of the logic simulation model is verified.

According to the invention of claim 4, the storage device is a file on the computer system, and the same effect as that of the invention of claim 3 can be obtained. According to the fifth aspect of the invention, verification is performed by inputting stored simulation element data into a predetermined simulation element of the logic simulation model during operation verification of the logic simulation model to forcibly cause an abnormal state. It was done like this. The same effect as that of the invention described in claim 3 can be obtained.

[0015]

FIG. 4 shows an embodiment of the invention described in claim 1. In FIG. 4, reference numeral 30 denotes a computer system. The computer system 30 is equipped with a logic simulation model for the designed LSI, and the logic simulation model constitutes a logic simulator for the LSI designed on the computer system. The logic simulation model is a program for verifying the function of the LSI, and is configured in the gate level description or function level description format as in the conventional case. An interface 32 connects the computer system 30 and the actual circuit 34. The actual circuit 34 is configured to perform a part of the function of the designed LSI and is mounted on the package. A pattern generator 36 supplies a pattern signal to the actual circuit 34.

The actual circuit 34 includes a test pattern signal generator 34T for generating a test pattern signal (test pattern data), and a pattern signal (data) obtained as a result of being simulated by a logic simulation model in response to the test pattern signal. And a comparison section 34C for performing verification by comparing with a test pattern signal sent from the circuit section 34T. The input from the pattern generator 36 of the actual circuit 34 is given the reference number 52, the output of the actual circuit 34 to the interface 32 is given the reference number 54, and its input is given the reference number 76.

An example of the actual circuit 34 is shown in FIG. Figure 5 Smell
The test pattern signal generator 34T
Circuit (FF) 40, 42, 44, 46, 48, and
The other OR circuit 50. This test pattern signal
The generator 34T uses the polynomial X^Five+ X³+1 calculation is performed.
The comparison unit 34C includes a flip-flop circuit (FF) 60,
62, 64, 66, 68 and exclusive OR circuits 70, 72
Consisting of Polynomial X ^Five+ X³+1 calculation and polynomial
X^Five+ X³The same pattern signal as the signal generated by +1
Is input to the terminal 76 or not. 7
4 is an error cow connected to the output of the exclusive OR circuit 72
It is a computer. This error counter 64 indicates the verification result
ing. The error counter 64 has a reset terminal R,
The reset terminal R is reset by closing the switch 75.
A set signal is supplied. The switch 75 is a test pattern
The test pattern signal is generated from the signal generator
After the delay time determined by the logical simulation model
Is configured to be operated.

In FIG. 4, a computer system 30 corresponds to the logic simulator 2 of FIG. 1, and an actual circuit 34 is shown in FIG.
It corresponds to package 4 of. The interface 32 corresponds to the interface 6 of FIG.

The operation of the invention according to claim 1 configured as described above will be described below. By the time the operation of the designed LSI is to be confirmed, it is assumed that the actual circuit 34 as shown in FIG. 5 is mounted on the package.

Then, it is assumed that the logic simulation apparatus is connected as shown in FIG. A pattern signal, for example, a clock signal is generated from the pattern generator 36 (see (1) in FIG. 6) and the clock signal is supplied to the test pattern signal generation unit 34T of the actual circuit 34. From the output terminal 54 of the test pattern signal generator 34T, 31 sets of test pattern signals (data) of 5 bits are output (see (2) in FIG. 6), and the interface 3
After that, it is used for the arithmetic processing of the logic simulation model of the computer system.

An error counter is output from the computer system when a predetermined time elapses after the signal obtained by simulating from the logic simulation model is output from the time when the test pattern signal is transmitted (see (5) in FIG. 6). 74 is reset.

After that, the signal (data) resulting from the simulation by the logic simulation model passes through the interface 32 and the input terminal 7 of the comparison section 34C of the actual circuit 34.
6, and the comparison unit 34C determines whether or not the same signal as the test pattern signal output from the test pattern signal generation unit 34T is returned.

When the returned signal is the same signal as the test pattern signal output from the test pattern signal generator 34T, no signal is generated from the exclusive OR circuit 72 and the error counter 74 counts up. Is not done.

If they are not the same, an error as shown in FIG. 6 (3) has occurred in the signal, that is, when there is no error, the signal which should be returned as D3 is returned as D2, In response to the clock signal supplied to the input terminal 52, the error counter 74 is counted up and the count value becomes 1, and when there is no error, the signal that should be returned as D6 is also returned as D5. The count-up of the counter 74 is generated, and the count value becomes 2.

As described above, the function of the logic simulation model of the designed LSI and the minimum necessary function of the actual circuit 34 can be verified at the same time. Therefore, there is no abnormality in the logic simulation of the designed LSI with the logic simulation model alone which is not configured by the actual circuit, and the LS is manufactured after the LSI is manufactured.
When I is mounted in the above-mentioned package to verify the function of the system, the function becomes defective, and the verification period of the entire system can be shortened as compared with the case where the LSI is redesigned. . It also reduces design man-hours.

The actual circuit 34 is configured as a circuit equipped with the function corresponding circuit portion when the time required for the operation of the function in the LSI to be developed is long and cannot be confirmed on the computer system. Good.

FIG. 7 shows an embodiment of the invention described in claim 2. In this embodiment, in the embodiment shown in FIGS. 4 and 5, the test pattern signal output from the actual circuit 34 and supplied to the logic simulation model of the computer system through the interface 33 is used as the test data of the logic simulation model. The one used is supplied to the logic simulation model as an expected value. That is, the test data is supplied to the computer system in the same manner as the conventional one, and the data of the logic simulation result output from the logic simulation model in response to the test data and the interface 33 from the actual circuit 34 are supplied. By comparing the expected value supplied through the computer system with the computer system, it is possible to verify the function of the system including the logic simulation model and the actual circuit.

Since such functional verification can be performed, the verification period can be shortened and the design man-hour can be reduced also in this embodiment. In FIG.
The computer system 30 corresponds to the logic simulator 2 in FIG. 2, and the interface 33 is the interface 6 in FIG.
Corresponding to. The actual circuit 34 corresponds to the package 4 in FIG.

FIG. 8 shows an embodiment of the invention described in claims 3 to 5. This embodiment shows an embodiment for forcibly generating a singular state in a logic simulation model on a computer system to perform functional verification. The singular state is a state that cannot occur in a normal logic simulation model. For the forced singular state to the logic simulation model, the data bit (internal state) of the simulation element generated in the logic simulation model is stored in the RAM 80.
Can be generated by inputting the stored data bit to a specific simulation element (for example, a storage element) of the logic simulation model.

In FIG. 8, the computer system 30 corresponds to the logic simulator 2 of FIG. 3, and the actual circuit 34 is shown in FIG.
It corresponds to package 4 of. The interface 33 corresponds to the interface 6 of FIG.

FIG. 8 shows an example thereof. A portion 82 surrounded by a chain double-dashed line shows an example of a simulated logic simulation model, and FIG. 8 shows the logic simulation model in a circuit form. Flip-flop circuit (FF) 8 in this circuit diagram
Reference numerals 4, 86 and 88 indicate one logic simulation model, and the selector 90 is a selector for inputting a singular state to the above-mentioned specific circuit. In a normal operating state that is not in the singular state, the selector 90 operates so as to supply the output signal of the flip-flop circuit 84 to the flip-flop circuit 86 by the signal on the line 92, and when the input is in the singular state, the selector 90 is operated. Is configured to be generated in the computer system for switching the signal to the output side of the RAM 80. To switch to the singular state, the logic simulation model is operated when a state to be verified occurs on the computer system, and the simulation is verified.

Assume that the singular state is the output data of the flip-flop circuit 86 of the logic simulation model, assuming that the test pattern signal (data) generated by the actual circuit 34 is a signal as shown in (1) of FIG. D3 (Fig. 9
(See (3)) in the RAM 80 via the interface 34, read from the RAM 80 at the next clock time, and read into the flip-flop circuit 86 via the selector 90 to generate in the logic simulation model. You can

When the singular state is generated in this way,
Since the signal of the simulation result output from the logic simulation model and input to the comparison unit 34C of the actual circuit is as shown in (3) of FIG. 9, as shown in (4) of FIG.
The count-up operation of the error counter 74 is caused. Thereby, it can be verified that the logic simulation model is operating normally. Further, the fact that the error counter 74 does not perform the counter-up operation when the singular state as described above is generated can verify that the logic simulation model is operating abnormally.

As described above, the function of the logic simulation model of the designed LSI and the minimum necessary function of the actual circuit 34 can be verified at the same time. Therefore, there is no abnormality in the logic simulation of the logic simulation model alone, and when the LSI is manufactured and then the LSI is mounted on the package to verify the function of the system, the function becomes defective and the L
The verification period of the entire system can be shortened as compared with the case of redesigning the SI. It also reduces design man-hours.

[0035]

As described above, according to the present invention, the logic simulation model of the designed LSI and the external logic circuit to be verified mounted on the package or L
Simultaneous verification with SI can be performed. Therefore, the time required for verification is shortened, and the man-hours required for incorporating the designed LSI into the system are reduced.

Further, it is possible to generate a singular state in the simulation element of the logic simulation model and perform simultaneous verification of the logic simulation model and the external logic circuit or LSI to be verified. Also in this case, it is possible to reduce the verification time and the number of steps.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 1.

FIG. 2 is a principle block diagram of the invention according to claim 2;

FIG. 3 is a principle block diagram of the invention described in claims 3 to 5.

FIG. 4 is a diagram showing an embodiment of the invention according to claim 1;

5 is a detailed view of the actual circuit shown in FIG.

6 is an operation timing chart of the embodiment shown in FIG.

FIG. 7 is a diagram showing an embodiment of the invention according to claim 2;

FIG. 8 is a diagram showing an embodiment of the invention described in claims 3 to 5;

9 is an operation timing chart of the embodiment shown in FIG.

[Explanation of symbols]

 2 logic simulator 4 package 6 interface 8 storage device 30 computer system 32 interface 33 interface 34 actual circuit 36 pattern generator 80 storage device 82 logic simulation model

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 11/26 310

Claims (5)

[Claims] 1. A logic simulator for executing a logic simulation model of a simulation target LSI configured in a gate level description or a function level description format on a computer system, and an external logic circuit or LSI configuring the verification target. And an interface for connecting the logic simulator to an external logic circuit or LSI of the package, and supplying test pattern data from the external logic circuit or LSI of the package to the logic simulator via the interface. However, by operating the external logic circuit or LSI of the package according to the data of the simulation result of the logic simulation model, the logic simulation model and the external logic circuit of the package or the LSI A logic simulation device characterized by performing operation verification. 2. The logic simulation device according to claim 1, wherein an external logic circuit or LSI on the package and the logic simulation model are logically equivalent to each other, and a predetermined test is performed on the logic simulation model. The logic simulation model is obtained by comparing the data of the simulation result obtained by supplying the data with the data output from the external logic circuit or LSI on the package as an expected value for the simulation. And an external logic circuit of the package, or L
A logic simulation device characterized by performing operation verification of SI. 3. The logic simulation apparatus according to claim 1, wherein output data of a predetermined simulation element of the logic simulation model is read into a storage device via the interface, and the read output data is read by the logic simulation model. The logical simulation model and the external logic circuit of the package are operated by operating the external logic circuit or the LSI of the package according to the data of the simulation result of the logical simulation model, which is input to a predetermined simulation element to be simulated. , Or a logic simulation device for verifying the operation of an LSI. 4. The logic simulation apparatus according to claim 3, wherein the storage device is a file on a computer system. 5. The logic simulation apparatus according to claim 3 or 4, wherein the stored output data of the simulation element is stored in a predetermined simulation element of the logic simulation model during operation verification of the logic simulation model. Inputting and operating the external logic circuit or LSI of the package according to the simulation result data of the logic simulation model to verify the operation of the logic simulation model and the external logic circuit of the package or LSI. A logic simulation device characterized by.