JP2001331544A - Method and device for simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that simulation in function and logic verification of an LSI is performed by using plural test vectors which sometimes have sharable parts such as initialization patterns of a circuit, however, the patterns can not be shared by a conventional simulation method and simulation time becomes wasteful. SOLUTION: The simulation time is put back to a halfway point by a circuit state output processing part 5 which stores a circuit state halfway in simulation separately from test vector information and a circuit state read-in processing part 7 which reads in its circuit state output result and a test vector is changed to shorten the simulation time of a common pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a simulation method and apparatus for simulating a function / logic at the time of designing a semiconductor device such as an LSI.

[0002]

2. Description of the Related Art In recent years, with the increase in the size of semiconductor devices, the efficiency of semiconductor device design has been emphasized. Against this background, it is necessary to verify whether the designed circuit operates as specified. Therefore, the operation of the semiconductor device has been conventionally verified using a simulation device.

FIG. 8 shows a configuration diagram of a conventional simulation apparatus. In FIG. 8, 1 is a netlist describing circuit information of a semiconductor device, 2 is a test vector describing a test pattern created by a designer according to the specifications of the semiconductor device, and 3 is a netlist 1 based on a test vector 2 Simulation processing unit for performing simulation
Is a simulation result obtained by simulating the netlist 1 based on the test vector 2. The designer verifies the netlist 1 while checking whether the simulation result 4 matches the specification one by one.

[0004]

In the conventional simulation method, a simulation is performed using a plurality of test vectors in order to confirm whether the designed circuit operates normally. In many cases, the plurality of test vectors include a portion that can be shared, such as a circuit initialization pattern. This will be described with reference to FIG. FIG. 2 shows a case where three test vectors are used as an example. Among these three vectors, the pattern A is a common pattern. Therefore, at the time T when the simulation of the pattern A ends, these three circuit states are exactly the same. In the conventional simulation apparatus, since the test vector cannot be changed by going backward in the past and changing the test vector, the pattern A portion must be simulated three times as a result. As described above, in the conventional simulation method, when there is a portion that can be shared in the test vector, there is a problem that the simulation time is wasted.

An object of the present invention is to provide a simulation method and apparatus which can solve the above-mentioned conventional problems by sharing a common part such as an initialization pattern of a test vector and reducing waste of simulation time. Aim.

[0006]

According to a first aspect of the present invention, there is provided a simulation method comprising the steps of:
A simulation method for performing a simulation based on a test vector describing a test pattern and verifying that a circuit operates as specified, wherein a circuit state during the simulation is stored in a readable manner separately from test vector information. Is included.

According to the simulation method of the first aspect, the simulation is performed by simulating the circuit state of the common pattern a plurality of times by storing the circuit state of the common pattern in a readable manner and reading and simulating the circuit state when necessary. Waste of time can be reduced.

According to a second aspect of the present invention, there is provided a simulation method comprising:
In 請 Motomeko 1, comprising the step of reading the circuit state in the middle simulation and stored, and has a simulation process using a storage time of the different test vectors of the circuit state after the reading of circuit conditions.

According to the simulation method of the second aspect, in a simulation using a plurality of test vectors, the simulation time of a test vector in which the first half of the test vector has the same pattern can be reduced.

[0010] The simulation method according to claim 3 is characterized in that:
2. The method according to claim 1, further comprising the step of reading the saved circuit state during the simulation, and the step of controlling the circuit state during the simulation and the step of reading the circuit state using a test vector.

According to the simulation method of the third aspect, in a simulation in which the same state exists a plurality of times, such as in a state machine, it is possible to reduce the waste of executing the same transition a plurality of times, thereby reducing the simulation time. Can be reduced.

According to a fourth aspect of the present invention, there is provided a simulation apparatus comprising:
A simulation execution processing unit that simulates a netlist describing circuit information based on a test vector describing a test pattern, a circuit state output processing unit that outputs and stores a circuit state during the simulation of the simulation execution processing unit, A circuit state read processing unit for reading from the circuit state output processing unit and returning the simulation execution processing unit to the circuit state during the simulation.

According to the simulation apparatus of the fourth aspect, the same effect as that of the first aspect is obtained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) In a simulation method according to a first embodiment of the present invention, by saving a circuit state during a simulation, the circuit state can be arbitrarily returned to the saved circuit state. Can be. Further, since the information on the test vector is not included in the stored circuit state, the simulation can be restarted by using a different test vector than when the circuit information was stored.

FIG. 1 is a block diagram of a simulation apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes a netlist, 2 denotes a test vector, 3 denotes a simulation execution processing unit, and 4 denotes a simulation result, which are the same as those of the conventional example. Reference numeral 5 denotes a circuit state output processing unit that outputs a circuit state during the simulation. Reference numeral 6 denotes circuit state information output from the circuit state output processing unit 5. The circuit state information 6 includes information on the logic value of each element in the netlist 1 at the time of outputting the circuit state and information on the scheduled event. However, information on test vector 2 is not included. Reference numeral 7 denotes a circuit state read processing unit that reads the circuit state information 6 and returns the circuit state of the netlist 1 to the same state as when the circuit state information 6 was output.

Next, the flow of the simulation method according to the first embodiment of the present invention will be described using an example in which simulation is performed using three test vectors shown in FIG. FIG. 3A shows a simulation flow.
First, a netlist to be simulated is read (step 101). Next, a test vector is read (step 102). The test vector at this time is pattern A. Next, the simulation is executed until time T when the pattern A ends (step 103). Next, the circuit state output processing unit 5 outputs the circuit state information 6 at the time T at which the simulation of the pattern A is completed, and ends the simulation (104). The simulation of the pattern A, which is a common part of the three test vectors, has been completed by the steps described above. Next, the simulation of the pattern B is performed. As shown in FIG. 3B, a net list is first read (step 10).
5). Next, the circuit state read processing unit 7 reads the circuit state information output in the step (step 104) and returns the circuit state to the state at the time A when the simulation of the pattern A is completed (step 106). Next, a test vector is read (step 107). The pattern read at this time is B. Next, the simulation is executed and terminated until the simulation of the pattern B is completed (step 108).

For patterns C and D, the patterns to be read in step (step 107) are changed to patterns C and D, respectively, and the steps (step 105) to (step 10) are performed.
8) is performed in the same manner as in the simulation of the pattern B. With the conventional method, all the patterns could not be simulated unless the simulation of pattern A was performed three times. By using this method, all the patterns were simulated only by executing the simulation of pattern A once. And the simulation time can be reduced.

According to the simulation apparatus and the simulation method of the present invention, in a simulation using a plurality of test vectors, the simulation time of a test vector in which the first half of the test vector has the same pattern can be reduced.

(Embodiment 2) In the simulation method according to the second embodiment of the present invention, the processing for saving the circuit state during the simulation in the first embodiment and the processing for returning to the saved circuit state By adding a syntax that can be controlled arbitrarily from the test vector side, it is possible to freely return to the past state, while the conventional method could only simulate in one direction from the past to the future,
This is a simulation method that enables a simulation to be executed under conditions different from the previous time.

The configuration of the simulation apparatus according to the second embodiment of the present invention is the same as that of the first embodiment, and FIG.
Shown in However, the second embodiment differs from the first embodiment in that a syntax that can freely control the circuit state output processing unit 5 and the circuit state read processing unit 7 is added to the test vector 2.

Next, the flow of the simulation method according to the second embodiment of the present invention will be described using a simulation example of the state machine in FIG. In the state machine of FIG. 4, there are six states A, B, C, D, E, and F,
If the first state is A, the next state is B. The next state shows a state transition in which the test pattern branches into three states C, D, and E, then changes to the F state, and then returns to the A state. To simulate all states of this state machine, A → B, B → C, B → D,
It is necessary to perform eight transitions of B → E, C → F, D → F, E → F, and F → A. FIG. 5 shows a test vector flow when the state machine is simulated by the conventional method. First, a transition from A to B is executed (step 201). Next, a transition from B to C is executed (step 202). Next, a transition from C to F is executed (step 203). Next, a transition from F to A is executed (step 2).
04). Next, a transition from A to B is executed (step 20).
5). Next, a transition from B to D is executed (step 20).
6). Next, a transition from D to F is executed (step 20).
7). Next, a transition from F to A is executed (step 20).
8). Next, a transition from A to B is executed (step 20).
9). Next, a transition from B to E is executed (step 21).
0). Next, a transition from E to F is executed (step 21).
1). As described above, the conventional method cannot arbitrarily return the circuit state to the previous state during the simulation.
A of step 201, step 205, and step 209
→ B transition and F → A in step 204 and step 208
Must be executed multiple times.

Next, FIG. 6 shows a flow of a test vector when the state machine of FIG. 4 is simulated by using the simulation method according to the second embodiment of the present invention. First, a transition from A to B is executed (step 3
01). Next, the circuit state of the current circuit state B is output and stored according to the instruction in the test vector (step 30).
2). Next, a transition from B to C is executed (step 30).
3). Next, a transition from C to F is executed (step 30).
4). Next, a transition from F to A is executed (step 30).
5). Next, by an instruction in the test vector (step 30).
The circuit state stored in 2) is read and set to the state of B (step 306). Next, a transition from B to D is executed (step 307). Next, a transition from D to F is executed (step 308). Next, in accordance with the instruction in the test vector, the circuit state saved in step (302) is read again and set to the state of B (step 309). Next, a transition from B to E is executed (step 310). Then E
→ The transition of F is executed (step 311).

FIG. 7 shows a test vector description example describing the test vector flow of FIG. Save on line 40 in Figure 7
The syntax ((state B)) corresponds to (step 302) in FIG.
This is an instruction corresponding to the processing of. This syntax is an instruction to output circuit information when this instruction is called as circuit state information 6 under the name "state B" by the circuit state output processing unit 5. The syntax of load (“state B”) on lines 80 and 110 in FIG.
06 and an instruction corresponding to the processing of step 309. This syntax allows the circuit state reading unit 7 to read the circuit state information 6 named “state B” output from the circuit state output processing unit 5 and output the circuit state named “stateB”. It is an instruction to return to. The reason why the circuit state information 6 is given a name such as "state B" is to identify the circuit state information 6 when there are a plurality of circuit states to be returned.

Since the circuit state can be arbitrarily returned from the test vector side, it is possible to reduce waste such as executing the same transition a plurality of times. Also,
Since the process of returning the circuit state can be controlled from the test vector side, it is possible to realize a programming process of returning to an arbitrary circuit state according to the state of the circuit, and to efficiently describe the test vector.

By using the simulation method and apparatus according to the second embodiment of the present invention, it is possible to reduce the waste of executing the same transition a plurality of times in a simulation such as a state machine in which the same state exists a plurality of times. And the simulation time can be reduced.

[0026]

According to the simulation method of the first aspect, the circuit state of the common pattern is stored in a readable manner, and the circuit state of the common pattern is simulated a plurality of times by reading and simulating the circuit state when necessary. Simulation time can be reduced.

According to the simulation method of the second aspect, in a simulation using a plurality of test vectors, the simulation time of a test vector in which the first half of the test vector has the same pattern can be reduced.

According to the simulation method of the third aspect, in a simulation in which the same state exists a plurality of times, such as in a state machine, it is possible to reduce the waste of executing the same transition a plurality of times. Can be reduced.

According to the simulation apparatus of the fourth aspect, the same effect as that of the first aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a simulation device of the present invention.

FIG. 2 is an explanatory diagram showing a plurality of test vectors.

FIG. 3 is a flowchart of a simulation according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a state machine regarding a flow of a simulation method according to a second embodiment of the present invention.

FIG. 5 is a flowchart of a conventional test vector corresponding to the second embodiment.

FIG. 6 is a flowchart of a test vector when simulating the state machine according to the second embodiment of this invention.

FIG. 7 is a diagram illustrating a test vector description example describing a test vector flow according to the present invention;

FIG. 8 is a configuration diagram of a conventional simulation device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Net list 2 Test vector 3 Simulation execution processing part 4 Simulation result 5 Circuit state output processing part 6 Circuit state information 7 Circuit state reading processing part

Claims (4)

[Claims] 1. A simulation method for simulating a netlist describing circuit information based on a test vector describing a test pattern, and verifying that the circuit operates as specified. A simulation method including a step of storing a state in a readable manner separately from the information of the test vector. 2. The simulation according to claim 1, further comprising the step of reading the stored circuit state during the simulation, and the step of performing a simulation using a test vector different from that at the time of storing the circuit state after reading the circuit state. Method. 3. The method according to claim 1, further comprising the step of reading the stored circuit state during the simulation, and the step of controlling the circuit state during the simulation and the step of reading the circuit state using a test vector. Simulation method. 4. A simulation execution processing unit for simulating a netlist describing circuit information based on a test vector describing a test pattern, and a circuit state for outputting and storing a circuit state during the simulation of the simulation execution processing unit A simulation apparatus comprising: an output processing unit; and a circuit state reading processing unit that reads from the circuit state output processing unit and returns the simulation execution processing unit to the circuit state during the simulation.