JP2001282883A - Logic verification method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an operation simulation of a logic circuit including gate circuits and flip-flop circuits so as to easily clarify the cause of malfunction, regarding a logic verification method and a device thereof which verify the authenticity of the logic of the logic circuit. SOLUTION: Prior to executing operation simulation, a tag that distinguishes between a clock signal and a data signal is added to each input signal for objective logic circuit of the operation simulation. While the operation simulation is performed, in the case an output of a gate circuit in the logic circuit varies in response to the change of inputted clock signal, a tag of clock signal is added to the signal of the output, in the case the output varies in response to the change of inputted data signal, a tag of data signal is added to the signal of the output and these output signals are permitted to propagate, and in case a signal having a tag of data signal is inputted to a clock input terminal of the flip-flop circuit in the logic circuit, a message is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification method and apparatus for performing a simulation of a logic circuit including a gate circuit and a flip-flop circuit and verifying the correctness of the logic of the logic circuit.

[0002]

2. Description of the Related Art In the logic design of a logic circuit such as an LSI, the operation of the logic circuit is defined as a technique for verifying the correctness of the logic of the logic circuit before actually creating the logic circuit to be designed as hardware. Model created,
A technique is known in which a simulation is performed by giving a test pattern in which a clock signal and a data signal are treated the same to this model, and the simulation result is verified.

In general, a logic circuit including a gate circuit and a flip-flop circuit is designed so that the logic circuit operates in synchronization with a clock signal.
At this time, the clock signal is generally designed so that the clock signal arrives at the flip-flop circuit at the same time.

FIG. 6 is a diagram for explaining the arrival time of each signal to a flip-flop circuit in a logic circuit.

In the circuit 60 shown in FIG. 6, a clock tree is formed, and a plurality of flip-flop circuits 61 and 6 are formed.
The clock signal CK1 is designed to simultaneously reach the clock input pins 2, 63, and 64, respectively.

On the other hand, the control of the arrival time of the data signal to the data input pin of each circuit is caused by the fact that the signal propagation path is complicated, the number of signal propagation stages is different, and the delay of each circuit is different. Is difficult. In FIG. 6, each data signal D1, D2, D
3 and D4 are input to the data input pins of the flip-flop circuits 61, 62, 63 and 64 after passing through a complicated signal propagation path. For this reason, in designing a logic circuit,
If a design is used in which clock signals of different cycles are switched by control using a data signal, or the clock signal is stopped using a data signal to reduce power consumption, hazards due to variations in the arrival time of the data signal may cause a hazard. May occur and the logic circuit may malfunction.

If an asynchronous circuit due to a wiring error unintended by the designer exists in the logic circuit, a data signal propagates to the clock input pin of the flip-flop circuit, causing a malfunction.

[0008]

However, in the conventional logic verification technique, a simulation is performed by giving a test pattern in which a clock signal and a data signal are treated the same to a model. It is difficult to investigate the cause.

The present invention has been made in view of the above circumstances, and in verifying the correctness of logic of a logic circuit, when a malfunction occurs,
It is an object of the present invention to provide a logic verification method and its device that can easily determine the cause.

[0010]

In order to achieve the above object, a logic verification method of the present invention simulates the operation of a logic circuit including a gate circuit and a flip-flop circuit and verifies the correctness of the logic of the logic circuit. In the logic verification method, prior to execution of the operation simulation, each input signal of the logic circuit to be subjected to the operation simulation is
A tag for distinguishing whether each of the input signals is a clock signal or a data signal is attached, and during execution of the operation simulation, the output of the gate circuit in the logic circuit is the clock signal input to the gate circuit. When the output signal of the gate circuit is changed in accordance with the change of the data, the output signal of the gate circuit is tagged with a tag indicating that the output signal is a clock signal, and the output signal is propagated. When the signal changes in response to a change in the signal, the output signal of the gate circuit is tagged with a tag indicating that it is a data signal, the output signal is propagated, and the output signal is applied to the clock input terminal of a flip-flop in the logic circuit. A message is output when a signal with a tag indicating that it is a data signal is input.

According to the logic verification method of the present invention, a logic simulation for verifying an operation of a logic circuit is provided.
When the flip-flop circuit operates due to a change in the data signal, a message is output, so that the cause of the malfunction can be easily clarified.

According to another aspect of the present invention, there is provided a logic verification apparatus for simulating the operation of a logic circuit including a gate circuit and a flip-flop circuit to verify whether the logic of the logic circuit is correct. A signal definition unit that attaches a tag to each input signal of a logic circuit to be simulated for operation to determine whether each input signal is a clock signal or a data signal, and an output of a gate circuit of the logic circuit. When a change occurs in response to a change in the clock signal input to the gate circuit, the output signal of the gate circuit is tagged with a tag indicating that the signal is a clock signal, and the output signal is propagated. Is changed in response to a change in the data signal input to the gate circuit, a tag indicating that the output signal is a data signal is output from the gate circuit. A simulating unit for transmitting the output signal by attaching a signal indicating that the signal is a data signal to a clock input terminal of a flip-flop in the logic circuit. And an output unit.

A logic verifying apparatus according to the present invention has a signal defining section and a simulating section for separately handling the propagation of a clock signal and the propagation of a data signal, and the flip-flop circuit operates according to a change in the data signal. In this case, a message output unit for outputting a message is also provided, so that the cause of the malfunction can be easily clarified.

[0014]

Embodiments of the present invention will be described below.

First, an embodiment of the logic verification method according to the present invention will be described with reference to FIG.

FIG. 1 is a flowchart showing a routine executed in one embodiment of the logic verification method of the present invention.

In the logic verification method of the present embodiment, a change in signal state (from "H" level to "L" level or "L" level)
Change from level to 'H' level) as an event,
An event-driven system in which a model is driven by transmitting the event is employed.

First, before executing the logic verification, test pattern data, clock definition data, circuit diagram data, and delay information are prepared in advance.

The circuit diagram data is data of a circuit for performing logic verification, and a simulation model is created based on the circuit diagram data. The test pattern data is data in which a clock signal and a data signal are mixed and given to the created simulation model. The clock definition data is data defining a clock signal in the test pattern data.

In step S101, a test pattern in which a clock signal and a data signal are mixed is generated based on the test pattern data. When the test pattern is generated, an input event occurs in which a change from the “H” level to the “L” level or the change from the “L” level to the “H” level is an event. Therefore, this input event corresponds to the input signal according to the present invention.

Next, in step S102, each signal in the test pattern is defined as a clock signal and a data signal based on the clock definition data. That is, in this embodiment, a flag is set for an input event related to a clock signal.

In step S103, the simulation model created based on the circuit diagram data is provided with delay information and an input event generated in step S101 and flagged for the clock signal in step S102. , A simulation is performed.

FIG. 2 shows the simulation model.
This will be described with reference to FIG.

FIG. 2 is a diagram showing an example of a simulation model in one embodiment of the logic verification method of the present invention.

Simulation model 2 shown in FIG.
0 indicates a plurality of input pins 201, 202,.
Output pin 241 and first-stage circuits 211, 212, 21
3, 214, second-stage circuits 221 and 222, and a third-stage circuit 231. Each circuit 211, 212, 21
3, 214, 221, 222 and 231 are gate circuits and flip-flop circuits. Hereinafter, description will be made with reference to FIG.

The first simulation is for each input pin 2
, 208, the corresponding input events are input, and the first-stage circuits 211, 212, 21
The operation in each of 3,214 is simulated. When an input event is input, the output is
When the level changes from the “H” level to the “L” level or from the “L” level to the “H” level, an output event having this change as an event occurs. Therefore, this output event corresponds to the output signal according to the present invention. The output events generated by the first-stage circuits 211, 212, 213, and 214 are verified in step S104 and subsequent steps described below.

In step S104, the first-stage circuit 21
It is determined whether or not the output event generated by 1, 212, 213, 214 is due to an input event input to a clock input pin of a flip-flop circuit (abbreviated as FF in FIG. 1; the same applies hereinafter).

First-stage circuits 211, 212, 213, 2
When it is determined in step S104 that the output event generated by the input event 14 is caused by the input event input to the clock input pin of the flip-flop circuit, the input event input to the clock input pin of the flip-flop circuit is determined. It is determined whether a flag is set for the event (step S105).

When it is determined in step S105 that the flag is not set for the input event input to the clock input pin of the flip-flop circuit, a message including the determination time and the name (instance name) of the flip-flop circuit Is output (step S10).
6). This determination result in step 105 means that an event has been output due to an input event relating to the data signal input to the clock input pin of the flip-flop circuit. Thereafter, the output event for which such determination has been made is sent to the circuits 221 and 222 of the second stage.
, And thereafter, simulation and verification are sequentially performed until the output pin 241 of the simulation model 20 is reached.

On the other hand, in the above step S104,
When it is determined that the output event is not due to the input event input to the clock input pin of the flip-flop circuit, in step S107, it is determined whether the input event is flagged.

If it is determined in step S107 that the input event is not flagged, the first-stage circuit 21 is connected to the input pins of the second-stage circuits 221 and 222.
Simulations and verifications are sequentially performed until an output event generated by 1, 212, 213, 214 is input and thereafter reaches an output pin 241 in the simulation model 20. This determination result in step S107 means that an event has been output due to an input event relating to the data signal input to the data input pin of the flip-flop circuit or the input pin of the gate circuit.

On the other hand, in step S107, it is determined that the flag is set in the input event, or in step S10, the flag is set in the input event input to the clock input pin of the flip-flop circuit.
5, the circuits 221 and 221 in the second stage
The first-stage circuit 211, 22
A flag is set for the output event generated by 212, 213, 214 (step S108). Thereafter, the output event for which the flag has been set in step S108 is input to the input pins of the circuits 221 and 222 in the second stage, and thereafter simulation and verification are sequentially performed until the output event reaches the output pin 241 in the simulation model 20. Done.

Here, a specific example of error detection in this embodiment will be described below.

First, one specific example will be described with reference to FIG.

FIG. 3A is a circuit diagram showing a first logic circuit which is a part of the simulation model.
(B) is a timing chart of the first logic circuit.

The first logic circuit 30 shown in FIG.
An AND gate 31 and a flip-flop circuit 32 are provided. The AND gate 31 receives the data signal D5 and the clock signal CK2. In the flip-flop circuit 32, the output signal CK3 from the AND gate 31 is input to a clock input pin. As shown in FIG. 3B, the first logic circuit 30 supplies the "L" level data signal D5 to the AND gate 31.
Is input, the output signal CK3 from the AND gate 31 also maintains the “L” level, so that the switching operation of the flip-flop circuit 32 is not performed, and as a result, the power consumption can be reduced. is there. Here, the data signal D5 is input to the AND gate 31 after passing through a complicated signal propagation path, which is omitted in dotted lines in FIG. 3A. For this reason, it is difficult to control the time required for the data signal D5 to reach the AND gate 31. As shown in FIG. 3B, the clock signal CK having a predetermined cycle
If the "H" level data signal D5 arrives too early with respect to the rising edge of No. 2, a hazard H1 occurs in the output signal CK3 due to the rising edge of the data signal D5 and the falling edge of the clock signal CK2. Resulting in. Conversely, even if the arrival time of the data signal D5 at the AND gate 31 is delayed, a hazard H2 is generated in the output signal CK3 by the rising edge of the clock signal CK2 and the falling edge of the data signal D5. Would.

The error detection in the first logic circuit 30 where a hazard has occurred by the logic verification method of the present embodiment will be described with reference to FIG. Due to the input event (“L” level → “H” level) of the data signal D5 in the timing chart shown in FIG. 3B, the event from the hazard H1 (“L” level → “”) is output from the AND gate 31. H ′ level) occurs. However, no flag is set for the event (“L” level → “H” level) due to the hazard H1 (step S107). In the simulation at the next stage, an event (“L” level → “H” level) generated at the output of the AND gate 31 due to the hazard H1 in which the flag is not set is output to the clock input pin of the flip-flop circuit 32. When input, an event occurs at the output from flip-flop circuit 32. However, since the event (“L” level → “H” level) input to the clock input pin of the flip-flop circuit 32 is not flagged, the time at which the determination was made and the name of the flip-flop circuit ( A message including the instance name is output (step S106), indicating that the flip-flop circuit 32 is operating with the data signal. In addition, hazard H2
Event ('H' level → 'L' level)
When the signal is input to the clock input pin of the flip-flop circuit 32, a message including the time at which the determination is performed and the name of the flip-flop circuit is output in the same manner as described above (step S106). You can see that it is working. As described above, according to the logic verification method of the present embodiment, it can be easily determined that a timing error has occurred due to a data signal that is difficult to control.

Next, another specific example will be described with reference to FIG.

FIG. 4A is a circuit diagram showing a second logic circuit which is a part of the simulation model.
(B) is a timing chart of the second logic circuit.

The second logic circuit 40 shown in FIG.
It has a multiplexer 41 and a flip-flop circuit 42. In the multiplexer 41, the clock signal CK4 is input to the data input pin 411, the clock signal CK5 is input to the data input pin 412, and the data signal D6 is input to the select input pin. Clock signal CK4
And the clock signal CK5 are different from each other and have predetermined cycles, and the rising edge of the clock signal CK4 and the falling edge of the clock signal CK5 are synchronized. The flip-flop circuit 42
Is an output signal CK6 from the multiplexer 41 is input to a clock input pin. As shown in FIG. 4B, the second logic circuit 40 outputs the signal CK6 from the multiplexer 41 while the “L” level data signal D6 is being input to the select input pin of the multiplexer 41. , While the clock signal CK4 is output as it is and the data signal D6 of “H” level is input to the select input pin of the multiplexer 41,
This is a logic circuit for switching clock signals, in which the clock signal CK5 is output as it is as the output signal CK6 from the multiplexer 41. Here, the data signal D6 is omitted from the dotted line in FIG.
Since the signal is input to the select input pin of the multiplexer 41 after passing through a complicated signal propagation path, it is difficult to control the arrival time of the data signal D6 to the multiplexer 41.
As shown in FIG. 4B, if the arrival of the data signal D6 at the “H” level is delayed with respect to the rising edge of the clock signal CK4 and the falling edge of the clock signal CK5, the delay is delayed. However, the output signals CK6 from the multiplexer 41 have hazards H3 and H
4 occurs.

The detection of an error in the second logic circuit 40 where this hazard has occurred by the logic verification method of this embodiment will be described with reference to FIG. Due to the input event (“L” level → “H” level) of the data signal D6 in the timing chart shown in FIG. 4B, the event from the hazard H3 (“H” level → “L”) is output from the multiplexer 41. 'Level) occurs. However, this event by hazard ('H' level →
No flag is set for the “L” level (step S107). In the next simulation,
When an event (“H” level → “L” level) generated at the output from the multiplexer 41 and for which a flag is not set and which is caused by a hazard is input to the clock input pin of the flip-flop circuit 42, the flip-flop circuit 42 An event occurs at the output from. However, since the event (“H” level → “L” level) input to the clock input pin of the flip-flop circuit 42 is not flagged, the time at which the determination was made and the name of the flip-flop circuit are given. Is output (step S106).
It can be seen that the flip-flop circuit 42 operates with the data signal. Also, when an event due to the hazard H4 (“L” level → “H” level) is input to the clock input pin of the flip-flop circuit 42,
As described above, a message including the time at which the determination was made and the name of the flip-flop circuit is output (step S1).
06) It can be seen that the flip-flop circuit 42 operates with the data signal. As described above, according to the logic verification method of the present embodiment, it can be easily determined that a timing error has occurred due to a data signal that is difficult to control.

Next, an embodiment of the logic verification apparatus of the present invention will be described with reference to FIG.

FIG. 5 is a schematic diagram of a hardware configuration of an embodiment of the logic verification device of the present invention.

The logic verifying device 50 shown in FIG. 5 is a device for executing one embodiment of the above-described logic verifying method of the present invention, and includes an arithmetic unit 51 including a CPU, a memory, and the like.
0 and an output unit 520 such as a monitor.

Step S1 described with reference to FIG.
01 to step S108,
Done in That is, operation unit 510 corresponds to both the signal definition unit and the simulation unit according to the present invention. The output of the message in step S106 described with reference to FIG.
Is output, and a message including the determination time and the name (instance name) of the flip-flop circuit is output to the output unit 520. Therefore, the output unit 520 outputs
It corresponds to the message output unit according to the present invention.

As described above, in the logic verification method and the logic verification apparatus according to the present invention, the displayed message indicates that the flip-flop circuit is operating with the data signal. By the name (instance name) of the flip-flop circuit, the flip-flop circuit operating with the data signal can be specified. Further, since the clock signal and the data signal are defined respectively, when a timing error occurs, it is possible to know whether the cause is the clock signal or the data signal. Also, without timing errors,
Even when a flip-flop circuit is accidentally operating with a data signal, the flip-flop circuit operating with this data signal can be specified. The danger that a timing problem occurs due to the variation, that is, a potential timing problem can be known. Furthermore, if the message is displayed continuously, there is an asynchronous circuit in the logic circuit due to a wiring mistake not intended by the designer, and the data signal propagates to the clock input pin of the flip-flop circuit, causing a malfunction. Can be easily predicted. Therefore, by using the logic verification method and the logic verification device according to the present invention, it is possible to improve the design quality of the logic circuit and to improve the design TAT (Turn Around Tim Time).
e) can be shortened.

[0047]

As described above, according to the present invention, when verifying the correctness or incorrectness of the logic of a logic circuit, if a malfunction occurs, a logic verification method and a device for easily elucidating the cause thereof are provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a routine executed in an embodiment of the logic verification method of the present invention.

FIG. 2 is a diagram illustrating an example of a simulation model in one embodiment of the logic verification method of the present invention.

3A is a circuit diagram illustrating a first logic circuit which is a part of a simulation model, and FIG. 3B is a timing chart of the first logic circuit.

4A is a circuit diagram illustrating a second logic circuit which is a part of a simulation model, and FIG. 4B is a timing chart of the second logic circuit.

FIG. 5 is a schematic diagram of a hardware configuration of an embodiment in a logic verification device of the present invention.

FIG. 6 is a diagram for explaining the arrival time of each signal to a flip-flop circuit in a logic circuit.

[Explanation of symbols]

20 Simulation models 201, 202, 203, 204, 205, 206, 2
07, 208 input pin 241 output pin 211, 212, 213, 214 first-stage circuit 221, 222 second-stage circuit 231 third-stage circuit 50 logic verification device 510 operation unit 520 output unit

Claims (2)

[Claims] 1. A logic verification method for simulating the operation of a logic circuit including a gate circuit and a flip-flop circuit and verifying the correctness of the logic of the logic circuit. Each input signal of the logic circuit has a tag for distinguishing whether the input signal is a clock signal or a data signal, and an output of a gate circuit in the logic circuit is output during an operation simulation. When a change occurs in response to a change in the clock signal input to the gate circuit, the output signal of the gate circuit is tagged with a tag indicating that the signal is a clock signal, and the output signal is propagated. Changes in response to a change in the data signal input to the gate circuit, the output signal of the gate circuit A signal indicating that the signal is a data signal is input to a clock input terminal of a flip-flop in the logic circuit. A logic verification method characterized by outputting 2. A logic verification device for simulating the operation of a logic circuit including a gate circuit and a flip-flop circuit and verifying the correctness of the logic of the logic circuit, wherein each input signal of the logic circuit to be simulated is A signal definition unit for tagging whether each of the input signals is a clock signal or a data signal; and an output of a gate circuit of the logic circuit according to a change in the clock signal input to the gate circuit. When the output signal of the gate circuit changes, the output signal of the gate circuit is tagged with a tag indicating that it is a clock signal, and the output signal is propagated. A simulating unit for attaching a tag indicating that the output signal is a data signal to the output signal of the gate circuit and propagating the output signal, Logic verification apparatus characterized by comprising a message output section for outputting a message if the signal tagged representing data representing the data signal to the clock input terminal of the flip-flop in the logic circuit is inputted.