JP2003076739A - Apparatus, method and program for logical verification - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem wherein it is impossible to perform a precise logical verification of connecting parts with abnormal voltages in a logical circuit. SOLUTION: An apparatus for logical verification comprises a logical model simulating logical operations of logical elements composing a logical circuit, a file of voltage value information storing voltage value information defining pressure-resistant characteristics of electric elements composing the logical elements, a processing model, which is installed into the logical model, for voltage value information reading out voltage value information set in itself from the file of the voltage value information to compare with the voltage value information when the voltage value information is input and determining whether it is possible or not for voltage values input from outside to be accepted by the electric elements corresponding to itself based on the result of the comparison and a performing means of logical verification performing the logical verification of the logical circuit using the logical model based on the test pattern and the connecting information of the logical elements described in a net list of the logical circuit and also verifying the connecting parts with abnormal voltages according to a result of determination acquired by transmission of each voltage value information among each processing model.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification apparatus and method for handling a plurality of voltage value information in logic verification of a semiconductor integrated circuit such as an LSI, and a program for causing a computer apparatus to execute the method.

[0002]

2. Description of the Related Art In designing a semiconductor integrated circuit such as an LSI, there is a step of first assembling a function specification to be realized by the LSI. Specifically, it creates an external specification that specifies the behavior of the LSI when viewed from the outside, and creates an internal specification that specifies the internal hardware of the LSI to realize the functions required by this external specification. To do. Based on the internal specifications, functional design, logic design, circuit design, and layout design are sequentially performed.

To briefly explain these steps, in the function design step, the operation contents of the hardware such as the arithmetic unit, the register, and the bus inside the LSI and the mutual connection relationship are determined based on the internal specifications. That is, the schematic configuration of the LSI is determined in this functional design process. Next, in the logic design process, more specific logic circuit design at the gate level is performed based on the schematic configuration of the LSI determined in the function design process. A CAD system is generally used for this logic design. For example, using a workstation or a personal computer that constitutes a CAD system, a gate circuit is automatically generated (logic synthesis) from a logic description in a functional description language, or the logic circuit is input as a drawing and displayed by a dedicated editor. The layout and connection of the gate circuit is edited above.

The circuit to be designed includes not only digital circuit functional blocks but also various analog circuit functional blocks. In the circuit design process, the transistor circuit in the analog circuit block is designed. Finally, in the layout design process, the circuit diagram determined in the upstream process is converted into a layout pattern which is a layout and wiring of circuit elements having physical shapes and dimensions. This layout pattern data is used as mask pattern data in the exposure process during LSI manufacturing.

In each of the above-mentioned steps, design verification is carried out in order to eliminate design errors. In design verification, a simulation technique corresponding to each process is generally used. The simulation in this design verification is to prepare a model for describing a phenomenon process for a certain phenomenon and verify the result for some basic input parameters. For example, what simulates a digital operation (logical operation function) in a design circuit is called a logic simulation, and what mainly simulates an analog operation is called a circuit simulation.

That is, a logic simulator simulating a logical operation function is used for the logic verification of whether or not the logic circuit obtained in the logic design process operates as intended. The logic simulator gives an input signal sequence (test pattern) to a netlist (which summarizes the types of logic models that express the characteristics of gate circuits and their connection information) having the same meaning as logic circuits, It is possible to analyze the operation of the logic model in the circuit and extract the signals at each point in the circuit in time series.

On the other hand, a circuit simulator is used for the analog operation block obtained in the circuit design process.
The circuit simulator prepares a theoretical model of a semiconductor element expressing the characteristics of various semiconductor devices and analyzes the circuit characteristics at the transistor level. For example, from the input netlist, the node voltage is used as an unknown and the equation is formed and analyzed by Kirchhoff's law.

FIG. 14 is a diagram showing a configuration of a conventional logic verification device for performing a logic simulation on the above-mentioned designed circuit. In the figure, reference numeral 100 denotes a conventional logic verification device, which is specifically configured by a storage device for storing data for logic simulation and a computer device equipped with a program for executing logic verification using these.
101 is a netlist generated by extracting logic circuit connection information from logic circuit diagram data in the logic design process,
It is a file in which a logic model (for example, a logic gate model such as an AND model) and connection information (logic circuit connection information) of the logic models are described. A logic simulation model group 101a is a group of logic models that represent logic gates, and the logic circuit connection information of the netlist 101 represents a logic circuit configured from each logic model.

Reference numeral 101b is a basic model group for logic simulation in which basic models which are models forming a logical model are grouped, and the logical circuit connection information of the netlist 101 expresses a logical model composed of the respective basic models. The basic model is a model that represents a logical operation of a semiconductor element that constitutes a gate circuit, such as a model corresponding to a pch transistor. A test bench 102 is input at the time of logic verification, and is a file in which a test pattern and an expected output value are described. Reference numeral 103 is a logic verification executing means for executing the logic verification by inputting the above-mentioned data, and compares the processing result of the logic model with respect to the test pattern and the expected output value to verify whether or not the expected behavior is met. An output unit 104 outputs the verification result of the logic verification executing unit 103, and includes an output control mechanism such as data format conversion at the output. Reference numeral 105 denotes a verification result file in which the verification results of the logic verification executing means 103 are collected, and is data stored in the storage device of the computer device constituting the logic verification device 100.

Next, the operation will be described. FIG. 15 shows FIG.
4 is a flowchart showing the logic verification operation by the logic verification device in FIG. 4, and the conventional logic verification will be described with reference to this figure. First, the logic verification device 100 uses the netlist 101
Is read and developed as data having the same meaning as the logic circuit diagram on the internal memory (step ST100). Next, the test bench 102 is read, and the logic verification execution means 103 reads out the test pattern information and the expected value (output expected value) of the processing result by the logic model in which the signal of the pattern is input and processed. Subsequently, the logic verification executing means 103 sequentially applies the test pattern (input signal sequence) to the netlist 101, and sequentially propagates the processing result processed according to the logical model to the subsequent logical model (step ST101).

At this time, the logic verification executing means 103 compares the output expected value with the processing result processed according to the logical model to dynamically determine whether the netlist 101 expanded on the memory is operating as expected. To verify (step S
T102). This logic verification operation is repeated until all test patterns have been input (step ST10).
3). Finally, when all the test patterns have been input, the logic verification execution means 103 collectively outputs the verification results to the output unit 104. The output unit 104 converts the input verification result data into an appropriate format and verifies the verification result file 1
It is output as 05 (step ST104).

Here, the logic simulation as described above does not have a clear concept of "voltage value" as in circuit simulation, but incorporates the concept of "signal strength". That is, in the conventional logic simulation, in addition to the steady values 1 and 0 as the signal values to be handled, digital values indicating the unknown state and the high impedance state that causes the signal strength change and the transition thereof are set.

[0013]

Since the conventional logic verification device is configured as described above, there is a problem that it is not possible to perform accurate logic verification for different voltage connection parts in the design circuit.

The above problems will be described in detail. As described above, since the conventional logic simulation incorporates the concept of “signal strength”, the information corresponding to voltage is simply “strong or weak”. Will be treated. For this reason, the design circuit has multiple voltage values (for example,
In the case of a design having 3.3V system and 5.0V system), the voltage value must be ignored in the logic verification. Therefore, the accurate logic verification of the different voltage connection cannot be performed,
There was a situation in which the defect was discovered only by evaluating the actual machine. For example, even if a 3.3V element is used where a 5.0V element should be used, the defect may not be extracted because the voltage value is ignored in the conventional logic verification. In such a case, the breakdown voltage of the 3.3V element is exceeded because the withstand voltage of the 3.3V element is exceeded at the time of evaluation in an actual machine.

FIG. 16 is a diagram for explaining the problems of the conventional logic verification device. As shown, the netlist 100
In the connection information of the logic model described in, the voltage value information (in the illustrated example, for the illustrated example, for the signal line that travels between a plurality of voltage systems (3.3V system and 5.0V system in the illustrated example)
4. Input signal from 3.3V system circuit to 5.0V system circuit,
Information for identifying each input signal from the 0V system circuit to the 3.3V system circuit is not added (cannot be added). Further, the voltage value information is not expressed in the test bench 102 as in the netlist 101. Therefore, in the logic verification device 100, since the voltage value information is not added to the input information itself, the logic verification in consideration of the “voltage value” cannot be performed. As a result, the logic verification device 100 provides the verification result file 105 in which accurate logic verification has not been performed on the different voltage system.

On the other hand, in the circuit simulation capable of accurately handling the voltage value, it is necessary to perform complicated calculation such as node analysis, and the signal change is limited to a part in a large-scale circuit. There is a problem that comprehensive verification cannot be performed from the viewpoint of.

The present invention has been made in order to solve the above problems, and the input / output of each logic simulation model constituting a design of an element having a function of adding, recognizing and judging voltage value information. / A logic verification device that enables logic verification in consideration of voltage values by incorporating it in an input / output unit and performing logic verification using those models for logic simulation, a method thereof, and a program for causing a computer device to execute the method. The purpose is to

[0018]

SUMMARY OF THE INVENTION A logic verification device according to the present invention comprises a logic model for simulating a logic operation of a logic element forming a logic circuit to be logic-verified, and a withstand voltage characteristic of an electric element forming the logic element. The voltage value information file that stores the voltage value information that defines the voltage value information and the voltage value information that is incorporated in the logic model and is input from the outside, reads the voltage value information that should be set for itself from the voltage value information file, and Recognizing the voltage values specified by the voltage value information and the voltage value information set for itself, the comparison is performed, and the input voltage value from the outside can be accepted by the electric element corresponding to itself based on the comparison result. The voltage value information processing model for determining whether or not, the test pattern to be given to the logic circuit of the logic verification target, the expected value, and the connection information of the logic element described in the netlist of the logic circuit. Based on the above, the logic verification of the logic circuit using the logic model is performed, and from the determination result obtained by propagating each voltage value information between each voltage value information processing model, between different voltage connection parts in the logic circuit. And a logic verification executing means for verifying the above.

The logic verification apparatus according to the present invention comprises voltage value information processing model adding means for inputting the logic model and the voltage value information processing model and incorporating the voltage value information processing model into the logic model.

The logic verification apparatus according to the present invention extracts voltage value information, logic elements and their connection information from logic circuit diagram data in which voltage value information is preset, and creates a voltage value information file and a netlist of logic circuits. It is provided with a voltage value information file / netlist generating means for generating.

The logic verification apparatus according to the present invention extracts voltage value information from layout pattern data in which voltage value information is preset and generates voltage value information file, voltage value information file generating means, and layout pattern data. A netlist generating unit that extracts a logic element and its connection information from the logic circuit diagram data having a one-to-one configuration and generates a netlist of the logic circuit is provided.

In the logic verification device according to the present invention, the voltage value information file stores abnormal voltage value information arbitrarily set in addition to the voltage value information, and the abnormal voltage value information is stored in the logic circuit to be logically verified. It is equipped with an abnormal voltage information propagation model propagated by.

The logic verifying device according to the present invention uses the information extracted from the layout pattern data in which the voltage value information is set in advance, and the verification result data by the above-described logic verifying device and the layout pattern data have a one-to-one structure.
Is provided with a coincidence verification unit that compares the verification result data by the above-described logic verification device using the information extracted from the logic circuit diagram data corresponding to the above.

The logic verification device according to the present invention comprises a specific information display means for extracting specific information contained in the verification result data and displaying it on the logic circuit diagram and / or layout pattern.

In the logic verification method according to the present invention, the voltage value information defining the withstand voltage characteristics of the electric elements forming the logic element in the logic circuit to be logic-verified is set as a voltage value information file, and the logic of the logic element is set. When voltage value information is input from the outside to the logic model that simulates the operation, the voltage value information that should be set for itself is read from the voltage value information file, and the voltage value information from the outside and the voltage value information set for itself are read. A voltage value information processing model that incorporates a voltage value information processing model that recognizes each specified voltage value and performs comparison, and determines whether or not an input voltage value from the outside can be accepted by an electric element corresponding to itself based on the comparison result The voltage value information processing function addition step, the test pattern to be given to the logic circuit of the logic verification target, the expected value, and the connection information of the logic element described in the logic circuit netlist. Based on the determination result obtained by propagating each voltage value information between each voltage value information processing model, the logic verification of the logic circuit using the logic model is performed. And a logic verification step for performing verification.

In the logic verification method according to the present invention, the voltage value information, the logic element and the connection information thereof are extracted from the logic circuit diagram data in which the voltage value information is preset, and the voltage value information file and the net list of the logic circuit are extracted. It is provided with a voltage value information file / netlist generating step to be generated.

According to the logic verification method of the present invention, the voltage value information is extracted from the layout pattern data in which the voltage value information is set in advance, and the voltage value information file generating step of generating the voltage value information file, and the layout pattern data are generated. And a netlist generation step of generating a netlist of the logic circuit by extracting logic elements and their connection information from the logic circuit diagram data having a one-to-one correspondence.

In the logic verification method according to the present invention, the verification result data by the logic verification method using the information extracted from the layout pattern data in which the voltage value information is preset and the layout pattern data have a one-to-one correspondence. It is provided with a match verification step of performing verification by comparing verification result data by a logic verification method using information extracted from the logic circuit diagram data.

A logic verification program according to the present invention includes a logic model for simulating a logic operation of a logic element forming a logic circuit to be logic-verified, and voltage value information defining a withstand voltage characteristic of an electric element forming the logic element. The voltage value information file to be stored is incorporated into the logic model, and when the voltage value information is input from the outside, the voltage value information that should be set to itself is read from the voltage value information file and set to the external voltage value information and to the self. The voltage value for recognizing the voltage value specified by each of the voltage value information is compared, and based on the comparison result, it is determined whether or not the input voltage value from the outside can be accepted by the corresponding electric element. Based on the information processing model, the test pattern to be given to the logic circuit of the logic verification target, the expected value, and the connection information of the logic element described in the net list of the logic circuit, A logic that performs logic verification of the logic circuit using the model and verifies between different voltage connection parts in the logic circuit from the judgment result obtained by propagating each voltage value information between each voltage value information processing model. The computer is caused to function as a verification execution means.

The logic verification program according to the present invention inputs a logic model and a voltage value information processing model, and causes the computer to function as a voltage value information processing model adding means for incorporating the voltage value information processing model into the logic model. is there.

A logic verification program according to the present invention extracts voltage value information, logic elements and their connection information from logic circuit diagram data in which voltage value information is preset, and creates a voltage value information file and a logic circuit netlist. The computer is caused to function as a voltage value information file / netlist generating means to be generated.

The logic verification program according to the present invention comprises voltage value information file generating means for extracting voltage value information from layout pattern data in which voltage value information is preset and generating a voltage value information file, layout pattern data and configuration. Is to make a computer function as a netlist generating means for generating a netlist of a logic circuit by extracting logic elements and their connection information from the logic circuit diagram data corresponding to one to one.

The logic verification program according to the present invention uses the information obtained by extracting the voltage value information from the preset layout pattern data, and the verification result data by the above-mentioned logic verification program and the layout pattern data have a one-to-one structure. That is, the computer is made to function as a match verification unit that compares the verification result data by the above-described logic verification program using the information extracted from the logic circuit diagram data corresponding to the above, and performs the match verification.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a diagram showing the configuration of a logic verification device according to a first embodiment of the present invention. In the figure, reference numeral 1 is a logic verification device according to the first embodiment, which performs logic verification dealing with voltage value information. Reference numeral 2 denotes a conventional netlist for logic simulation, which is a file in which a logic model to which voltage value information is not added and logic circuit connection information are described. Reference numeral 2a is a logic simulation model group in which logic models expressing logic gates are combined, and the logic circuit connection information of the netlist 2 expresses a logic circuit composed of each logic model. Reference numeral 2b is a basic model group for logic simulation, which is a group of basic models which are models constituting the logical model, and expresses a logical model composed of each basic model by the logic circuit connection information of the netlist 2. The basic model is a model that represents a logical operation of a semiconductor element that constitutes a gate circuit, such as a model corresponding to a pch transistor.

Reference numeral 3 is a voltage value information processing model which is a feature of the present invention, and it is "destroyed due to exceeding the withstand voltage" by comparing the recognition of the input voltage value with the voltage value set by itself. Etc., the physical phenomenon is replaced with logical information such as “output an indefinite value” and propagated to another basic model, or information to be reported to the designer is generated. The voltage value information processing model 3 is specifically a program written in a function description language that the logic verification device 1 can understand, and operates as one function of the logic verification device 1. Reference numeral 4 is a test bench input at the time of logic verification, and is a file in which a test pattern and an expected output value are described. The test pattern of this test bench incorporates voltage value information in addition to the conventional signal value information. This voltage value information may be encoded as simple information so that the voltage value information processing model 3 can restore the original voltage value. For example, the keyword “A” is propagated as data corresponding to a voltage value of 3.3V.

Reference numeral 5 is a logic verification executing means for executing logic verification, which is used as a basic model constituting the operation verification result of the logic model obtained by comparing the processing result of the logic model with respect to the test pattern and the expected output value. The voltage value information transmitted by the added voltage value information processing model 3 is output as a verification result. An output unit 6 outputs the verification result data from the logic verification executing unit 5, and includes an output control mechanism that performs data format conversion when outputting the verification result data as the display unit 7 and the verification result file 8. Reference numeral 7 denotes a display means, which is a CR of a computer device that constitutes the logic verification device 1.
It is realized by T and LCD. 8 is a logic verification executing means 5
It is a verification result file (verification result data) in which verification results including voltage value information from are collected, and is data stored in the storage device of the computer device configuring the logic verification device 1.

Numeral 9 is a voltage value information processing model adding means for generating a logic simulation basic model group 11b in which the voltage value information processing model 3 is incorporated in the logic simulation basic model group 2b. Reference numeral 10 is a voltage value information file describing voltage value information relating to an arbitrary basic model or logic model, which is read by the voltage value information processing model 3 at the time of logic verification and becomes basic data of voltage value information.
Reference numeral 11 denotes a logic simulation netlist expanded in the memory of the logic verification device 1, and the logic simulation model group 11a is based on the logic circuit connection information.
Constitutes data equivalent to the logic circuit to be verified. Reference numeral 11a denotes a logic simulation model group, which is a collection of logic models including a basic model incorporating the voltage value information processing model 3. Reference numeral 11b is a basic model group for logic simulation, which is a group of basic models incorporating the voltage value information processing model 3.

FIG. 2 is a block diagram showing the configuration of the voltage value information processing model in FIG. In the figure, 3a is a voltage value information recognition unit which is one component of the voltage value information processing model 3, and restores the voltage value information 12a received from the logic verification executing means 5 to the actual voltage value. Reference numeral 3b is a voltage value information determination unit that compares the voltage value restored by the voltage value information recognition unit 3a with the specified voltage value information 13 from the voltage value information file 10 to determine the magnitude relationship. A reporting unit 3c receives the processing result by the voltage value information judging unit 3b, and controls the voltage value information adding unit 3d based on the processing result by the voltage value information judging unit 3b. 3d is a voltage value information addition unit,
Under the control of the reporting unit 3c, the voltage value information 12b to be output to the voltage value information processing model 3 (hereinafter referred to as the next-stage element) corresponding to the next-stage basic model is generated and output. 12
a and 12b are voltage value information, which propagates between the voltage value information processing models 3 during the logic verification. Reference numeral 13 is defined voltage value information including a reference voltage value and allowable voltage value information, which is data which the voltage value information processing model 3 appropriately reads from the voltage value information file 10 and supplies to the internal voltage value information determination unit 3b. . The components of the voltage value information processing model 3 are specifically programs created in a language understandable by the logic verification device 1. In addition, the same components as those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 3 is a diagram showing an example of the voltage value information file in FIG. As shown in the figure, the voltage value information file 10 has a comment line beginning with //
OP. CHIP. TIMERB. G01_ID1 and SD
A description field for describing an instance ID or a module name for specifying an addition target of the voltage value information processing model 3 such as a RAM, a description field for reference voltage value information,
It is composed of a description field of the allowable voltage value information (for the reference voltage value information, the allowable voltage value is designated by an absolute value or a relative value).

Next, the operation will be described. FIG. 4 is a flowchart showing the operation of the logic verification device according to the first embodiment, and the logic verification according to the first embodiment will be described with reference to this flow chart. First, the logic verification device 1 uses the netlist 2 for the conventional logic simulation, the netlist 2
The logic simulation model group 2a whose connection relationship is defined by the logic circuit connection information in the above, the logic simulation basic model group 2b that constitutes the logic simulation model group 2b, the voltage value information processing model 3, the logic simulation test bench 4, and the voltage value information Read file 10 (step ST
1).

In the logic verification device 1, the netlist 2 and the logic simulation model group 2a whose connection relationship is defined by the logic circuit connection information in the netlist 2 are expanded in the internal memory and equivalent to the logic circuit diagram. Of the net simulation 11 and the logic simulation model group 11a whose connection relationship is defined by the logic circuit connection information in the net list 11. At this time,
Voltage value information processing model adding means 9 in the logic verification device 1
Reads out the instance ID or module name for specifying the addition target of the voltage value information processing model 3 described in the voltage value information file 10 as shown in FIG. 3, and follows the basic model for logic simulation. The voltage value information processing model 3 is incorporated into the basic model in the group 2b (step ST2). Specifically, the voltage value information processing model 3 is incorporated into each of the input, output, and input / output ports of the basic model. These steps ST1 and ST2 correspond to the voltage value information processing model addition step.

Next, the logic verification executing means 5 reads from the test bench 4 a test pattern (an input signal sequence in which a specific value is set for logic verification) and an expected output value for the logic model that processed this test pattern, The test patterns are sequentially supplied to the netlist 11. This starts the logic verification operation. In the netlist 11, the test patterns are supplied to the logic models in the logic simulation model group 11a, and the results processed according to the test patterns are successively propagated to the next-stage element whose connection relationship is defined by the logic circuit connection information. . At this time, the voltage value information processing model 3 incorporated in the basic model forming the logic model reads the voltage value information 12a from the test pattern and performs a process related to the voltage value (step ST3).

A specific processing flow in the voltage value information processing model 3 will be described. First, the read voltage value information 12a is input to the voltage value information recognition unit 3a. The voltage value information recognition unit 3a decodes the voltage value information 12a to restore the original voltage value, and outputs it to the voltage value information determination unit 3b.
For example, when the voltage value information in which the keyword “A” is described is received, the voltage value of 3.3 V corresponding to this is restored. When the input voltage value information is the voltage value information 12b from the preceding element, the voltage value information recognizing unit 3 determines how many voltage values the processing request from the basic model defines.
recognized by a.

In the voltage value information judging section 3b, first, the specified voltage value information specified by itself is read out from the voltage value information file 10, and based on the reference voltage value information and the allowable voltage value information set in this, the information of its own approval is given. Calculate the voltage value. For example, when the reference voltage information set for itself is “3.3” and the allowable voltage value information is “+1.0”, the allowable voltage value is 4.3.
V (= 3.3 + 1.0). After that, the voltage value information determination unit 3b should compare the restored voltage value and the allowable voltage value by arithmetic comparison to determine the magnitude relationship between the allowable voltage value and propagate the voltage value information to the next-stage element. Determine whether or not. The propagation direction of the voltage value information is not limited to input → output, input / output → output, and so-called backflow of output → input is possible.

The processing result by the voltage value information judging section 3b is
It is input to the reporting unit 3c. The reporting unit 3c controls the voltage value information adding unit 3d based on the processing result of the voltage value information determining unit 3b. Specifically, when the voltage value information determination unit 3b determines that the voltage value is less than or equal to the allowable voltage value, the voltage value information addition unit 3d is controlled to propagate the logical value and the voltage value information 12b to the next-stage element. As a result, the voltage value information adding unit 3d outputs the logical value related to the processing result of the test pattern by the basic model in which it is incorporated and the voltage value information 12b which is the processing result of its own voltage value information to the next-stage element. To do. Here, the voltage value information 12b corresponds to information defining what voltage value of V the self is outputting.

On the other hand, if it is larger than the allowable voltage value, first, warning message information indicating that the next-stage element is destroyed is generated and output to the logic verification executing means 5. The logic verification executing means 5 sends the warning message information to the output unit 6. The output unit 6 converts the warning message information into a format displayable on the display unit 7 or a format corresponding to the verification result file 8 and outputs the warning message information. This allows the designer to know by logic verification that the voltage value setting was inadequate. As the warning message, for example, “Warning! At time AAA, the next-stage element BBB has an abnormal voltage value CCC
Destroyed by (V). The allowable voltage value of the next-stage element BBB is DDD (V). Warning number EEE-warning count FFF (cumulative number of warnings) "is output.

At the same time, the reporting unit 3c controls the voltage value information adding unit 3d so as to generate information indicating that the input voltage value from the device cannot be accepted. As a result, the voltage value information adding unit 3d generates information indicating that the input voltage value from the element cannot be accepted and propagates it to the next-stage element. For example, if the voltage value information 12a, 12b is information indicating the keyword "A", the information indicating the unacceptability is assigned with a keyword such as "ZZZ" that does not overlap with this information.

Further, the logic verification processing means 5 is sequentially input with the voltage value information which is the processing result by the voltage value information processing model 3 and the processing result of the logical model for the test pattern supplied to the netlist 11. As a result, the logic verification executing means 5 compares the input processing result with the expected output value and dynamically verifies whether the netlist 11 expanded on the memory is operating as expected.
The operation so far corresponds to step ST4.

This logic verification operation is performed by the logic verification execution means 5.
Is repeated until all the test patterns have been input to the netlist 11 (step ST5). Finally, when all the test patterns have been input, the logic verification executing means 5 collectively outputs the verification results including the voltage value information to the output unit 6.
Send to. The output unit 6 converts the input verification result data into an appropriate format and outputs it to the verification result file 8 and the display means 7 (step ST6). Step ST3 described above
The processing from to ST6 corresponds to the logic verification step.

As described above, according to the first embodiment, the circuit simulation technique of "handling a voltage value" is incorporated in the logic simulation technique, that is, the voltage value information processing model 3 is added to the basic model forming the logic model. Since it is possible to handle the information about the voltage value by incorporating, the netlist 2 for the conventional logic simulation is used.
It is possible to perform accurate logic verification of different voltage connection parts while using.

Embodiment 2. FIG. 5 is a diagram showing the configuration of the logic verification device according to the second embodiment of the present invention. In the figure, 1A is a logic verification device according to the second embodiment, which performs logic verification using voltage value information using logic circuit diagram data 14 in which voltage value information is set. Reference numeral 8a denotes a verification result file (verification result data) in which the verification results by the logic verification device 1A are summarized. In addition to the processing result according to the logic model for the test pattern, the logic circuit diagram data 14
It is configured to include the processing result of the voltage value information using. 1
A voltage value information file 0a is generated by the voltage value information / netlist generating means 15 using the voltage value information extracted from the logic circuit diagram data 14. Reference numeral 14 is logic circuit diagram data in which voltage value information is preset, and a netlist is generated by extracting connection information of the logic circuit from this data. Here, with respect to the conventional logic circuit diagram data, the designer specifies each element on the display screen using the CAD system and sets the voltage value, or the symbol name of each element is set. The logic circuit diagram data 14 in which the voltage value information is preset is generated by, for example, installing a program that determines and automatically sets the voltage value.

Reference numeral 15 is a voltage value information / netlist generating means (voltage value information file / netlist generating means), which uses the information extracted from the logic circuit diagram data 14 to generate the voltage value information file 10a and the netlist 16. To generate. Reference numeral 16 is a net list, which is generated using the voltage value information / net list generation means 15 using the information for specifying the logic model extracted from the logic circuit diagram data 14 and the logic circuit connection information. A logical simulation model group 16a is constituted by a logical model in which the connection relation is defined by the logic circuit connection information described in the netlist 16 so as to be equivalent to the logic circuit diagram of the logic verification target. 1
6b is a basic model group for logic simulation, which is a group of basic models constituting the logical model in the logical simulation model group 16a. The voltage value information processing model 3 is previously incorporated in the input, output, and input / output ports of the basic model. ing. In addition, the same components as those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. FIG. 6 is a flowchart showing the operation of the logic verification device according to the second embodiment, and the logic verification according to the second embodiment will be described with reference to this flow chart. First, the logic verification device 1A includes a test bench 4 for logic simulation, logic circuit diagram data 14,
The logic simulation model group 16a and the logic simulation basic model group 16b constituting the logic simulation model group 16a are read (step ST1a).

Next, the voltage value information in the logic verification device 1A /
The net list generating means 15 extracts the voltage value information from the logic circuit diagram data 14 and generates the voltage value information file 10a in the format as shown in FIG. At the same time, the voltage value information / netlist generating means 15 extracts the information for specifying the logic model and the logic circuit connection information from the logic circuit diagram data 14 to generate the netlist 16. As a result, the logic simulation model group 16a composed of the logic models whose connection relationships are defined by the logic circuit connection information described in the netlist 16
By the logic simulation basic model group 16b (the voltage value information processing model 3 is incorporated in advance) constituting the same, data equivalent to the logic circuit diagram of the logic verification target is stored in the memory in the logic verification device 1A. It is developed (step ST2a). The processes from step ST1a to step ST2a correspond to the voltage value information file / netlist generating step.

After that, the logic verification operation started by reading the test pattern from the test bench 4 (step S
The processing from T3 to step ST6) is the same as that of the above-described first embodiment, and thus the duplicated description will be omitted. The verification result file 8a obtained by this logic verification operation includes the processing result based on the voltage value information from the logic circuit diagram data 14.

As described above, by incorporating the voltage value information processing model 3 in the input, output and input / output ports of the basic model in the logical simulation basic model group 16b in advance, the voltage value information processing model adding means 9 Can be omitted. Further, the logic value verification information processing model addition means 9 may be provided in the logic verification device 1A according to the second embodiment so that the logic simulation basic model group 16b in which the voltage value information processing model 3 is incorporated is not used. . In this case, which basic model the voltage value information processing model 3 is incorporated into is determined based on the voltage value information file 10a generated from the information from the logic circuit diagram data 14. These processes are automatically performed by the logic verification device 1A.

As described above, according to the second embodiment, the logic circuit diagram data 14 is provided with the function of extracting preset voltage value information. Therefore, the voltage value information from the logic circuit diagram data 14 is extracted from the logic circuit diagram data 14. Forward annotation is possible, and accurate logic verification of different voltage connection parts can be performed.

Third Embodiment FIG. 7 is a diagram showing the configuration of the logic verification device according to the third embodiment of the present invention. In the figure, 1B is a logic verification device according to the third embodiment, which performs a logic verification using voltage value information by using layout pattern data 17 in which voltage value information is set. 8b
Is a verification result file (verification result data) by the logic verification device 1B according to the third embodiment, and includes the processing result of the voltage value information using the layout pattern data 17 in addition to the processing result according to the logic model for the test pattern. Composed of. 10b is a voltage value information file,
The voltage value information is generated by the voltage value information file generating means 19 using the voltage value information extracted from the layout pattern data 17. Reference numeral 17 is layout pattern data in which voltage value information is set, and circuit elements having a physical shape and dimensions are placed and wired in the circuit diagram determined in an upstream process such as logic design or circuit design in the layout design process. Obtained. Here, with respect to the conventional layout pattern data, the designer specifies each element one by one on the display screen using the CAD system and sets the voltage value, or the layout pattern is determined and the voltage is determined. The layout pattern data 17 in which the voltage value information is preset is generated by installing a program for automatically setting the value.

18 is layout pattern data 17 and 1
It is the logic circuit diagram data having the logic circuit connection information corresponding to the pair 1, and the netlist 21 is generated by extracting the connection information of the logic circuit from this data. 19
Is a voltage value information file generating means for generating the voltage value information file 10b using the information extracted from the layout pattern data 17. Reference numeral 20 is a netlist generating means, which generates a netlist 21 using the information extracted from the logic circuit diagram data 18. Reference numeral 21 is a netlist for logic simulation, which is generated using the information for specifying the logic model extracted from the logic circuit diagram data 18 by the netlist generating means 20 and the logic circuit connection information. 21
Reference numeral a is a model group for logic simulation, and is composed of a logic model in which the connection relationship is defined by the logic circuit connection information described in the netlist 21 so as to be equivalent to the logic circuit diagram of the logic verification target. Reference numeral 21b is a basic model group for logic simulation, which is a group of basic models constituting the logical model in the logical simulation model group 21a. The voltage value information processing model 3 is previously incorporated in the input, output and input / output ports of the basic model. ing. The same components as those in FIGS. 1 and 5 are designated by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. FIG. 8 is a flowchart showing the operation of the logic verification device according to the third embodiment, and the logic verification according to the third embodiment will be described with reference to this flow chart. First, the logic verification device 1B reads the test bench 4 for logic simulation, the layout pattern data 17, the logic circuit diagram data 18, the logic simulation model group 21a and the logic simulation basic model group 21b constituting the logic simulation model group 21b (step ST1).
b).

Next, the voltage value information file generating means 19 in the logic verification device 1B causes the layout pattern data 17 to be generated.
The voltage value information is extracted from the file to generate the voltage value information file 10b in the format as shown in FIG. At the same time, the netlist generating means 20 determines that the logic circuit diagram data 1
The information for specifying the logical model and the logical circuit connection information are extracted from 8 to generate the netlist 21. As a result, a logical simulation model group 21a including a logical model whose connection relationship is defined by the logical circuit connection information described in the netlist 21 and a logical simulation basic model group 21b (voltage value information processing) forming the logical simulation model group 21a. Model 3 is pre-installed)
Data equivalent to the logic circuit diagram of the logic verification target is developed on the memory in the logic verification device 1B (step ST2).
b). The processes from step ST1b to step ST2b correspond to the voltage value information file generating step and the netlist generating step.

After that, the logic verification operation started by reading the test pattern from the test bench 4 (step S
The processing from T3 to step ST6) is the same as that of the above-described first embodiment, and thus the duplicated description will be omitted. The verification result file 8b obtained by this logic verification operation includes the processing result by the voltage value information from the layout pattern data 17.

As described above, by incorporating the voltage value information processing model 3 in the input, output, and input / output ports of the basic model in the logical simulation basic model group 21b in advance, the voltage value information processing model adding means 9 is added. Can be omitted. In addition, the logic value verification information processing model addition means 9 may be provided in the logic verification device 1B according to the third embodiment so that the logic simulation basic model group 21b in which the voltage value information processing model 3 is incorporated is not used. . In this case, which basic model the voltage value information processing model 3 is incorporated into is determined based on the voltage value information file 10b generated from the information from the layout pattern data 17. These processes are automatically performed by the logic verification device 1B.

As described above, according to the third embodiment, since the layout pattern data 17 has the function of extracting preset voltage value information, the back annotation from the layout pattern data 17 of the voltage value information is performed. It is possible to perform accurate logic verification of different voltage connection parts.

Fourth Embodiment FIG. 9 is a diagram showing the configuration of the logic verification device according to the fourth embodiment of the present invention. In the figure, 1C is a logic verification device according to the fourth embodiment, which verifies the range of influence when an abnormal voltage occurs by a logic simulation. The abnormal voltage value refers to a high voltage value assuming static electricity or the like generated outside the semiconductor chip finally manufactured after finishing the design process. Three
A is a predetermined basic model in the logical simulation basic model group 22b and a voltage value information processing model (abnormal voltage information propagation model) incorporated between the connection paths thereof, which is an assumed abnormal voltage value read from the voltage value information file 10c. Of the voltage value information adding section for outputting to the next-stage element. This voltage value information processing model 3A is specifically a program written in a function description language that can be understood by the logic verification device 1C, and operates as one function of the logic verification device 1C. Reference numeral 8c is a verification result file (verification result data) of the logic verification device according to the fourth embodiment, which is configured to include information including the influence range of the logic circuit due to the assumed abnormal voltage value.

Reference numeral 10c is a voltage value information file which describes voltage value information relating to an arbitrary basic model or logic model.
In addition to the above voltage value information, an assumed abnormal voltage value read into the voltage value information processing model 3A at the time of logic verification is included. Reference numeral 22 denotes a logic simulation netlist expanded in the memory of the logic verification device 1C, and the logic simulation model group 22a constitutes data equivalent to the logic circuit to be verified based on the logic circuit connection information. 22a is a model group for logic simulation,
It is a compilation of logical models consisting of basic models incorporating the voltage value information processing model 3A. Reference numeral 22b is a basic model group for logic simulation, which is a group of basic models incorporating the voltage value information processing model 3A. In addition, the same components as those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 10 is a diagram showing an example of the voltage value information file in FIG. Similar to FIG. 3, the voltage value information file 10c includes comment lines, voltage value information processing models 3 and 3A.
In addition to the description field that describes the instance ID or module name for specifying the target to be added, the description field of the reference voltage value information, the description field of the allowable voltage value information, and the assumption that the designer freely sets the abnormal voltage value. It has an abnormal voltage value description field (in the example shown, TO
P. CHIP. TIMERB. G01_ID1. ND5
"30" is described as the abnormal voltage value corresponding to the node 3).

Next, the operation will be described. First, the logic verification device 1C includes a conventional logic simulation netlist 2, a logic simulation model group 2a in which a connection relation is defined by logic circuit connection information in the netlist 2, and a logic simulation basic component constituting the logic simulation model group 2a. The model group 2b, the voltage value information processing models 3 and 3A, the test bench 4 for logic simulation, and the voltage value information file 10c are read.

In the logic verification device 1C, the netlist 2,
Logic simulation model group 2a whose connection relationship is defined by the logic circuit connection information in this netlist 2
Is expanded in an internal memory to generate a netlist 22 that is data equivalent to a logic circuit diagram and a logic simulation model group 22a whose connection relationship is defined by logic circuit connection information in this netlist 22. At this time, the voltage value information processing model addition means 9 in the logic verification device 1C causes the voltage value information file 10c as shown in FIG.
The instance ID or the module name for specifying the addition target of the voltage value information processing model 3 described in 1. is read, and the voltage value information processing model 3 is added to the basic model in the logic simulation basic model group 2b in accordance with this. Incorporate. Further, the voltage value information processing model adding means 9
Reads out an instance ID or a module name for specifying an addition target of the voltage value information processing model 3A described in the voltage value information file 10c, and follows the basic model in the basic model group 2b for logic simulation. And voltage value information processing model 3 in the path connecting them
Incorporate A.

Next, the logic verification execution means 5 reads from the test bench 4 the test pattern (the input signal sequence in which a specific value is set for logic verification) and the expected output value for the logic model that processed this test pattern, The test patterns are sequentially supplied to the netlist 22. This starts the logic verification operation. In the netlist 22, the test patterns are supplied to the logic models in the logic simulation model group 22a, and the results processed according to the test patterns are sequentially propagated to the next-stage element whose connection relationship is defined by the logic circuit connection information. . At this time, the voltage value information processing model 3A incorporated in the basic models forming the logical model and the path connecting them is the voltage value information file 1
The abnormal voltage value to be set to itself is read from 0c and propagated to the next stage element. Next-stage element is voltage value information processing model 3
If it is A, the abnormal voltage value is propagated as it is. On the other hand, when the next-stage element is the voltage value information processing model 3, the abnormal voltage value from the voltage value information processing model 3A is read out and the process related to the voltage value is performed.

More specifically, the abnormal voltage value read into the voltage value information processing model 3 is the voltage value information recognition unit 3
Input to a. The voltage value information recognition unit 3a decodes the abnormal voltage value to restore the original voltage value, and outputs it to the voltage value information determination unit 3b. The voltage value information determination unit 3b reads out the specified voltage value information to be set for itself from the voltage value information file 10c, and obtains its own allowable voltage value from the reference voltage value information and the allowable voltage value information set therein. after this,
The voltage value information determination unit 3b determines the magnitude relationship between the restored abnormal voltage value and the allowable voltage value by performing arithmetic comparison, and determines whether or not the voltage value information should be propagated to the next-stage element. To judge. At this time, since the abnormal voltage value becomes larger than the allowable voltage value, the voltage value information adding unit 3d generates warning message information indicating that the next-stage element has been physically destroyed due to exceeding the withstand voltage and logical verification is performed. Output to the execution means 5. The logic verification executing means 5 sends the warning message information to the output unit 6. The output unit 6 converts the warning message information into a format that can be displayed on the display unit 7 or a format corresponding to the verification result file 8c and outputs the warning message information. This allows the designer to know by logic verification that the next-stage element has been destroyed due to the occurrence of the abnormal voltage value.

At this time, at the same time, the reporting section 3c controls the voltage value information adding section 3d so as to generate information indicating that the input voltage value from another element cannot be accepted.
As a result, the voltage value information adding unit 3d generates information indicating that the input voltage value cannot be received from another element and propagates it to the next-stage element.

Further, to the logic verification executing means 5, the voltage value information which is the processing result by the voltage value information processing model 3 and the processing result of the logical model for the test pattern supplied to the netlist 22 are sequentially input. As a result, the logic verification executing means 5 compares the input processing result with the expected output value and dynamically verifies whether the netlist 22 expanded on the memory operates as expected.
This operation is similar to that of the first embodiment.

This logic verification operation is performed by the logic verification execution means 5.
Is repeated until all the test patterns have been input to the netlist 22. Finally, when all the test patterns have been input, the logic verification execution means 5 collectively outputs the verification results including the voltage value information to the output unit 6. The output unit 6 converts the input verification result data into an appropriate format and outputs it to the verification result file 8c and the display means 7.

As described above, according to the fourth embodiment, voltage value information other than the voltage value generated only in the circuit, for example, generated outside the semiconductor chip finally commercialized after finishing the design process. Voltage information processing model 3A that propagates voltage value information assuming abnormal voltage due to static electricity
Since it is provided, it is possible to perform an impact degree simulation when an abnormal voltage occurs (simulate the range of elements that are affected by the abnormal voltage occurrence in the circuit (elements that are physically destroyed due to exceeding the breakdown voltage)). it can.

Although the voltage value information processing model 3A is applied to the configuration of the first embodiment in the fourth embodiment, the same effect can be obtained by applying it to the second and third embodiments. Play.

Embodiment 5. 11 is a diagram showing the configuration of a logic verification device according to a fifth embodiment of the present invention. In the figure, 1D is a logic verification device according to the fifth embodiment, which shows a logic verification result using voltage value information extracted from logic circuit diagram data and a logic verification result using voltage value information extracted from layout pattern data. Match verification of.
Reference numeral 8d is a verification result file (verification result data) of the logic verification device according to the fifth embodiment, which is configured to include the above-mentioned matching verification result. Reference numeral 23 is a voltage value information reconstructing means (coincidence verifying means), which decodes the verification result file and extracts specific information in the order of occurrence time to constitute information to be compared. Two
Reference numeral 4 is an inter-device information comparing means (coincidence verifying means), which extracts the voltage value information from the logic circuit diagram data and performs the logic verification, and the voltage verification information from the layout pattern data and the logic verification. Voltage value information reconstructing means 23 based on the verification result file with the logic verification device 1B.
Performs comparison verification by comparing the comparison target information respectively configured. The same components as those in FIGS. 1, 5 and 7 are designated by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. FIG. 12 is a flow chart showing the operation of the logic verification device according to the fifth embodiment, and the logic verification according to the fifth embodiment will be described with reference to this flow chart. First, the logic verification device 1D extracts the voltage value information from the logic circuit diagram data and performs the logic verification, the verification result file 8 or the verification result file 8a of the logic verification device 1 or the logic verification device 1A, and the voltage value from the layout pattern data. Logic verification device 1B for extracting information and performing logic verification
Reading the verification result file 8b (step ST1
c).

Next, the voltage value information reconstructing means 23 in the logic verification device 1D decodes the contents of the verification result file 8 or the verification result file 8a and the verification result file 8b, respectively, and extracts specific information. Then, the comparison information for matching verification is formed by arranging the information in the order of the information generation time for each subsequent element (step ST2c). More specifically, as a specific information, a warning message regarding voltage value information, for example, "Warning !! The next-stage element BBB was destroyed by the abnormal voltage value CCC (V) at time AAA. The allowable voltage of the next-stage element BBB. The value is DDD (V). Warning number EEE-warning count FFF (cumulative number of warnings) "is extracted.

After that, the voltage value information reconstructing means 23
The warning messages regarding the voltage value information are arranged in the order of the abnormal voltage generation time for each next-stage element, and the element breakdown time generated in the next-stage element BBB (allowable voltage value DDD (V)) is A
AA0 (abnormal voltage is CCC0 (V)), AAA1 (abnormal voltage is CCC1 (V)), AAA2 (abnormal voltage is CCC)
2 (V), ..., AAAAn (abnormal voltage is CCCn
(V)) ”.

The comparison target information composed of each verification result file by the voltage value information reconstructing means 23 is output to the inter-device information comparing means 24, respectively. The device-to-device information comparison means 24 compares these information (in the above example, the warning messages regarding the voltage value information are compared with each other, and the different points (allowable voltage value, abnormal voltage value occurrence time, abnormal voltage value) for each next-stage element are compared. ) Is determined (step ST3c) The processing from step ST1c to step ST3c corresponds to the match verification step.

The match verification result by the inter-device information comparing means 24 is sent to the output unit 6. As a result, the output unit 6
Converts the match verification result into an appropriate format and outputs it to the verification result file 8d or the display means 7 (step ST4).
c).

As described above, according to the fifth embodiment, the logic verification result using the voltage value information extracted from the logic circuit diagram data and the logic verification result using the voltage value information extracted from the layout pattern data are obtained. Since the configuration for performing the coincidence verification is provided, it is possible to perform the dynamic coincidence verification between the logic circuit diagram data and the layout pattern data from the result of the logic verification.

Sixth Embodiment FIG. 13 is a diagram showing the configuration of a logic verification device according to a sixth embodiment of the present invention.
(A) shows the structure which displays a verification result on a logic circuit diagram, (b) has shown the structure which displays a verification result on a layout pattern. In the figure, 1E and 1F are logic verification devices according to the sixth embodiment, and have a function of displaying the logic verification results of the logic verification device shown in the above-described embodiments by reflecting them on a logic circuit diagram and a layout pattern, respectively. . Reference numeral 25 is a related logic circuit diagram data extraction means (specific information display means) for extracting logic circuit diagram data related to specific information in the verification result file. Reference numeral 26 is related logic circuit diagram data, which is logic circuit diagram data related to specific information in the verification result file extracted by the related logic circuit diagram data extraction means 25. The related logic circuit diagram data 26 is obtained by extracting only the data relating to the specific information from the logic circuit diagram data 14, or the data for distinguishing the data related to the information from the data not related (for example, the specific information). (Data necessary for highlighting only the logic circuit diagram related to)).

Reference numerals 27a and 27b denote display control units (specific information display means) for converting the information extracted by the related logic circuit diagram data extraction means 25 and the related layout pattern data extraction means 28 into a format displayable by the display means 7. . Reference numeral 28 is a related layout pattern data extraction means (specific information display means) for extracting layout pattern data related to specific information in the verification result file. Reference numeral 29 is related layout pattern data, which is layout pattern data related to specific information in the verification result file extracted by the related layout pattern data extraction means 28. The related layout pattern data 29 is obtained by extracting only the data related to the specific information from the layout pattern data 17, or the data for distinguishing the data related to the information from the unrelated data (for example, related to the specific information). Data required to highlight only the layout pattern to be displayed).
In addition, the same components as those in FIGS. 1, 5, 7, 9, and 11 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. The logic verification device 1E (or the logic verification device 1F) is the logic verification device 1, 1A, 1B, 1C, 1 according to the first to fifth embodiments.
Any one of the D verification result files 8, 8a, 8b, 8c, and 8d (hereinafter, simply referred to as a verification result file) is read together with the logic circuit diagram data 14 (or the layout pattern data 17).

The related logic circuit diagram data extraction means 25 in the logic verification device 1E (or the related layout pattern data extraction means 28 in the logic verification device 1F) extracts the specific information described in the verification result file. Related logic circuit diagram data 26 which is logic circuit diagram data related to
(Or, the related layout pattern data 29, which is the layout pattern data related to this) is converted into the logic circuit diagram data 14 (or the layout pattern data 1).
Extract from 7). Specifically, the related logic circuit diagram data extraction means 25 (or the related layout pattern data extraction means 28 in the logic verification device 1F) issues a warning message regarding the voltage value information described in the verification result file as the specific information, for example. And the logic circuit diagram data (or layout pattern data) related to the next-stage element BBB specified by the warning message is extracted from the logic circuit diagram data 14 (or layout pattern data 17).

At this time, the related logic circuit diagram data extraction means 25 (or the related layout pattern data extraction means 28 in the logic verification device 1F) is connected to the related logic circuit diagram data 26 (or the related layout pattern data 29).
As data for distinguishing logic circuit diagram data (or layout pattern data related to the next-stage element BBB) from logic circuit diagram data (or layout pattern data) not related to the next-stage element BBB Is also extracted from the logic circuit diagram data 14 (or layout pattern data 17). As the data for distinguishing the above two data, for example, the next-stage element B
The logic circuit diagram data (or layout pattern data) is associated with the range of about 10 stages before and after BB. In addition, the range of the data for this distinction may be set appropriately by the designer in the logic verification devices 1E and 1F.

Thereafter, the display control unit 27a (or the display control unit 27b), as the logic circuit diagram data 14 and the related logic circuit diagram data 26, the logic circuit diagram data relating to the next-stage element BBB and the logic not relating thereto. Data for distinguishing from the circuit diagram data (or, as the layout pattern data 17 and the related layout pattern data 29, data for distinguishing between layout pattern data related to the next-stage element BBB and layout pattern data not related thereto) The data is read from the related logic circuit diagram data extraction means 25 (or the related layout pattern data extraction means 28) and converted into data in a format displayable by the display means 7. This gives the above data
It is displayed on the display means 7 and can be viewed by the designer as appropriate.

As described above, according to the sixth embodiment, the specific information described in the verification result files 8, 8a, 8b, 8c, 8d of the logic verification devices 1, 1A, 1B, 1C, 1D is used. Since the related portion is displayed by being reflected in the logic circuit diagram data 14 (or the layout pattern data 17), a specific phenomenon regarding the voltage value information (for example, data regarding a warning message regarding the voltage value information is extracted as the specific information). In this case, a phenomenon due to an abnormal voltage value (a phenomenon in which an element is destroyed due to the application of a voltage value equal to or higher than the allowable voltage value) can be visually observed through the display means 7, and therefore the analysis is easily performed. be able to.

[0091]

As described above, according to the present invention, the logic model simulating the logic operation of the logic element forming the logic circuit to be subjected to logic verification and the withstand voltage characteristic of the electric element forming the logic element are defined. The voltage value information file that stores the voltage value information and the voltage value information that is embedded in the logic model and is input from the outside, reads the voltage value information that should be set for itself from the voltage value information file and Whether the voltage value specified by each of the information and the voltage value information set to the self is recognized and compared, and whether the input voltage value from the outside can be accepted by the electric element corresponding to the self based on the comparison result A voltage value information processing model for determining whether
Based on the expected value and the connection information of the logic element described in the netlist of the logic circuit, the logic verification of the logic circuit using the logic model is performed, and the voltage value information between each voltage value information processing model Since the verification between different voltage connection parts in the logic circuit is performed based on the determination result obtained by propagating, the accurate verification of the different voltage connection parts in the circuit can be performed while performing the logic verification of the logic circuit without performing the circuit simulation. The effect is that it can be verified. As a result, it is possible to verify the different voltage connection portion of the large-scale design at high speed and in the upstream process (logic design, logic verification) of the design.

According to the present invention, the logic model and the voltage value information processing model are respectively inputted, and the voltage value information processing model adding means for incorporating the voltage value information processing model into the logic model is provided. There is an effect that it is possible to accurately verify the different voltage connection portion while using the netlist.

According to the present invention, the voltage value information, the logic element and the connection information thereof are extracted from the logic circuit diagram data in which the voltage value information is preset, and the voltage value information file and the voltage for generating the net list of the logic circuit are generated. Since the value information file / netlist generating means is provided, it is possible to perform forward annotation of the voltage value information from the logic circuit diagram data, and it is possible to accurately verify the different voltage connection portion.

According to the present invention, the voltage value information file generating means for generating the voltage value information file by extracting the voltage value information from the layout pattern data in which the voltage value information is preset, and the layout pattern data and the configuration are 1 1 to
Since it is provided with a netlist generating unit that extracts a logic element and its connection information from the logic circuit diagram data corresponding to, and generates a netlist of the logic circuit, it is possible to perform back annotation from the layout pattern data of the voltage value information. Therefore, there is an effect that it is possible to accurately verify the different voltage connection portion.

According to the present invention, the voltage value information file stores abnormal voltage value information arbitrarily set in addition to the voltage value information, and propagates the abnormal voltage value information in the logic circuit to be logically verified. Since it has an abnormal voltage information propagation model,
There is an effect that it is possible to perform a degree of influence simulation when an abnormal voltage occurs (simulate the range of elements (elements that are physically destroyed due to exceeding the breakdown voltage) that are affected by the occurrence of abnormal voltage in the circuit). .

According to the present invention, the verification result data by the logic verification using the information extracted from the preset layout pattern data for the voltage value information and the voltage value information in which the layout pattern data have a one-to-one correspondence with the configuration. Since a match verification means for comparing the verification result data by the logic verification using the information extracted from the preset logic circuit diagram data with each other to perform the match verification is provided, the logic circuit diagram data and the layout pattern data are obtained from the result of the logic verification. There is an effect that a dynamic match verification with can be performed.

According to the present invention, the specific information included in the verification result data is extracted and provided with the specific information display means for displaying it on the logic circuit diagram and / or the layout pattern. Since it can be visually observed, there is an effect that the analysis can be easily performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a logic verification device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a voltage value information processing model in FIG.

FIG. 3 is a diagram showing an example of a voltage value information file in FIG.

FIG. 4 is a flowchart showing the operation of the logic verification device according to the first embodiment.

FIG. 5 is a diagram showing a configuration of a logic verification device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing the operation of the logic verification device according to the second embodiment.

FIG. 7 is a diagram showing a configuration of a logic verification device according to a third embodiment of the present invention.

FIG. 8 is a flowchart showing the operation of the logic verification device according to the third embodiment.

FIG. 9 is a diagram showing a configuration of a logic verification device according to a fourth embodiment of the present invention.

10 is a diagram showing an example of a voltage value information file in FIG.

FIG. 11 is a diagram showing a configuration of a logic verification device according to a fifth embodiment of the present invention.

FIG. 12 is a flowchart showing the operation of the logic verification device according to the fifth embodiment.

FIG. 13 is a diagram showing a configuration of a logic verification device according to a sixth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a conventional logic verification device.

15 is a flowchart showing a logic verification operation by the logic verification device in FIG.

FIG. 16 is a diagram illustrating a problem of a conventional logic verification device.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D, 1E, 1F Logic verification device, 2 Netlist, 2a Logic simulation model group, 2b Logic simulation basic model group, 3,3A Voltage value information processing model, 3a Voltage value information recognition Section, 3b voltage value information judging section, 3c reporting section, 3d
Voltage value information addition section, 4 test bench, 5 logic verification execution means, 6 output section, 7 display means, 8, 8a, 8
b, 8c, 8d verification result file (verification result data), 9 voltage value information processing model adding means, 10, 10
a, 10b, 10c voltage value information file, 11, 1
6,21,22 Netlist, 11a, 16a, 21
a, 22a logical simulation model group, 11
b, 16b, 21b, 22b basic model group for logic simulation, 12a, 12b voltage value information, 13 specified voltage value information, 14 logic circuit diagram data, 15 voltage value information / netlist generating means (voltage value information file / netlist Generating means), 17 layout pattern data, 18 logic circuit diagram data, 19 voltage value information file generating means, 20 net list generating means, 23 voltage value information reconstructing means (match verification means), 24 inter-device information comparing means (match) Verification means), 25 related logic circuit diagram data extraction means (specific information display means), 26 related logic circuit diagram data, 27a, 27b display control section (specific information display means), 28 related layout pattern data extraction means (specific information display) Means), 29 related layout pattern data.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuuji Mikawa             3-1-1 Chuo 3-chome, Itami City, Hyogo Prefecture             Machine System LSI Design Co., Ltd.             Inside the company (72) Inventor Hiroyuki Hamano             3-1-1 Chuo 3-chome, Itami City, Hyogo Prefecture             Machine System LSI Design Co., Ltd.             Inside the company F-term (reference) 2G132 AA01 AB01 AC11 AD06 AE23                       AL00 AL11                 5B046 AA08 BA02 GA01 JA05                 5F064 HH06 HH09

Claims (16)

[Claims] 1. A logic model for simulating a logic operation of a logic element that constitutes a logic circuit to be subjected to logic verification, and voltage value information that stores voltage value information that defines withstand voltage characteristics of an electrical element that constitutes the logic element. When the voltage value information input from the file and the above-mentioned logic model is input from the outside, the voltage value information to be set for itself is read from the voltage value information file, and the voltage value information from the outside and the voltage set for itself are read. Voltage value information processing that recognizes the voltage value specified by each value information and performs comparison, and determines based on the comparison result whether the input voltage value from the outside can be accepted by the corresponding electric element A model and a test pattern given to the logic circuit to be logic-verified,
Based on the expected value and the connection information of the logic element described in the netlist of the logic circuit, the logic verification of the logic circuit using the logic model is performed, and each of the voltage value information processing models Logic verification executing means for verifying between different voltage connection parts in the logic circuit from a determination result obtained by propagating the voltage value information of the logic verification device. 2. A voltage value information processing model adding means for inputting a logic value model and a voltage value information processing model, respectively, and incorporating the voltage value information processing model into the logic model. Logic verification device. 3. A voltage value information file for extracting voltage value information, logic elements and their connection information from logic circuit diagram data in which voltage value information is preset, and generating a voltage value information file and a logic circuit netlist. The logic verification apparatus according to claim 1 or 2, further comprising a netlist generation unit. 4. A voltage value information file generating means for extracting voltage value information from layout pattern data in which voltage value information is preset and generating a voltage value information file, and the layout pattern data and the configuration have a one-to-one correspondence. The logic verification according to claim 1 or 2, further comprising: a netlist generating unit that extracts a logic element and its connection information from corresponding logic circuit diagram data to generate a netlist of the logic circuit. apparatus. 5. The voltage value information file stores abnormal voltage value information arbitrarily set in addition to the voltage value information, and causes the abnormal voltage value information to propagate in the logic circuit of the logic verification target. The logic verification device according to claim 1, further comprising a propagation model. 6. The verification result data by the logic verifying device according to claim 4, wherein the voltage value information is extracted from preset layout pattern data, and the layout pattern data has a one-to-one correspondence with the logic. A logic verification device comprising a match verification means for comparing the verification result data by the logic verification device according to claim 3, which uses information extracted from the circuit diagram data. 7. The specific information display means for extracting the specific information contained in the verification result data and displaying it on the logic circuit diagram and / or the layout pattern. The logic verification device according to any one of 1. 8. A logic model for simulating the logical operation of the logic element by setting voltage value information defining a withstand voltage characteristic of an electrical element forming a logic element in a logic circuit to be logic-verified as a voltage value information file. When the voltage value information is input from the outside, the voltage value information to be set to the self is read from the voltage value information file, and the voltage specified by each of the external voltage value information and the self-set voltage value information is specified. A voltage value information processing function incorporating a voltage value information processing model for recognizing a value, performing a comparison, and determining whether or not an external input voltage value can be accepted by an electric element corresponding to the self based on the comparison result An additional step, a test pattern given to the logic circuit to be logic-verified,
Based on the expected value and the connection information of the logic element described in the netlist of the logic circuit, the logic verification of the logic circuit using the logic model is performed, and each of the voltage value information processing models Logic verification step for verifying between different voltage connection parts in the logic circuit based on the determination result obtained by propagating the voltage value information of 1. 9. A voltage value information file for generating voltage value information files and logic circuit netlists by extracting voltage value information, logic elements and their connection information from logic circuit diagram data in which voltage value information is preset. 9. The logic verification method according to claim 8, further comprising a netlist generation step. 10. A voltage value information file generating step of generating voltage value information file by extracting voltage value information from layout pattern data in which voltage value information is preset, and the layout pattern data and the configuration have a one-to-one correspondence. 9. The logic verification method according to claim 8, further comprising a netlist generating step of generating a netlist of the logic circuit by extracting the logic element and its connection information from the corresponding logic circuit diagram data. 11. The verification result data according to the logic verification method according to claim 9, wherein the voltage value information is extracted from preset layout pattern data, and the layout pattern data has a one-to-one correspondence with the configuration. A logic verification method comprising a match verification step of performing verification by comparing verification result data according to the logic verification method according to claim 10, which uses information extracted from circuit diagram data. 12. A logic model for simulating the logical operation of a logic element forming a logic circuit to be subjected to logic verification, and a voltage value information file storing voltage value information defining withstand voltage characteristics of electric elements forming the logic element. , Built in the logic model, when voltage value information is input from the outside, the voltage value information to be set for itself is read from the voltage value information file, and the voltage value information from the outside and the voltage value information set for itself are read. Each of the voltage value information processing model for recognizing the voltage value specified by each of the comparison, to determine whether or not the input voltage value from the outside can be accepted by the electric element corresponding to itself based on the comparison result, A test pattern to be given to the logic circuit of the above logic verification
Based on the expected value and the connection information of the logic element described in the netlist of the logic circuit, the logic verification of the logic circuit using the logic model is performed, and each of the voltage value information processing models A logic verification program for causing a computer to function as a logic verification executing means for verifying between different voltage connection parts in the logic circuit based on the determination result obtained by propagating the voltage value information. 13. The logic verification according to claim 12, wherein a logic model and a voltage value information processing model are respectively input to cause the computer to function as voltage value information processing model adding means for incorporating the voltage value information processing model into the logic model. program. 14. A voltage value information file for generating voltage value information files and logic circuit netlists by extracting voltage value information, logic elements and their connection information from logic circuit diagram data with preset voltage value information. The logic verification program according to claim 12 or 13, which causes a computer to function as a netlist generating unit. 15. A voltage value information file generating means for generating voltage value information file by extracting voltage value information from layout pattern data in which voltage value information is preset, and the layout pattern data and the configuration have a one-to-one correspondence. 13. The computer is caused to function as a netlist generating unit that extracts a logic element and its connection information from the logic circuit diagram data to generate a netlist of the logic circuit.
Alternatively, the logic verification program according to claim 13. 16. The information extracted from layout pattern data in which voltage value information is set in advance is used.
2. The information extracted from the verification result data by the described logic verification program and the logic circuit diagram data in which the layout pattern data has a one-to-one correspondence with the layout pattern data.
A logic verification program for causing a computer to function as a match verification means for comparing the verification result data by the logic verification program described in 4, and performing a match verification.