JP3340283B2 - Hazard simulation device for logic circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hazard simulation device for a logic circuit, and more particularly to a hazard simulation device for a logic circuit capable of shortening the period of logic design and easily detecting occurrence of a hazard. .

[0002]

2. Description of the Related Art Conventionally, in logic design, in a timing design in which a time delay of a signal change is considered, an unexpected transient output is generated due to a time delay of a change of a logic variable, and an abnormal progress of a sequence occurs. In general, a logic simulation is performed in consideration of the delay of the gate element in order to investigate occurrence of the hazard (hereinafter referred to as a hazard) and propagation of the hazard. Since the occurrence of the hazard not only causes a timing malfunction, but also causes an increase in power consumption due to useless switching, it is desirable to check at an early stage of design.

FIG. 6 shows an outline of a conventional logic design apparatus. This logic design device receives a predetermined logic connection data 1 and performs a desired logic design in consideration of timing design, power consumption, and the like, and a circuit designed by the logic simulation unit 101. A layout design unit 103 for designing the layout of the circuit, a hazard analysis unit 103 for analyzing the hazard of the circuit laid out by the layout design unit 103,
An analysis result output unit 107 that outputs the analysis result of the hazard analysis unit 103 is provided.

An operator of the logic design apparatus refers to the analysis result and the like of the analysis result output unit 107 and refers to the generation and propagation of a hazard. If the reference does not satisfy the predetermined requirement, the connection information of the logical connection data 1 is corrected, the simulation is performed again by the logic simulation unit 101, and the layout design and the hazard analysis are performed. As described above, in the conventional logic design, the design is performed by trial and error correction of the logical connection data until a predetermined requirement is satisfied with reference to an analysis result or the like.

[0005]

As described above, in the conventional logic design apparatus, the design is performed by trial and error until the logical connection data is corrected until predetermined requirements are satisfied. Oops. Furthermore, there has been a problem that the time required for logic design is further increased with the recent increase in the degree of integration and scale of integrated circuits.

In the analysis of the hazard, the delay time of the gate element must reflect the value in the logic circuit including the wiring, so that it can be checked only at the final stage of the circuit design in which the layout is determined. Therefore, it must be after a very time-consuming logic simulation and layout design.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a hazard simulation device for a logic circuit capable of shortening the period of logic design and easily detecting occurrence of a hazard. To provide.

[0008]

SUMMARY OF THE INVENTION The inventor of the present invention has proposed that the analysis of the hazard must reflect the delay time of the gate element in the integrated circuit including the wiring. In other words, the fact that the check can be performed only at the final stage of the design may cause an increase in the period of the logical design. Then, by modeling the hazard without using the delay time of the gate element, it was thought that the occurrence of the hazard could be detected in the initial stage of logic design. For that purpose, it is necessary to give rules for the generation and propagation of hazards for each logic gate, and to clarify what happens to the hazards that have reached the feedback loop when there is a feedback loop such as a flip-flop .

From the above considerations, the inventor of the present invention has conducted careful studies and as a result, has completed the present invention. The feature of the present invention is to input predetermined logical connection data,
A connection information extraction unit that extracts a connection relationship of each logic gate as connection information, and a logic gate state propagation table that stores a logic gate state propagation table in which a hazard is modeled and the state propagation of each logic gate is represented by a logical value, A hazard simulation unit that simulates the occurrence and propagation of a hazard using the logic gate state propagation table for the connection relationship between the logic gates extracted by the connection information extraction unit, and a hazard simulation result of the hazard simulation unit And a hazard simulation result output unit that outputs the result.

Here, the logic gate state propagation table
In the state of each logic gate, a state of constantly "0", a state in which a transition from "1" to "0", the state settles to "0" with a hazard in the middle, stationary A state of "1", a state of transition from "0" to "1", a state of settling down to "1" with an intermediate hazard,
Preferably , the modeled logic gate state propagation table is stored .

When performing a simulation of a logic circuit having a feedback loop, the hazard simulation section sets “0” with the hazard for the state of each of the modeled logic gates in the feedback loop. Is constantly converted to a state of “0” or a transition state from “1” to “0”, and a state of being settled to “1” with the hazard is constantly changed to a state of “1” or “1”. It is preferable to simulate the generation and propagation of a hazard in the logic circuit by converting the transition state from "0" to "1".

[0012]

In the configuration of the present invention, the connection relation of each logic gate extracted by the connection information extraction unit using the logic gate state propagation table in which the state propagation of each logic gate modeling a hazard is represented by a logical value is described. The simulation of the occurrence and propagation of hazards is performed using the logic gate state propagation table. Here, in the layout design unit shown in the conventional example, the calculation could not be performed unless the layout was expanded to the transistor level. However, according to the configuration of the present invention, even before the layout was determined, the hazard analysis was performed. Since it can be performed, it is possible to easily analyze the generation and propagation of the hazard. Further, since the hazard analysis can be performed in a relatively upstream process of the logic circuit design, a more effective logic circuit can be designed, and a logic circuit with further reduced power consumption can be designed.

[0013] Further, it is possible to shorten the time required for designing a logic circuit by making an operator know which part of the hazard has occurred at the hazard simulation result output unit. You can.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a hazard simulation apparatus for a logic circuit according to an embodiment of the present invention.

First Embodiment First, in this embodiment, a hazard is modeled using multi-valued logic. Below are the seven logical values S0, T0, U0, S
1, T1, U1, and XX will be described.
The meaning of each logical value is shown below.

S0: Steady state of "0" T0: Transition state from "1" to "0" U0: State of settling down to "0" with a hazard in the middle S1: Steady state of "1" T1: Transition state from “0” to “1” U1: State settled to “1” with a hazard on the way XX: Undefined state Settled to “0” or “1” with a hazard on the way in U0, U1 Because "0"->"1"->
"0" or "1"->"0"->"1"->"0"->
It means that it vibrates before finally settling to "0" or "1" like "1".

Note that the logical values used in this embodiment are not limited to the following seven logical values. For example, different logical values may be used for the case of vibrating only once and the case of vibrating a plurality of times. In this way, by using different logic values depending on the behavior of the hazard, it is possible to know a more accurate increase in power consumption.

Table 1 shows a state propagation table for the NOT gate.

[0019]

[Table 1] Table 2 shows the state propagation for the AND gate. State propagation for other logic gates can be created from state propagation tables for NOT gates and AND gates.

[0020]

[Table 2] AND (T0, T1) becomes U0 as shown in Table 2.
This is because there is a timing at which both become "1" due to the difference between the delays of the input elements, and the output changes like "0"->"1"->"0".

Next, a description will be given of a logic circuit hazard simulation apparatus according to this embodiment. As shown in FIG. 1, a hazard simulation device for this logic circuit receives predetermined logic connection data 1 and extracts a connection relationship between logic gates as connection information, and a connection information extraction unit 3 which models a hazard to form each logic connection. The logical gate state propagation table 9 storing a logical gate state propagation table in which the state propagation of the gate is represented by a logical value and the connection relation of each logical gate extracted by the connection information extracting unit 3 are described in the logical gate state propagation. Hazard simulation unit 7 that simulates generation and propagation of hazard using Table 9
And a hazard simulation result output unit 13 that outputs a hazard simulation result of the hazard simulation unit 7.

Here, the connection information extracting unit 3 is for inputting predetermined logical connection data from the logical connection data holding unit 1 and extracting the connection relationship of each logical gate of the logical connection data as connection information. is there. Here, in this embodiment, the logical connection data may be at the logical gate level, and does not need to be at the transistor level. This eliminates the need for a layout design, thereby shortening the design period. Further, the extracted data may be stored in the connection information buffer 5. The logic gate state propagation table 9 stores a logic gate state propagation table in which a hazard is modeled and the state propagation of each logic gate is represented by a logical value. Here, the state propagation table for each logic gate is similar to the state propagation table for the NOT gate shown in Table 1 and the state propagation table for the NAND gate shown in Table 2.

The hazard simulation section 7 determines whether or not the connection relation of each of the extracted logic gates is such that a hazard occurs using a predetermined logic gate state propagation table stored in the logic gate state propagation table storage section 9. Is to be checked for each connection relationship.

The hazard simulation test pattern generation unit 11 is for generating a hazard simulation test pattern according to the present embodiment. Here, the above-described logical values S0, T0, U0, S1, T1,
An arbitrary combination of U1 and XX is generated and output to the hazard simulation unit 7.

Hazard simulation result output unit 13
Is for outputting a hazard simulation result of the hazard simulation unit 7. This output may be that used in a normal computer system such as a CRT device or a printer device. Further, by providing the output with the graphics function, the operability of the operator is improved, so that the period of logic design can be further shortened.

Next, the operation of the hazard simulation apparatus according to the present invention will be described. First, the operator selects desired logical connection data from the logical connection data holding unit 1 and inputs the data to the connection information extracting unit 3. Connection information extraction unit 3
Then, the connection relationship between the logic gates of the input logic connection data is checked, how the signal propagates, and the result is output as connection information.

Next, the hazard simulation section 7 simulates whether or not a hazard is generated with respect to the connection relationship between the logic gates based on the input connection information. In this simulation, the initial values of all the gates included in the circuit are set to XX, and S0, T0, S1, and S1 are changed according to the change in the test pattern output from the test pattern generation unit 11 for hazard simulation.
This is performed by adding any one of T1 and calculating the output based on the logic gate state propagation table given for each logic gate. If there is a gate which becomes U0 or U1 during the simulation, it means that it is a hazard occurrence part, and this hazard occurrence part is output.

Next, the result of whether or not the hazard is generated is output to a hazard simulation result output unit 13, and the operator can see the output result to grasp the portion where the hazard has occurred. Can be.

Second Embodiment Next, in this embodiment, a hazard simulation of a logic circuit having a feedback loop will be described. In a logic circuit having this feedback loop, it is necessary to clarify what happens to a hazard that has reached the feedback loop. In this embodiment, a logic circuit including a flip-flop is described as a logic circuit including a feedback loop.

FIG. 2 is a model for reducing a hazard in a flip-flop. In the operation of a general sequential circuit, generation of a hazard in the combinational circuit portion and disappearance of the hazard in the flip-flop portion are repeated. In order to realize the disappearance of the hazard by simulation, that is, in order to simulate the actual circuit to behave, a virtual element is inserted. In this embodiment, an element F for absorbing a hazard is inserted before the output Q. Table 3 shows the propagation rules of the element F. IN indicates an input to the element F, F indicates an output of the element F, and RP indicates an initial state of the element F.

[0031]

[Table 3] By inserting the element F in this manner, a hazard simulation of a logic circuit having a feedback loop can be performed.

Next, a hazard simulation apparatus for a logic circuit according to this embodiment will be described. Basically, the configuration of the first embodiment can be used, but means for inserting a virtual element into a feedback loop portion of a logic circuit having a feedback loop is required. This means is preferably provided in the hazard simulation section 7 described above.

Next, an example of a hazard simulation of a logic circuit having a feedback loop will be described. Three, three, and three frequency divider circuits are shown in FIGS. 3, 4, and 5. FIG. These figures are output to the hazard simulation result output unit 13 as a result of the hazard simulation performed by the above-described hazard simulation apparatus. Nodes in which hazards occur in the figure are indicated by thick oblique lines. In the case of FIG. 3, a hazard occurs in the output, but does not appear in the output in FIGS.

As described above, in the hazard simulation according to the present embodiment, the analysis of the hazard cannot be performed unless the layout is conventionally designed. However, according to the present embodiment, the hazard is modeled. Hazard analysis can be performed more easily.

As described above, the hazard can be easily analyzed by modeling the hazard, so that the hazard can be analyzed in a relatively upstream process of the logic circuit design. Thus, a more effective logic circuit can be designed, and a logic circuit with further reduced power consumption can be designed.

Further, by letting the operator know the portion where the hazard has occurred in the hazard simulation result output section 13, the design period of the logic circuit can be shortened.

[0037]

As described above, according to the hazard simulation apparatus for a logic circuit according to the present invention, the hazard can be easily analyzed by modeling the hazard. Further, since the hazard analysis can be performed in a relatively upstream process of the logic circuit design, a more effective logic circuit can be designed, and a logic circuit with further reduced power consumption can be designed.

Further, by letting the operator know the portion where the hazard has occurred in the hazard simulation result output section, the period for designing the logic circuit can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hazard simulation apparatus according to the present invention.

FIG. 2 is a model for eliminating a hazard in a flip-flop. An element F for absorbing a hazard is inserted before the output Q.

FIG. 3 is an example of a divide-by-3 circuit in which a hazard occurs in an output.

FIG. 4 is an example of a divide-by-3 circuit in which no hazard appears in the output.

FIG. 5 is an example of a divide-by-3 circuit in which a hazard occurs in an output.

FIG. 6 is a block diagram showing an outline of a conventional simulation apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Logical connection data 3 Connection information extraction part 5 Connection information part buffer 7 Hazard simulation 9 Logic gate state propagation table 11 Hazard simulation test pattern generation part 13 Hazard simulation result output part 15 Element 101 Logic simulation part 103 Layout design part 105 Hazard analysis Unit 107 Analysis result output unit

Continuation of front page (56) References JP-A-5-35816 (JP, A) Hirabayashi, K .; , Hazard simulation of sequential circuits, Journal of Electronic Testing: Theory and Applications, April 1996, Vol. 8, No. 2, p. 215-217 Yasushi and 2 others, A method of hazard detection by quinary logic simulation based on TRF delay model, IEICE Transactions A, IEICE, 1991, Vol. 74, no. 2, p. 237-246 Nishika Ishiura and 2 others, Time symbol simulation for accurate timing verification of logic circuits, Transactions of Information Processing Society of Japan, Information Processing Society of Japan, 1990, Vol. 31, No. 12, p. 1832-1839 Kanji Hirabayashi, Delayed fault simulation of sequential circuits, IEICE technical report, IEICE, December 10, 1992, Vol. 92, no. 364 (ICD92 115-125), p. 67-73 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 668 JICST file (JOIS)

Claims (3)

(57) [Claims] 1. A connection information extraction unit for inputting predetermined logical connection data and extracting connection relation of each logic gate as connection information, and a logic which models a hazard and expresses a state propagation of each logic gate by a logical value. A logic gate state propagation table that stores a gate state propagation table, and for the connection relationship between the respective logic gates extracted by the connection information extraction unit, a simulation of the generation and propagation of hazards is performed using the logic gate state propagation table. A hazard simulation device for a logic circuit, comprising: a hazard simulation unit for performing; and a hazard simulation result output unit for outputting a hazard simulation result of the hazard simulation unit. The method according to claim 2, wherein said logic gate state propagation table,
The state of each logic gate is steadily “0” state, the state that transitions from “1” to “0”, the state that settles to “0” with hazards on the way, The modeled logic gate state propagation table is stored in the state of “1”, the state of transition from “0” to “1”, and the state of settling down to “1” with an intermediate hazard.
Hazard simulation apparatus of a logic circuit according to claim 1, wherein. 3. When simulating a logic circuit having a feedback loop, the hazard simulation section sets “0” with the hazard for the state of each of the modeled logic gates in the feedback loop. Is constantly converted to a state of “0” or a transition state from “1” to “0”, and the state of being settled to “1” with the hazard is constantly changed to a state of “1” or “ 3. The hazard simulation apparatus for a logic circuit according to claim 2, wherein the transition from "0" to a transition state of "1" is performed to simulate generation and propagation of the hazard in the logic circuit.