JP2002083007A - Device and method for verifying logic of event-driven simulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm the presence of a contention by confirming whether or not an execution result depends upon the execution order of a module. SOLUTION: A 2nd module 12 connected to a 1st module 14 is extracted and a 3rd module 13 connected to the 1st module 14 is extracted. The 1st delay state of the signal line between the 1st module 14 and 2nd module 12 is defined and the 2nd delay state of the signal line between the 1st module 14 and 3rd module 13 is defined. The 1st logic verification result of the 1st module 14 based upon the definition of the 1st delay state is outputted and the 2nd logic verification result of the 1st module 14 based upon the definition of the 2nd delay state is outputted. The 1st and 2nd logic verification results are compared with each other to judge whether or not the 1st and 2nd logic results are different. Delay is virtually and positively defined and then it is surely judged whether or not the logical value showing the execution result of the execution module has a difference depending upon the execution order. Eventually, event-driven simulation can be made fast at the stage of a hardware description language in which a circuit of register transfer level is described.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device and a verification method for an event-driven simulator, and more particularly, to shortening an event propagation time by grouping a plurality of elements of a circuit designed in a hardware description language. The present invention relates to a logic verification device for an event-driven simulator that can confirm a conflict between a plurality of events that occur in the event, and a verification method thereof.

[0002]

2. Description of the Related Art Register transfer level circuits are designed in a hardware description language. The circuit so described is simulated as to whether it has an event conflict. A plurality of elements of such a circuit to be simulated are grouped based on a predetermined criterion and assigned to each same group. Such an assignment reduces the event propagation time.

FIG. 4 illustrates such an assignment.
The elements A and B of the LSI to be simulated are I-LS
Grouped into an I group, and the elements C and D of the LSI
Are grouped into a J-LSI group, the elements E and F of the LSI are grouped into a K-LSI group, and the elements D and H of the LSI are grouped into an L-LSI group. The assigning unit assigns the I-LSI and J-LSI to the first
Assigned to processor, K-LSI, L-LSI
Assign to processor. In such an assignment, I-
Since the case where the event is propagated from the LSI to the L-LSI is not taken into account, if there is a conflict between the event propagated from the K-LSI and the event propagated from the L-LSI, correct operation may not be obtained. Conceivable. It is considered that the propagation time of events becomes uniform when grouping is performed. In such a case, even if the delays of the elements A, B, E, and F are different, the events input to the element G of the L-LSI At the same time, the logic verification cannot be performed in the order of the event input. Therefore, if the event propagation time is shortened by the assignment as described above, the K-LSI and the L
-Unable to confirm two conflicts of LSI.

It is required that it is possible to confirm whether or not the execution result depends on the execution order of the modules and to confirm the existence of a conflict.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic verification device for an event-driven simulator capable of confirming whether the execution result depends on the execution order of modules and confirming the existence of a conflict. It is to provide a verification method.

[0006]

Means for solving the problem are described as follows. The technical items appearing in the expression are appended with numbers, symbols, and the like in parentheses (). The numbers, symbols, and the like refer to technical items that constitute at least one embodiment or a plurality of embodiments of the embodiments or embodiments of the present invention, particularly, the embodiments or the embodiments. Corresponds to the reference numbers, reference symbols, and the like assigned to the technical matters expressed in the drawings corresponding to. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.

According to the logic verification device for an event driven simulator according to the present invention, a first delay state of a first signal line on which a first output of a first module (12) propagates to a third module (14), and a second module ( 13) a virtual delay unit (2) for defining a relative delay relationship of a second delay state of a second signal line on which a second output propagates to a third module (14), and corresponds to the first delay state. Third module (1
A logic verification result comparison unit (11) for comparing the logic verification result of (4) with the logic verification result of the third module (14) based on the second delay state. By actively defining the delay virtually, it is possible to reliably determine whether or not there is a difference depending on the execution order in the logical value indicating the execution result of the execution module (14). As a result, the event-driven simulation can be sped up at the stage of a hardware description language that describes a register transfer level circuit.

The definition of the relative delay relationship can be variously defined as follows. A relative delay relationship is defined as a relationship where the first output enters the third module faster than the second output, in which case only the first signal line is delayed and the second signal line is not delayed. Is done. Alternatively, the relative delay relation is defined as a first relation in which the first output is input to the third module (14) faster than the second output, and a third module (14) in which the first output is lower than the second output. And the second relationship to be input to By reversing the delay relationship, the existence or nonexistence of the above becomes clearer.

The first relation is defined as inserting a delay element into the first delay line and not inserting a delay element into the second delay line. The second relation is defined as inserting a delay element into the second delay line and inserting the delay element into the first delay line. It can be defined that no delay element is inserted into the delay line. Further, the definition of the relative delay relationship may be defined as inserting a delay element into the first delay line. It is also effective to compare a logical value with a delay and a logical value without a delay, and it is effective to perform a logical value comparison based on one or many of various delay relationships. is there.

By providing the extraction unit for extracting the first signal line and the second signal line, the simulation can be completed quickly and automatically for all the circuits.

According to the logic verification method for an event-driven simulator according to the present invention, the second module (12) connected to the first module (14) is extracted, and the third module (13) connected to the first module (14). Extracting, defining a first delay state of a signal line between the first module (14) and the second module (12), the first module (14) and the third module (13).
Defining a second delay state of the signal line between the first and second modules, outputting a first logic verification result of the first module based on the definition of the first delay state, and defining a second logic state based on the definition of the second delay state. Outputting the second logic verification result of the one module (14); comparing the first logic verification result with the second logic verification result to determine whether there is a difference between the first logic verification result and the second logic verification result; It consists of things.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Corresponding to the drawings, in the embodiment of the logic verification device for an event driven simulator according to the present invention, a circuit connection information extraction unit is provided together with a virtual delay element insertion unit. The circuit connection information extraction unit 1 is connected to a virtual delay element insertion unit 2, as shown in FIG. The circuit connection information 3 is input to the circuit connection information extraction unit 1. The circuit connection information extraction unit 1 extracts that a signal input to the execution module described in the circuit connection information 3 is output from two or more other modules, and a signal through which the two signals pass. The line information 4 is output.

The signal line information 4 is input to the virtual delay element insertion unit 2. The virtual delay element insertion unit 2 inserts a virtual delay element for respectively delaying such two signals based on the signal line information 4. The virtual delay element insertion unit 2 outputs the delay circuit connection information 5 after the virtual delay element has been inserted. Virtual delay element insertion unit 2
Are connected to the logic verification unit 6. Delay circuit connection information 5 output from virtual delay element insertion unit 2
Is input to the logic verification unit 6.

The logic verification unit 6 receives the delay circuit connection information 5 and the logic verification test vector 7. The logic verification unit 6 outputs the first logic verification result 8 based on the delay circuit connection information 5 by using the test vector 7 for logic verification. The second logic verification result 9 based on the circuit connection information 3 before the virtual delay element is inserted is separately obtained. The logic verification unit 6 is connected to the logic verification result comparison unit 11. The first logic verification result 8 is output from the logic verification unit 6 and input to the logic verification result comparison unit 11. The logic verification result comparison unit 11 compares the first logic verification result 8 with the second logic verification result 9.

FIG. 2 illustrates that a signal input to the execution module described in the circuit connection information 3 is output from two or more other modules. The circuit connection information extraction unit 1 focuses on any one circuit element based on the configuration of the plurality of execution modules in the circuit connection information 3 and the connection information between the plurality of modules, and inputs the input terminal of the circuit element. , Two different execution modules 12 and 13 which are reached by tracing the signal connected to the signal generation source and the net thereof.

Two different execution modules 12, 13
Is a signal generation source, and it is extracted that two signals output from the signal generation source are input to another execution module 14. In such a case, the virtual delay element insertion unit 2 provides the first virtual delay element 15 to each of a signal line connecting the execution module 12 and the execution module 14 and a signal line connecting the execution module 13 and the execution module 14. And the second virtual delay element 16 are inserted. After such insertion, the virtual delay element insertion unit 2 generates and outputs the delay circuit connection information 5 as described above.

The first virtual delay element 1 inserted as described above
5 and the second virtual delay element 16 each have two delay states A and B. In the delay state A, the delay constant is set so that the delay of the first virtual delay element 15 is larger than the delay of the second virtual delay element 16. In the delay state B, the delay of the first virtual delay element 15
The delay constant is set to be smaller than the delay of No. 6.

The logic verification unit 6 performs logic verification by selecting one of the delay states A and B defined in the first virtual delay element 15 and the second virtual delay element 16. By performing logic verification on each of the two delay states, logic verification can be performed on a state in which an event (change) of a signal output from each of the execution module 12 and the execution module 13 is reversed.

The logic verification result comparison unit 11 includes a second logic verification result 9 and the first logic verification result 6 obtained by the logic verification unit 6.
The comparison with the logic verification result 8 is performed to compare the logic value before and after inserting the virtual delay element. By performing such a logic verification result comparison, the execution order of the execution modules of the event-driven simulator, or
The difference in the logic verification result based on the difference in the execution order of the execution modules due to the optimization of the simulator can be confirmed, and the presence or absence of the consistency of the result can be determined.

Registers using hardware description language
In the transfer-level design, it is possible to verify that the description has a logical value that changes depending on the execution order of the execution modules without creating a gate-level description. The method of verifying the logical value difference at the register transfer level reduces the time by 10 times compared to the method of detecting the logical value difference at the gate level. The reason is that the execution order of the independent execution modules is not always constant and differs depending on the configuration of the simulator and the execution module, and the logic verification means processes the execution modules in the order determined to be optimal at the time of execution of the verification, At this time, if the execution order of the modules to be executed depends, the simulation result differs depending on the execution order.

[0021] It is possible to simulate the insertion of a virtual delay into a signal line connecting a plurality of execution modules in an LSI to change the order of event propagation, and to determine whether or not the execution order of each module is dependent. Confirmation can be made quickly and reliably.

FIG. 3 shows another embodiment of the logic verification device of the event driven simulator according to the present invention. The virtual delay element insertion unit 2 gives a definition for delaying the signal line propagation time instead of inserting the virtual delay element. In this case, when the logic verification unit 6 performs logic verification on the signal line obtained by the virtual delay element insertion unit 2, a signal propagation delay is given, and the signal obtained by the virtual delay element insertion unit 2 is given. For the line,
It defines and outputs the delay definition information 5 '. The logic verification unit 6 performs logic value verification using the circuit connection information 3, the test vector 7, and the delay definition information 5 ', and outputs a logic verification result 8'. The logic verification result comparison unit 11 compares the logic verification result 9 not using the delay definition information 5 ′ with the logic verification result 8 ′ using the delay definition information 5 ′,
If different parts are found by the comparison, it is determined that there is a dependency on the execution order of the execution modules.

[0023]

The logic verification device and the verification method of the event-driven simulator according to the present invention can positively delay the logic inconsistency and reliably find the logic inconsistency. It can be determined at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a logic verification device for an event-driven simulator according to the present invention.

FIG. 2 is a circuit block diagram showing a module structure.

FIG. 3 is a circuit block diagram showing another embodiment of the logic verification device of the event-driven simulator according to the present invention.

FIG. 4 is a circuit diagram showing a known grouping.

[Explanation of symbols]

2 Virtual delay unit 11 Logic verification result comparison unit 12 First module (or second module) 13 Second module (or third module) 14 Third module (or first module, execution module)

Claims (7)

[Claims] 1. A first delay state of a first signal line on which a first output of a first module propagates to a third module, and a first delay state of a second signal line on which a second output of a second module propagates to the third module. A virtual delay unit that defines a relative delay relationship with a second delay state; a logic verification result of the third module corresponding to the first delay state; and a logic of the third module based on the second delay state A logic verification device for an event-driven simulator including a logic verification result comparison unit that compares the verification result with a verification result. 2. The logic verification apparatus for an event-driven simulator according to claim 1, wherein the definition of the relative delay relation includes a relation in which the first output is input to the third module faster than the second output. 3. The definition of the relative delay relationship includes: a first relationship in which the first output is input to the third module faster than the second output; and a first output is slower than the second output. The logic verification device for an event-driven simulator according to claim 1, further comprising: a second relationship input to the third module. 4. The first relation is that a delay element is inserted into the first delay line and no delay element is inserted into the second delay line, and the second relation is that a delay element is inserted into the second delay line. 4. The logic verification device for an event-driven simulator according to claim 3, wherein an element is inserted and no delay element is inserted in said first delay line. 5. The logic verification apparatus for an event-driven simulator according to claim 1, wherein the definition of the relative delay relationship is to insert a delay element into the first delay line. 6. The logic verification device for an event-driven simulator according to claim 1, further comprising an extraction unit for extracting the first signal line and the second signal line. 7. Extracting a second module connected to the first module, extracting a third module connected to the first module, and extracting a signal line between the first module and the second module. Defining a first delay state; defining a second delay state of a signal line between the first module and the third module; a first of the first module based on the definition of the first delay state. Outputting a logic verification result; outputting a second logic verification result of the first module based on the definition of the second delay state; comparing the first logic verification result with the second logic verification result Determining whether there is a difference between a first logical verification result and the second logical verification result.