JP2000293555A - Device and method for verifying lsi circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LSI verification device and its method capable of analyzing a false error of a timing verification result at the time of logical verification by executing timing error analysis based on logic. SOLUTION: After acquiring the information of a register to be analyzed on the basis of a library 15 having timing restriction information depending on timing error information 13, a net list 14 and logic, the logical value of each event is determined on the basis of a simulation pattern 17 and the logical value of the register to be analyzed is compared with a condition in the library 15, so that whether a timing error in the simulation pattern 17 is a real error or a false error can be analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LSI circuit verification device and an LSI circuit verification method, and more particularly, to an LSI circuit verification device and an LSI circuit verification method for analyzing a pseudo error of a timing verification result.

[0002]

2. Description of the Related Art In a conventional LSI circuit verification apparatus 30, as shown in FIG. 11, a logic verification tool 31 using a cycle-based simulator or the like and a timing verification by a static timing analysis tool 32 are executed in separate flows. The entire LSI circuit is verified by analyzing the independent logic verification results 33 and the timing verification results 34, respectively. Prior to the development of the LSI circuit verification device 30, verification was performed by delay simulation in which logic verification and timing verification were simultaneously performed by inputting a pattern and transmitting a signal.

[0003] However, the verification by the delay simulation has a problem that the verification time becomes enormous as the circuit scale increases and the coverage of the verification decreases. Therefore, an LSI circuit verification device 30 has been developed in order to improve the reduction in coverage. The static timing analysis comprehensively analyzes the delay path of the entire circuit without using a pattern, and the logic verification performs signal propagation without considering the delay value to increase the verification coverage while verifying. We are trying to reduce time.

[0004]

The above-mentioned conventional LSI
The circuit verification device has the following problems. First, in timing verification, there are many spurious errors due to comprehensive analysis of delay paths, and it took time to find and analyze true errors from the verification results. Second, since the logic verification and the timing verification are executed separately, it is not possible to sufficiently analyze the logic-dependent timing constraints.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is an LSI circuit verification device capable of performing a pseudo error analysis of a timing verification result at the time of logic verification by analyzing a timing error based on logic. And LS
It is intended to provide an I-circuit verification method.

[0006]

In order to achieve the above-mentioned object, the invention according to claim 1 provides timing error information,
Input means for inputting a library having logic-dependent timing constraint information, a netlist and a simulation pattern, and obtaining information of a register to be analyzed based on the timing error information, the library and the netlist, and obtaining each event based on the simulation pattern Logic verification means for determining the logical value of the register, comparing the logical value of the analysis target register with the condition in the library, and analyzing whether the timing error information is a true error or a pseudo error in the simulation pattern. There is.

That is, when a library and a netlist having timing error information and logic-dependent timing constraint information are inputted to the input means, the logic verifying means, based on the inputted timing error information, library and netlist, To obtain the information of the analysis target register.

When the simulation pattern is input by the input means, the logic verification means determines the logical value of each event based on the input simulation pattern, and determines the logical value of the analysis target register and the condition in the library. And analyze whether the timing error information in the simulation pattern is a true error or a pseudo error. The input means may be any means for inputting a timing error information, a library having logic-dependent timing constraint information, a netlist and a simulation pattern, and may be input sequentially by an operator, or may be a predetermined input. It may be input automatically in the procedure.

[0009] As an example of the timing error information, the invention according to claim 2 is the LSI circuit verification device according to claim 1, wherein the timing error information is output from a static timing analysis tool. That is, when the timing error information is output from the static timing analysis tool, the output timing error information is input to the input unit.

The simulation pattern may be singular or plural, and as an example of the configuration in the latter case, the invention in claim 3 is based on any one of claims 1 and 2 above. The input means inputs a plurality of simulation patterns, and the logic verification means determines the logical value of each event based on each simulation pattern, and determines the logical value of the register to be analyzed. It is configured to compare with the conditions in the library and analyze whether the timing error information is a true error or a pseudo error in each simulation pattern.

That is, when a plurality of simulation patterns are input by the input means, the logic verification means determines the logical value of each event based on each of the input simulation patterns, and determines the logical value of the register to be analyzed. A comparison is made with the conditions in the library, and an analysis is made as to whether the timing error information is a true error or a pseudo error in each simulation pattern.

The logic verification means includes timing error information,
The information of the register to be analyzed is obtained based on the library and the netlist, the logical value of each event is determined based on the simulation pattern, and the logical value of the register to be analyzed is compared with the condition in the library. Any analysis of whether the timing error information is a true error or a pseudo error may be performed, and the analysis result may be output, or may be accumulated and held.

[0013] As an example of the configuration in the former case, the invention according to claim 4 is the LSI circuit verification apparatus according to any one of claims 1 to 3, wherein the logic verification means includes a timing error information in a simulation pattern. Is configured to output a result of analyzing whether the error is a true error or a pseudo error as a circuit verification result.
That is, when the logic verification unit analyzes whether the timing error information is a true error or a pseudo error in the simulation pattern, the analysis result is output as a circuit verification result.

Here, as an example of a configuration in which the logic verification means analyzes whether or not a timing error occurs in a plurality of simulation patterns, the invention according to claim 5 is directed to the LSI circuit verification according to claim 4. In the apparatus, the logic verification means is configured to output a circuit verification result when the analysis of whether the timing error information is a true error or a pseudo error in a plurality of simulation patterns input by the input means is completed.
That is, when a plurality of simulation patterns are input by the input unit, the logic verification unit outputs a circuit verification result when analysis of all the input simulation patterns is completed.

As described above, when the circuit verification results are output when the analysis is completed for all the input simulation patterns, the analysis results can be output collectively. From the viewpoint that the verification result can be output, it is also possible to output the circuit verification result every time the analysis is performed for each simulation pattern.

As described above, the method of analyzing a pseudo error of a timing verification result at the time of logic verification is not necessarily limited to a substantial device. When a library and a netlist having logic-dependent timing constraint information are input, the input timing error information, the information of the register to be analyzed is obtained based on the library and the netlist, and when a simulation pattern is input, Determine the logical value of each event based on the input simulation pattern,
The logic value of the register to be analyzed is compared with the condition in the library, and the simulation pattern is analyzed to determine whether the timing error information is a true error or a pseudo error. That is,
The present invention is not necessarily limited to a substantial device, and is effective as a method.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an LSI circuit verification device according to an embodiment of the present invention.

The LSI circuit verification apparatus 10 includes a static timing analysis tool (a tool generally called an STA tool) 11 for statically verifying the timing of an LSI circuit.
And a logic verification tool unit 12 represented by a cycle-based simulator. The static timing analysis tool 11 statically verifies the timing of the LSI circuit,
The timing error information 13 is output. As a result of the analysis, the timing error information 13 reports the instance name and terminal name of the register determined to be in violation of the constraint and the path from the preceding register to the register determined to be in violation of the constraint.

The logic verification tool section 12, when given a timing error information 13, a net list 14, and a library 15 having logic-dependent timing constraint information, sets information of a register to be analyzed. As the analysis target register, each instance in which an error of the timing error information has occurred is set. At the same time as performing the logic verification, the analysis target register is analyzed,
The circuit verification result 16 is output.

In analyzing the register to be analyzed, it is analyzed whether the timing error information is a pseudo error. Library 1 having logic-dependent timing constraint information
In FIG. 5, a block name and a condition when the timing constraint in each block becomes valid are indicated by a logical expression. The netlist 14 includes circuit configuration instances, blocks, terminals, and connection information.

The simulation pattern 17 includes stimulus information of an input signal for performing logic verification. The circuit verification result 16 includes information on timing constraint violation and the result of logic verification. Therefore, the input unit (not shown) for inputting the timing error information 13, the net list 14, the library 15, and the simulation pattern 17 constitutes an input means according to the present invention in this sense. Further, the logic verification tool unit 12 for performing logic verification in the LSI circuit constitutes a logic verification unit according to the present invention in this sense.

Next, the operation of the LSI circuit verification apparatus 10 according to the present embodiment will be described with reference to FIG.
An example of information (file) that is input / output of each unit will be described with reference to FIGS. In the example of the timing error information 13 shown in FIG. 3, the instance name (here, "/ to"
p / reg2 "and" / top / reg3 "), a block name (here," DFFS "and" DFFR "), and a report of the path from the previous stage to the register determined to have violated the constraint are obtained.

In the example of the library 15 having the timing constraint information depending on the logic shown in FIG. 4, the block names (here, "DFF1", "DFFS", "DFFR") are used.
And a condition when a timing constraint exists in each block (here, CheckEnable of each block)
le item) is represented by a logical expression.

As the net list 14, the circuit shown in FIG. 5 is used, and as the simulation pattern 17 and the circuit verification result 16, those shown in FIGS. 6 and 7 are used. First, the timing of the LSI circuit is statically verified (step S100), and the timing error information 13 is obtained.

In the logic verification tool section 12, when the timing error information 13 obtained in step S100, the library 15 having the logic-dependent timing constraint information and the netlist 14 are given, the register to be analyzed is set (step S100). S110). Each instance of the timing error information 13 where an error has occurred is set as an analysis target register, and information on the analysis target instance / block is obtained from the library 15 and the netlist 14 having logic-dependent timing constraint information. Here, the analysis target register is “DFF
S: / top / reg2 "and" DFFR: / top
/ Reg3 ".

The simulation pattern 17 is input,
When the simulation is started, the logic verification tool unit 1
2 performs processing for each event of the simulation pattern (step S120). When an event occurs, first, a logical value is determined (step S13).
0), and analyze the analysis target register (step S14)
0). In the analysis processing of the analysis target register, it is determined whether the error of each instance is a true error or a pseudo error.

Library 15 having timing constraint information in which the logical value of the register by each event depends on the logic
When the timing constraint described in CheckEnable is satisfied, the register is regarded as a true error because the register always generates a timing error in the simulation using the input simulation pattern 17. On the other hand, when the logical value of the register does not satisfy the timing constraint condition, the register does not generate a timing error in the simulation, and is regarded as a pseudo error.

Here, the above-described processing will be described using the case of Event 3 of the simulation pattern. First, analysis is performed on “DFFS: / top / reg2” among the analysis target registers set in step S130 (step S150).

"DFFS: / top" at Event 3
The logical value of “/ reg2” is SET = “0”, and the timing constraint “SET / =“ 1 ”&&” described in the CheckEnable of the DFFS of the library 15 having the logic-dependent timing constraint information.
Since DIN / = DOUT "is satisfied, it is excluded from the analysis target register (step S160).

That is, "DFFS: / top / reg"
Since it has been determined that the timing error “2” is not a pseudo error, it is excluded from the analysis in the subsequent events.

The same analysis is performed for "DFFR: / top / reg3" (step S150). Event
The logical value of “DFFR: / top / reg3” at the time of 3 is RESET = “1”, and the DFFR “C
HackEnable: RESET / = '1'&& D
IN / = DOUT ", and the timing error of the register remains as an analysis target register because the possibility of a pseudo error remains. The above-described operation is repeated for each event until the event ends (step S).
170).

The register remaining as an analysis target register until the simulation event ends is a register in which a timing error does not occur as long as the operation of the simulation pattern 17 is performed, so that the register is processed as a pseudo error (step S180). Then, the timing error information 13 excluding the pseudo error is output as a true error to the circuit verification result 16 (step S190). In the simulation pattern 17, since there is no condition pattern in which the timing error occurs in the register of "DFFR: / top / reg3", it is determined as a pseudo error.

Therefore, "DFFR: / top / reg
Only the 3 "error is a true error and the circuit verification result 16
Is output to In the present embodiment, the logic verification is performed using only a specific simulation pattern. However, the present invention is not necessarily limited to the case where a single simulation pattern is used, and as shown in FIG. Can also be used.
That is, by allowing n simulation patterns 20 to be input, as shown in FIG. 9, step S245 is added to S200 to S240 and S250 which are the same as in FIG. The determination as to whether an error has occurred is made after the end of all the input simulation patterns.

Therefore, for example, when the simulation pattern of FIG. 10 is input in addition to the simulation pattern of the present embodiment, “DFFR: / top / reg3”
Will not be a pseudo error but will be analyzed as a true error.

As described above, the timing error information 13,
After acquiring the information of the analysis target register based on the net list 14 and the library 15 having the logic-dependent timing constraint information, the simulation pattern 17 is obtained.
The logical value of each event is determined on the basis of the above, and the logical value of the register to be analyzed is compared with the condition in the library 15 having the timing constraint information depending on the logic. Or a pseudo error can be analyzed.

[0036]

As described above, the present invention can provide an LSI circuit verification device capable of performing a pseudo error analysis of a timing verification result at the time of logic verification. Further, according to the invention of claim 2, it is possible to perform an analysis based on the timing error information output from the static timing analysis tool.

Further, according to the invention of claim 3,
Analysis can be performed based on a plurality of simulation patterns. Further, according to the invention of claim 4, it is possible to output an analysis result as a circuit verification result.

Further, according to the invention of claim 5,
When analysis is performed based on a plurality of simulation patterns, circuit verification results can be output together.
Further, according to the invention of claim 6, it is possible to provide an LSI circuit verification method capable of analyzing a pseudo error of a timing verification result at the time of logic verification.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an LSI circuit verification device according to an embodiment.

FIG. 2 is a flowchart illustrating a procedure for performing circuit verification.

FIG. 3 is an example of timing error information.

FIG. 4 is an example of a library having logic-dependent timing constraint information.

FIG. 5 is a circuit diagram showing an example of a net list.

FIG. 6 is a pattern diagram showing an example of a simulation pattern.

FIG. 7 is an example of a circuit verification result.

FIG. 8 is a block diagram illustrating a schematic configuration of an LSI circuit verification device according to a modification.

FIG. 9 is a flowchart illustrating a procedure for performing circuit verification in a modified example.

FIG. 10 is a pattern diagram illustrating an example of a simulation pattern according to a modification.

FIG. 11 is a block diagram showing a schematic configuration of a conventional LSI circuit verification device.

[Explanation of symbols]

Reference Signs List 10 LSI circuit verification device 11 Static timing analysis tool 12 Logic verification tool unit 13 Timing error information 14 Netlist 15 Library having logic-dependent timing constraint information 16 Circuit verification result 17 Simulation pattern

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) H01L 21/82 T 9A001 F term (reference) 2G003 AA07 AB00 AF06 AH02 2G032 AA04 AB06 AB20 AC03 AC08 AD06 AE12 4M106 AA02 BA20 CA70 DH01 DJ20 5B046 AA08 BA04 JA05 JA07 5F064 HH06 HH09 HH10 HH12 HH13 HH14 9A001 BB05 DD15 HH32 LL05

Claims (6)

[Claims] An input means for inputting a library, a netlist and a simulation pattern having timing error information and logic-dependent timing constraint information, and information of a register to be analyzed based on the timing error information, the library and the netlist. Obtain and determine the logical value of each event based on the simulation pattern, compare the logical value of the analysis target register with the condition in the library, and determine whether the timing error information in the simulation pattern is a true error or An LSI circuit verification device comprising: logic verification means for analyzing whether a pseudo error has occurred. 2. The LSI circuit verification device according to claim 1, wherein the timing error information is output from a static timing analysis tool. 3. The L according to claim 1, wherein
In the SI circuit verification device, the input unit inputs a plurality of simulation patterns, the logic verification unit determines a logical value of each event based on each simulation pattern, and sets a logical value of the analysis target register and the logical value of the event. An LSI circuit verification device, which compares with conditions in a library and analyzes whether a timing error information is a true error or a pseudo error in each simulation pattern. 4. The LSI circuit verification device according to claim 1, wherein the logic verification means analyzes whether the timing error information in the simulation pattern is a true error or a pseudo error. An LSI circuit verification device for outputting a result as a circuit verification result. 5. The LSI circuit verification device according to claim 4, wherein the logic verification means determines whether the timing error information is a true error or a pseudo error in the plurality of simulation patterns input by the input means. An LSI circuit verification device which outputs the circuit verification result when the analysis is completed. 6. When a library and a netlist having timing error information and logic-dependent timing constraint information are input, information on a register to be analyzed is acquired based on the input timing error information, library and netlist. When the simulation pattern is input, the logic value of each event is determined based on the input simulation pattern, the logical value of the analysis target register is compared with the condition in the library, and the timing in the simulation pattern is determined. An LSI circuit verification method characterized by analyzing whether error information is a true error or a pseudo error.