JP2830579B2 - Logic simulation equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for supporting design of a logic circuit formed in an integrated circuit. The present invention is used for expected value matching in consideration of delay in logic simulation. The present invention relates to a logic simulation apparatus capable of automatically performing a timing analysis of a created logic circuit by using an input pattern and an expected value used for logic correctness check.

[0002]

2. Description of the Related Art In recent integrated circuits, the degree of integration on one chip has become larger than before, and the development period has been gradually shortened. Previously, a system was designed by combining integrated circuits of several chips on a printed circuit board. However, an increase in the degree of integration on a chip has made it possible to construct one system on one chip. In the case of an integrated circuit, if a design error is found after a chip is produced, re-prototyping is performed, and the development cost and development period are enormous.

Therefore, sufficient design verification is required before trial production. In such a large-scale integrated circuit, it is customary to imitate the operation of a logic circuit on a computer and find out a design error of the integrated circuit. I have. In recent high-integration, high-speed circuits, it is becoming essential to design a circuit in consideration of timing such as delay instead of verifying only the logical operation of the circuit. For this reason, recent simulators have been moving toward simulators that more closely resemble the behavior of actual devices in consideration of various factors such as element delays and wiring delays that occur when the device becomes an actual device.

One of the timing analysis is a method called dynamic analysis. In this method, parameters such as the delay time of an element, the delay time of wiring between elements, and the setup time of a flip-flop (hereinafter referred to as F / F) generated when a device is actually formed are stored in a library, and circuit connection information is stored. Calculate the delay time taking into account the connection relationship and the number of fanouts based on the above, incorporate this delay time into the logic simulation that considered only the logical value, and simulate with the input pattern prepared in advance, This is an analysis method in which the simulation result is compared with an expected value, and if there is a mismatch, the cause is checked to correct the circuit, and circuit correction and simulation are repeated until the mismatch is eliminated.

As another timing analysis, F / F
There is also a method called static analysis used for verification of setup time, hold time, and critical path verification. The static analysis is to analyze the delay between the F / Fs and the operation speed by focusing on the F / Fs of the circuit without using an input pattern. The circuit shown in FIG. 6 (a) is a synchronous circuit according to a single-phase clock. Hereinafter, the static analysis will be described using this circuit.

The F / Fs used in this circuit both take in data at the rising edge of the clock. In the F / F 15, the data setup time for the rising edge of the clock is TS, the period of the clock CLK is CP, and the F / F is F / F. The delay between F14 and F / F15 is D1
Then, in the static analysis, the delay of the element and the wiring delay are sequentially added while searching for the connection information of the circuit to obtain the delay D1, and it is checked whether or not the following equation is satisfied.

TS + D1 ≦ CP If the above equation is not satisfied, there is a problem in the circuit, and a circuit designer is instructed that the circuit needs to be corrected.

[0008]

When trying to find a critical path in a dynamic analysis method,
The simulation results of all elements in the circuit are output, and the human observes the simulation results and manually examines the margin of the signal from the element at the preceding stage of the F / F to the F / F with respect to the setup time and the like. It is necessary to find the F / F with the smallest margin. However, a simple circuit with a small number of elements in the circuit can be examined using this method.However, it takes an enormous amount of time to manually perform a circuit of tens of thousands or hundreds of thousands, which is impractical. It is.

Also, in the static analysis method, basically single-phase clock synchronization is mainly used, and there are the following problems in multi-phase synchronization and asynchronous. Figure 7 F / F16 circuit is shows an example of a two-phase synchronous circuit (b) is CLK
1, the F / F 17 operates at CLK2. In the case of static analysis, no input pattern is given and CLK
The timing at which 1 and CLK2 rise is not clear from the circuit connection information alone, so it is not possible to analyze the relationship between the F / F 16 and the F / F 17 in which the respective data is taken, and analysis is not possible.

Moreover, F / F18 with those circuit of FIG. 7 (c) shows an example of an asynchronous circuit whereas operates with a period of CLK1, the combination circuit to the clock terminal C of the F / F19 Output Are connected, and the timing at which the F / F 19 takes in data from the F / F 18 is determined based on the result of the logical operation. For this reason, in the static analysis in which no input pattern is given, the timing at which the F / F 19 takes in the data cannot be determined, and the analysis cannot be performed.

[0011] Next, the circuit shown in FIG. 8 (d) is an example but analysis is difficult for static analysis is a synchronous circuit according to a single-phase clock which does not give an input pattern. In the multiplexer in this circuit, the select signal S is "1".
If the static analysis is performed assuming that the input terminal A is selected at the time of, the path with the longest delay time is selected without looking at the logic when finding the path between F / F. Has input terminal IN2 → F / F21 →
The path of delay 23 → multiplexer 24 → delay 26 → multiplexer 27 → F / F29 → output terminal OUT is found as a critical path.

This is because the delay connected to the input terminal B in the multiplexers 24 and 27 is larger. However, opposite logics are input to the select terminals S of the multiplexers 24 and 27 via the inverter 28, so that the input terminal B of the multiplexer 24 and the input terminal B of the multiplexer 27 are not simultaneously selected.

Therefore, it is understood that the critical path found by the static analysis is not used in the actual circuit. In this case, the real critical path to be determined is IN2 → F / F21 → delay 23 → multiplexer 24 → delay 25 → multiplexer 27 → F /
F29 → OUT path.

If the circuit operates in a multi-phase or asynchronous manner, it is difficult to find a critical path. In a synchronous circuit using a single-phase clock, an erroneous path may be indicated as a critical path. In the static analysis and the symmetric dynamic analysis, the matching / mismatch of the simulation results makes it possible to only confirm the logical operation desired by the user and is not suitable for detecting the critical path.

The present invention has been made in view of such a background, and it is possible to easily find a critical path that becomes a problem when actually used, and to preempt a failed state when an actual product is put on a tester. It is an object of the present invention to provide a device capable of analysis.

[0016]

According to the present invention, an input device, an output device, a display device, and a storage device are connected to a central processing unit, and the storage device is connected to the central processing unit by an instruction input from the input device. A logic simulation device that takes in an input pattern and circuit information stored in advance in the logic device, executes logic simulation, and outputs an output pattern to the output device and / or the display device. Pattern compression means for compressing the period of the output pattern, and providing the input pattern compressed by the input pattern compression processing to the logic simulation means, comparing the simulation result with the output pattern compressed by the pattern compression means, and Putter to output the result Matching means, repetitive execution control means for repeatedly controlling the execution of each of the processes, and mismatched point search means for searching for a mismatched point where a mismatch first occurs during the pattern matching processing by the pattern matching means. It is characterized by.

[0017]

The input pattern after the normal dynamic logic simulation is completed and the result is confirmed as expected by the user is set as a reference input pattern, and the output pattern at this time is set as a reference expected value, and one of the reference input patterns is used. Compress the cycle to make it smaller. After this compression processing, an input pattern and circuit connection information are input to perform a simulation, and the simulation result is compared with a reference expected value to determine whether or not a mismatch occurs. The above processing is repeated in the same order until at least one mismatch is found in the expected value matching processing.

In such a simulation, since the input pattern and the expected value pattern are sequentially compressed, the period of one pattern is gradually reduced. However, since the delay time due to the element or the wiring takes a value predetermined by the library used, the delay time of the output signal of each element takes a constant value even if the input pattern is compressed. Therefore, as the expected value is compressed, the width of one pattern becomes shorter, and a mismatch occurs in the expected value matching process.

When a mismatch is found, the information on all element dumps based on the compressed pattern and the information on all element dumps on all the patterns of the circuit prepared by performing a simulation based on the reference input pattern are compared with the time when the mismatch occurs. Matching patterns are successively compared to find out where in the circuit the mismatch first occurred with reference to the circuit connection information, and output a path including the found element.

Thus, without picking up a path that exists as a path with a large delay but is not used in actual operation, it is possible to easily find a critical path that poses a problem in actual use. It is possible to perform a preemptive analysis of a fail state when a product is put on a tester.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

According to the present invention, the central processing unit 1 includes an input device 2,
The output device 3, the display device 4, and the storage device 5 are connected, and the central processing unit 1 takes in an input pattern and circuit information previously stored in the storage device 5 according to an instruction input from the input device 2, and executes a logic simulation. A logic simulation means 11 for outputting an output pattern to the output device 3 and / or the display device 4 is provided. As a feature of the present invention, a pattern compression means 12 for compressing the period of the input pattern and the output pattern, Pattern matching means 13 for providing the compressed input pattern to the logic simulation means 11, comparing the simulation result with the output pattern compressed by the pattern compression means 12, and outputting the result;
It includes a repetition execution control means 14 for repeatedly controlling the execution of each of the above-mentioned processes, and a non-coincidence point search means 15 for searching for a non-coincidence point where a first non-coincidence occurs during the pattern matching processing by the pattern matching means 13.

FIG. 2 is a diagram for explaining the processing performed by the apparatus according to the embodiment of the present invention.

In the pattern compression processing 101 by the pattern compression means 12, the logic simulation 10
2, after the verification of the operation is completed, the input pattern 106 and the expected value 107 used at that time or the compressed input pattern 108 and the expected value 109 after compression in which the pattern compression processing 101 has already been performed are stored. A post-compression input pattern 108 and a post-compression expected value 109 which are input and further compressed are output.

In the logic simulation 102 by the logic simulation means 11, the compressed input pattern 10
8 and circuit connection information 110 are input, and a simulation result 111 or a simulation result 112 of all elements is input.
Is output.

In the expected value matching process 103 by the pattern matching means 13, the simulation result 111 and the expected value after compression 109 are input and a result indicating whether or not a mismatch has occurred is output.

In the repetition execution control processing 104 by the repetition execution control means 14, the execution control of the pattern compression processing 101, the logic simulation 102, the expected value collation processing 103, and the repetition execution control processing 104 is performed. In the location search processing 105, circuit connection information 110, simulation results 112 of all elements, and expected values 113 of all elements are input and the results are output.

FIG. 3 is a flowchart showing an execution procedure of the embodiment of the present invention.

The initial input pattern and expected value, or the input pattern after compression and the expected value after compression are read out (step S1), the read pattern is subjected to pattern compression processing (step S2), and the compressed input is performed. The pattern and the expected value after compression are output (step S3).

[0030] will be described with reference to FIGS. 4 and 5 for the compression process. The pattern read from step S1 is
As shown in FIG . In step S2, compression represented by the compression ratio P is performed on the pattern of FIG .

NEW. LENGTH = P * OLD. LENGTH NEW. LENGTH: Total pattern length after compression P: Compression ratio (0 <P <1) OLD. LENGTH: Total pattern length before compression The total pattern length before compression is 100 ns per pattern, and is 30
When there are 00 patterns (3000 * 100 ns) and the compression ratio P is 0.9, the total pattern length after compression is 90 ns per pattern and 3000 patterns (3000 * 90 ns).
s). This means that the pattern cycle is gradually reduced at the compression rate P, and each change point of the input pattern is similarly compressed at the compression rate P with the compression of the pattern cycle. FIG. 5 shows the input pattern after compression and the expected value after compression output in step S3.

This is when the compression ratio P is 0.5, and the total number of patterns is from 1400 ns (200 * 7) to 70
It can be seen that the data is compressed in half to 0 ns (100 * 7), and each change point in the pattern also changes at half the time as compared with the pattern in FIG . However, the delay time of the output signal by the element and the wiring is a value peculiar to the library, and takes a constant value regardless of the compression of the input pattern.

The compressed input pattern and the circuit connection information output in step S3 are
1 is converted to internal data that can be handled (step S
4) The simulation of only one pattern is performed by the logic simulation means 11 (step S5), and the simulation result is normally output (step S6).
The normal simulation result output in step S6 is compared with the expected value after compression output in step S3 (step S7).

[0034] Here, a 4 reason for mismatch occurs when gradually reducing the pattern width by compressing the pattern
This will be described with reference to FIG. I1, I are connected to the NAND gate
Output 01 when the input pattern shown by 2 is given
It is shown in FIG. 6 (a) of change. It can be seen that the delay times until the output changes with respect to the change in the input signal are a and b. Turning now to FIG. 6 (b) obtained by compressing the period of this pattern,
Although the cycle of the input pattern and the expected value is reduced and the time between each change point is reduced, the delay time from the input change to the output change remains a and b.

This is because the delay time from the change of the input of the element to the change of the output is a constant value described in advance in a library or the like, so that it is not affected by the pattern cycle. Therefore, when the value of the pattern period is smaller than the total value of the delay times of the signals from the input terminal to which the input pattern is provided to the output terminal for which the expected value is prepared, a mismatch occurs.

The input pattern period by compression pattern also in the circuit shown in FIG. 8 (d) becomes smaller, F / F
20, M from the rising of the clock terminal C of the F / F 21
Element to the signal at the output terminal O of the UX27 changes, each total value of line delay time Da, a post Db time, which is either a post pattern compression shown in pattern compression before and 5 shown in FIG. 4 The same applies to Since the change of the output terminal O of the MUX 27 in FIG. 4 before the pattern compression is sufficiently faster than the rising edges C2 and C3 of the clock signal, the F / F 29 can take in the data after being stabilized.

[0037] In the following pattern compression shown in FIG. 5, MUX2
7 changes at the rising edge C of the clock signal.
In time for 2 ', the output does not cause a mismatch because the F / F 29 can take in the correct data. However, since the output O of the MUX 27 changes later with respect to the rising edge C3 'of the clock signal,
/ F29 cannot capture correct data, and its output terminal OUT causes a mismatch.

The elements of the circuit in the circuit from the input terminal to the output terminal for which the expected value is prepared,
When the value becomes smaller than the total value of the wiring delays, a mismatch occurs. At this time, it is considered that the first mismatch occurs due to the critical path.

As a result of the expected value comparison performed in step S7, if no mismatch occurs, the process proceeds to step S9. If no mismatch occurs, the process branches to step S10 (step S8).

If no mismatch occurs in step S8, the number of patterns to be simulated is increased by one pattern, and the process returns to step S5. If the simulation has been completed for all patterns, the process returns to step S1 to repeat the same processing (step S9). ).

If a mismatch occurs in step S8, the internal data is initialized and converted into internal data of the logic simulation means 11 capable of handling the compressed input pattern and circuit connection information output again in step S3. Then, the simulation results for all the elements in the circuit are set to be stored in the internal data (step S10), the re-simulation up to the mismatch occurrence pattern is performed (step S11), and the output terminals of all the elements in the circuit in the mismatch occurrence pattern Is output (step S12).

In step S13, the result of simulation of all elements output in step S12 is compared with expected values of all elements prepared for each pattern in advance to determine a case where a mismatch occurs. If there are several places, by referring to the circuit connection information 110 and searching for the connection relationship, the mismatch occurrence element is checked,
In the expected value comparison of the output terminal, a mismatched portion which causes a mismatch is searched for and the information is output to the display device 4.

The information output at this time allows the user to know the location in the circuit where the mismatch has occurred, and to find a critical path that may cause a problem during operation of the actual device.

[0044]

As described above, according to the present invention, analysis can be performed regardless of polyphase synchronization or non-synchronization, and only paths operating in a pattern in an actual circuit can be checked. However, it is possible to easily find a critical path that poses a problem in actual use without picking up a path that exists as a path with a large delay but is not used in actual operation. In this case, there is an effect that it is possible to perform a preemptive analysis of a fail state when a failure occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining processing contents by the apparatus according to the embodiment of the present invention;

FIG. 3 is a flowchart showing an execution procedure of the embodiment of the present invention.

FIG. 4 is a diagram showing an example of the relationship between an input pattern given to a circuit and an expected value when pattern compression processing is not performed in the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a relationship between an input pattern given to a circuit and an expected value when a pattern compression process is performed in the embodiment of the present invention.

FIG. 6 is a view for explaining a delay time due to pattern compression in the embodiment of the present invention.

FIG. 7 is a diagram showing an example of a circuit diagram used for describing the embodiment of the present invention.

FIG. 8 is a diagram showing an example of a circuit diagram used for describing the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Input device 3 Output device 4 Display device 5 Storage device 11 Logic simulation means 12 Pattern compression means 13 Pattern collation means 14 Repetition execution control means 15 Mismatch location search means

Claims (1)

(57) [Claims] 1. An input device, an output device, a display device, and a storage device are connected to a central processing unit, and an input pattern previously stored in the storage device in response to an instruction input from the input device is connected to the central processing unit. A logic simulation device comprising logic simulation means for taking in circuit information and executing a logic simulation to output an output pattern to the output device and / or the display device, wherein the central processing unit compresses the period of the input pattern and the output pattern. Pattern compression means; pattern matching means for providing the input pattern compressed by the input pattern compression processing to the logic simulation means, comparing the simulation result with the output pattern compressed by the pattern compression means, and outputting the result. , Each of the above A logic execution apparatus comprising: a repetition execution control means for repeatedly controlling the execution of the processing; .