JP2979798B2 - Test pattern guarantee method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for guaranteeing a test pattern of a logic circuit, and more particularly, to verify whether the pattern has a possibility of causing a timing problem at the time of a test.
Related to the test pattern assurance method.

[0002]

2. Description of the Related Art In a conventional test pattern assurance method, a plurality of simulation models, for example, a model in which delays of respective gates are uniformly applied, and a model close to a real chip in which layout information is added are created and simulated. A method has been adopted in which a pattern failure that is crucial in terms of timing is detected by comparing expected values. Alternatively, the pins whose input set values are simultaneously changed are shifted so that the pins change one pin at a time, simulated with the same simulation model, and collated with the original expected value, so that the A method of detecting a pattern that may cause a malfunction due to skew has been employed.

[0003]

According to the above-mentioned conventional method, since it takes a lot of time to perform the simulation in consideration of the timing, when there is an error, it is necessary to correct the pattern.
If re-verification is repeated, there is a problem that the period for creating test data becomes very long.

There is another problem that it is difficult to analyze the cause of the problem even when the expected values of the simulation do not match.

SUMMARY OF THE INVENTION It is an object of the present invention to correct a verification of a pattern which may cause a timing problem at the time of test in a short time and directly to find out the cause in creating a test pattern of a logic circuit. It is an object of the present invention to provide a test pattern assurance method for making high quality test data.

[0006]

According to a first aspect of the present invention, there is provided a method for assuring a test pattern of a logic circuit, wherein a simulation model is created from design information of the logic circuit, and a test pattern is applied to the model. Alternatively, a simulation process for performing a failure simulation, a violation rule for detecting a violation on the test pattern and a correction
A violation / correction rule obtaining process for obtaining correction rules;
Based on the violation rule obtained by the violation rule acquisition step, a violation pattern detecting step of detecting a violation of the test pattern, a violation in the violation pattern detecting process determines
It has been modified sequence and the value of the test pattern Le
A violation pattern correcting step based on the rule .

[0007]

Alternatively, as a second method, in the first method, instead of performing the simulation step, the violation pattern detection step and the violation pattern correction step, performing the logic or failure simulation,
A test pattern verification / correction simulation for detecting a rule violation of an input state value and an output state value change for each test pattern sequence, and continuing the simulation while correcting the sequence and value of the test pattern when the violation is determined. Process.

Alternatively, as a third method, in the above-mentioned second method, in place of the test pattern verification / correction simulation step, in the process of generating the test pattern, a violation of the test pattern is performed based on the violation rule. Test pattern verification that detects and detects a violation and continues to generate test patterns while correcting the sequence and values of the test patterns based on the correction rules.
A modified test generation step is included.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart of a first embodiment of the present invention. Part 1 surrounded by a dotted line in FIG.
Is a test pattern guarantee method. In the violation rule acquisition step 2, violation rule 3 is acquired. An expected value is created for the test pattern 4 with no expected value by the simulation process 5 and a test pattern 6 with the expected value is output. In the violation pattern detection step 9, two consecutive patterns of the test pattern are compared based on the violation rule 3 to check which terminal value has changed how, and to detect a portion having a timing problem. I do. For a part having a problem, in a rule violation pattern output step 10, a pattern number, an error content, a change state of a terminal / value, and the like are output as error information 11. If there is an error,
The pattern is corrected in the manual pattern correction step 12, and verification is performed again by the verification method 1. When there is no error, the test pattern 6 with the expected value is paid out as test data.

FIG. 2 is a flowchart of a second embodiment of the present invention. In a violation / correction rule obtaining step 8, a violation / correction rule 17 is obtained. Based on this rule, a part having a timing problem is detected in a violation pattern detection step 9, and a pattern is inserted in a violation pattern correction step 13. Simulation process 5
To generate a test pattern 14 containing a pattern correction expected value. This pattern is issued as test data.

FIG. 3 is a flowchart of a third embodiment of the present invention. The test pattern verification / correction simulator 15 simulates the test pattern 4 with no expected value, inserts a pattern if there is a timing problem based on the violation / correction rule 17, and creates an expected value. Test pattern with expected pattern correction value 14
Is output.

FIG. 4 is a flowchart of a fourth embodiment of the present invention. Pattern verification correction test generation process 1
In step 6, in the automatic pattern generation, among the patterns generated by the algorithm, if there is a timing problem based on the violation / correction rule 17, the pattern is inserted / corrected to generate an expected value. Then, a test pattern 14 having a pattern correction expected value is output.

FIGS. 5 to 9 show examples of data for specifically explaining a violation pattern detection and correction method. FIG. 5 shows an example of the expected value-containing test pattern 6, FIGS. 6 and 7 show the violation rule 3 and the violation / correction rule 17, respectively, and FIG. 8 shows the result by the processing of the violation pattern detection step 9 and the rule violation pattern output step 10. FIG. 9 shows an example of the error information 11 to be inserted, and FIG. 9 shows an example of a test pattern inserted by the violation pattern correction step 13 or the test pattern verification / correction simulation step 15 and the test pattern verification / correction test generation step 16. A case where the violation rule does not allow simultaneous input changes of clocks and clocks or clocks and data having different numbers of phases as shown in FIG. From FIG. 5, in the change from the input setting 1 to the input setting 2, the one-phase clock pin A changes from 0 to 1 and is active. Also, the two-phase clock pin D, which is opposite in phase to the clock A, is active from 1 to 0. Further, the normal input pin C also changes from 0 to 1, violating the rule. In the first method, this information is stored in the error information 11.
Output as In the second method, a pattern 1 in which only the clock is first changed in phase order between input settings 1 and 2 is used.
^, And 1 ^, are inserted. After that, only the data is changed to the input setting 2. In this case, the expected output value is undefined.
In the third method, insertion patterns 1 ^, 1 ^, 1 ^, are inserted, simulation is performed, and a test pattern containing an expected value is output. In the fourth method, when the pattern generated by the algorithm becomes the pattern shown in FIG. 5, the pattern is inserted and output as the pattern shown in FIG.

Violation rule 3 and violation / correction rule 17
In addition to the above, there are rules for checking bus fight and bus float of the bidirectional terminals, rules for restricting simultaneous operation of outputs, and the like. 10 to 14 show a test pattern 6 with no expected value, a violation rule 3 for avoiding a bus fight, a violation / correction rule 17, and error information 1.
1. This is an example of a modified test pattern. Since the expected value in the pattern 1 of the bidirectional terminal A that changes from the output mode to the input mode is different from the input value in the pattern 2, a bus fight error occurs. Therefore, the error information 1 shown in FIG.
1 and a pattern for inserting the previous expected value in the input mode as shown in FIG.

FIG. 15 is a flowchart for explaining the processing of the test pattern verification / correction simulation process of the third method based on the data and the violation / correction rules of the examples of FIGS. The simulation is performed by taking out one pattern at a time from the test pattern 4 with no expected value. At this time, information as to which terminal value is changing is obtained by comparing with the previous pattern. With reference to the violation rule, in this case, even if one clock changes to active and the data input changes, pattern insertion is performed. Simulate the insertion pattern and the current pattern to create an expected value. If there is no problem in the violation check, the expected pattern is created by simulating the current pattern without inserting the pattern. This is performed over all patterns.

FIG. 16 is a flow chart for explaining the processing of the test pattern verification / correction test generation process of the fourth method based on the data and the violation / correction rules of the examples of FIGS. When one of the fault models is selected and an input sequence is generated by the algorithm,
Compare with the previous expected value and check if a bus fight occurs for the bidirectional terminal. In the case of a problem, a pattern for avoiding bus fight is inserted before the generated pattern, and these two patterns are simulated to obtain an expected value and a detection rate.

[0019]

As described above, according to the present invention, it is possible to guarantee the test data in a short time, to directly point out the cause, and to correct the test data, and to produce test data of high quality. .

[Brief description of the drawings]

FIG. 1 is a flowchart of a first embodiment of the present invention.

FIG. 2 is a flowchart of a second embodiment of the present invention.

FIG. 3 is a flowchart of a third embodiment of the present invention.

FIG. 4 is a flowchart of a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram of an example of an expected value-added test pattern 6;

FIG. 6 is an explanatory diagram of violation rule 3.

FIG. 7 is an explanatory diagram of a violation / correction rule 17;

FIG. 8 is an explanatory diagram of an example of error information 11 output by the processing of a violation pattern detection step 9 and a rule violation pattern output step 10;

FIG. 9 shows a violation pattern correction step 13, test pattern verification,
An insertion pattern for explaining the operation of the correction simulator 15 and the test pattern verification / correction test generation step 16.

FIG. 10 shows an example of a test pattern 6 with an expected value.

FIG. 11 shows an example of a violation rule 3.

FIG. 12 shows an example of a violation / correction rule 17;

FIG. 13 shows an example of error information 11;

FIG. 14 is an operation explanatory view of a violation pattern correction step 13;

FIG. 15 is an operation explanatory diagram of a test pattern verification / correction simulator 15 and a test pattern verification / correction test generation step 16;

FIG. 16 shows a test pattern verification / correction test generation step 16
It is a processing flowchart of.

[Explanation of symbols]

 1 pattern verification method 2 violation rule acquisition process 3 violation rule 4 test pattern without expected value 5 simulation process 6 test pattern with expected value 7 simulation model 8 violation / correction rule acquisition process 9 violation pattern detection process 10 rule violation pattern output process 11 error Information 12 Manual pattern correction process 13 Violation pattern correction process 14 Test pattern with correction expected value 15 Test pattern verification / correction simulation process 16 Test pattern verification / correction test generation process 17 Violation / correction rule information

Claims (3)

(57) [Claims] A step of creating a simulation model from design information of the logic circuit and applying a test pattern to the model to perform a logic or failure simulation; A violation / correction rule obtaining step of acquiring a violation rule for detecting a violation of the rule and a correction rule for correction; and a violation pattern detecting a violation of the test pattern based on the violation rule obtained in the violation rule obtaining step. A test pattern assurance method, comprising: a detection step; and a violation pattern correction step of correcting a sequence and a value of the test pattern determined as a violation in the violation pattern detection step based on a correction rule. 2. The test pattern assurance method according to claim 1 , wherein said logic or fault simulation is performed in place of said simulation step, said violation pattern detection step and said violation pattern correction step.
A test pattern verification / correction simulation for detecting a rule violation of an input state value and an output state value change for each test pattern sequence, and continuing the simulation while correcting the sequence and value of the test pattern when the violation is determined. Test pattern assurance method including process. 3. The test pattern assurance method according to claim 2 , wherein a violation of said test pattern is detected based on said violation rule in said test pattern generation process instead of said test pattern verification / correction simulation step. If it is determined that a violation has occurred, the test pattern verification / continuing test pattern generation while correcting the test pattern sequence and value based on the correction rule.
A test pattern assurance method including a modified test generation process.