JP2863779B2 - Timing verification method, verification device, and test pattern generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing verification method and a verification device for a semiconductor integrated circuit, and more particularly to a timing verification method and a verification device for verifying a logic operation with a delay applied to an input pin.

[0002]

2. Description of the Related Art As a conventional timing verification method, a method of connecting a delay element such as a delay circuit between an input terminal and a semiconductor integrated circuit (JP-A-3-4184) and the operation of a semiconductor integrated circuit are confirmed. A method of adding input delay information of each input terminal to a test pattern is known.

On the other hand, in a CAD system or the like for designing a semiconductor integrated circuit, a symbol for inputting an input signal such as an input terminal is configured to simply set the attribute of the signal such as input or output and the signal name. I was

[0004]

In the conventional timing verification method described above, the delay element is connected in series with the input terminal, so that the timing verification is completed and the mask pattern is manufactured to manufacture the semiconductor integrated circuit. However, there is a problem that the delay terminal connected in series with the input terminal must be removed from the netlist data which is the configuration data of the semiconductor integrated circuit.

In the method of adding an input delay time to a test pattern for confirming the operation of a semiconductor integrated circuit, the circuit design of the conventional semiconductor integrated circuit and the test pattern design for confirming the operation are performed in a netlist in a CAD system or the like. And test patterns separately. For this reason, when designing a semiconductor integrated circuit, there is a problem that skew data between input terminals cannot be designed even if a circuit is designed in consideration of timing.

[0006]

In order to solve the above-mentioned problems, a timing verification method according to the present invention uses time difference information of a signal input to each input terminal of a semiconductor integrated circuit to be designed. The circuit connection information of the semiconductor integrated circuit is set so as to correspond to each of the input terminals, and a test pattern for confirming the operation of the semiconductor integrated circuit and the input terminal are paired.
A logic simulation is performed using the circuit connection information having the time difference information set in response thereto, and timing verification of the semiconductor integrated circuit is performed.
After confirming the normal operation of the semiconductor integrated circuit to be designed, the time difference information may be set again in the test pattern.

On the other hand, a timing verification apparatus according to the present invention comprises: a storage unit for storing time difference information of a signal input to each input terminal of a semiconductor integrated circuit to be designed; a unit for changing the time difference information; in a time difference information of the signal inputted to the input terminals of the semiconductor integrated circuit, versus the respective input terminals of the circuit connection information of the semiconductor integrated circuit
Means for setting by response, the test pattern generating means for generating an operation confirmation test pattern of a semiconductor integrated circuit, set to correspond to the input terminal and the test pattern
Logic simulation means for performing a logic simulation using the determined circuit connection information having the time difference information and performing timing verification of the semiconductor integrated circuit. Further, a means may be provided for resetting the time difference information to the test pattern after confirming the normal operation of the semiconductor integrated circuit to be designed.

[0008]

According to the timing verification method of the present invention, an input delay time set for each input terminal symbol, that is, an input skew between input terminals is extracted, and a logic simulation is performed in consideration of the input delay time. When the semiconductor integrated circuit operates normally, the input delay time set for each input terminal symbol is added to a test pattern for confirming the operation of the semiconductor integrated circuit.

In the timing verification device according to the present invention, when designing a semiconductor integrated circuit, an optimum combination of input delay times at which the semiconductor integrated circuit operates normally is set to an input terminal symbol for which an arbitrary delay time can be set. To verify the timing.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of one embodiment of the present invention. FIG. 2 shows an example in which each delay information is added to an input terminal symbol used in the present invention. FIG. 3 shows a configuration for realizing the verification device according to the invention, and is shown along a flow of adding the input delay information used in FIG. 2 to a test pattern to be input to the logic simulator.

First, when designing a semiconductor integrated circuit using the timing verification method of the present invention, it is assumed that an output signal output from another semiconductor product at a stage preceding the circuit to be designed is an input signal of the present semiconductor integrated circuit. An example in which the output signal is a data input signal and a clock input signal of a flip-flop used in the present semiconductor integrated circuit will be described.

In the design of a semiconductor integrated circuit, when a data signal and a clock signal are input at the same timing, an input signal of a flip-flop does not operate normally due to an error of insufficient setup or hold time margin.
On the other hand, in the present invention, in order to eliminate errors such as insufficient margin, as shown in FIG.
N1 has a terminal DATA to which a data signal is input.
0 ns, 20 n at the terminal CLK to which the clock signal is input
In order to provide a delay of s, delay information can be added to each input terminal at the time of circuit design.

Next, as shown in FIG. 1, a circuit diagram is created (S1).
At this time, a test pattern is created to confirm the operation of the circuit (S3), and a logic simulation is performed. here,
The input delay information of each input terminal stored in the input terminal delay information storage unit 32 of FIG.
The test pattern becomes effective when input to each input terminal, and the test pattern from the test pattern input unit 31 is input to each input terminal with a delay of a time corresponding to the input delay information (S2).

Next, the operation is confirmed by a logic simulation (S4) in the logic simulator unit 34 (S5).
Thereafter, a netlist for manufacturing a semiconductor integrated circuit and a test pattern for inspecting the netlist are created. For the input terminal to which the input delay time used in the present invention is added, only the terminal name is reflected in the net list. To the delay information of each input terminal (S
6).

As described above, by using the timing study method of designing a semiconductor integrated circuit by adding a delay time to an input terminal according to the present invention, an optimum input delay time can be set for each input terminal when designing a circuit diagram. It is possible to add the optimum input delay time to the test pattern without having to change the netlist used in the manufacture of the semiconductor integrated circuit. Also, by using the delay information changing unit 33 of FIG. 3 to add delay times to the respective input terminals in the circuit at equal intervals and execute a logic simulation, each of the input signals to the semiconductor integrated circuit to be designed is obtained. When the delay time between signals is unknown, it is possible to verify in advance the timing error due to the skew of the input signal occurring in the semiconductor integrated circuit, and it is possible to increase the reliability for the normal operation of the semiconductor integrated circuit.

[0016]

As described above, according to the present invention, input delay time information is added to an input terminal when designing a semiconductor integrated circuit, and the operation can be confirmed by logic simulation.
Since the input delay time information after confirmation can be added to the test pattern, the netlist and test pattern used for manufacturing the semiconductor integrated circuit can be created without changing the netlist at all. There is an effect that can be done. Further, when confirming the operation by the logic simulation, the delay time between each input signal can be set without changing the test pattern, so that the timing error caused by the shift of the input signal in the semiconductor integrated circuit can be verified in advance. effective.

[Brief description of the drawings]

FIG. 1 is a flowchart of one embodiment of the present invention.

FIG. 2 is a diagram showing an example in which input delay information is added to input terminal symbols in the flow shown in FIG.

FIG. 3 is a diagram showing a configuration of a verification device according to the present invention along a flow for adding input delay information.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Input terminal name 3 Delay time of each terminal 4 Internal circuit of semiconductor integrated circuit

Claims (4)

(57) [Claims] 1. The semiconductor integrated circuit according to claim 1, wherein time difference information of a signal input to each input terminal of the semiconductor integrated circuit to be designed is set in correspondence with each of said input terminals of circuit connection information of said semiconductor integrated circuit. Operation test pattern and
A timing verification method, wherein a logic simulation is performed using circuit connection information having the time difference information set in correspondence with the input terminal to perform timing verification of the semiconductor integrated circuit. 2. The method of claim 1] depending on the timing verification method according to claim 1, wherein
Test pattern generation method, wherein the after confirming completion of the normal operation of the semiconductor integrated circuit to be designed, reset the time difference information to the test pattern Te. 3. A storage means for storing time difference information of a signal input to each input terminal of a semiconductor integrated circuit to be designed, means for changing the time difference information, and each input of the semiconductor integrated circuit to be designed. The time difference information of the signal input to the terminal is input to each of the circuit connection information of the semiconductor integrated circuit.
Means for setting corresponding to the input terminal, test pattern creating means for creating a test pattern for confirming the operation of the semiconductor integrated circuit, and pairing the test pattern with the input terminal.
A logic simulation means for performing a logic simulation using the circuit connection information having the time difference information set in response thereto and performing timing verification of the semiconductor integrated circuit. 4. A means for resetting the time difference information to the test pattern after confirming normal operation of the semiconductor integrated circuit to be designed by the timing verification device according to claim 3. Timing verification device.