JP2845978B2 - Logic circuit simulation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation used for logic verification of a processing device, and particularly to a logic simulation of a clock synchronous system for performing a high-speed simulation with an element delay being zero. The present invention relates to a method for handling a delay time of an element.

[Conventional technology]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit design technique, logic verification for confirming the quality of a logic circuit has been important. In particular, with the increase in the degree of integration, a verification method using a computer has been adopted. I have. In such a logic circuit verification method using a computer, a logic verification CAD (Computer Aided Design) that is most often used is a logic simulation.

The inputs of the logic simulation are a description of an integrated circuit to be designed in a design language and simulation execution control data, and as a result, a time chart showing the operation is output.

Then, the logic of the logic circuit is verified by checking the contents of the time chart.

The most frequently used logic simulation is a gate-level logic simulation, in which a connection list including gate elements such as AND, OR, and memory elements such as flip-flops, ROM, and RAM as inputs is input.

In addition, switch level simulation is used for MOS circuit design, and function level simulation is used for FD.
When a higher-level design language such as L is used, mixed simulation is further used as an effective verification means of a hierarchical design accompanying the progress of VLSI.

In these logic verifications, mere confirmation of a logical operation is not sufficient, and confirmation of a timing problem is also important. The timing problem refers to a logical malfunction or a design constraint violation caused by an operation delay of a component of the logic integrated circuit. For this verification, an accurate definition of delay is assumed. In general, for each component, a maximum, minimum, or average delay time is defined for the rise and fall of the signal at the output, and a wiring delay is defined at the input side. As a means of verification, a logic simulation considering delay is often used. However, a logic path in a logic integrated circuit and its delay are obtained, and verification is performed by comparing a delay of a clock and control path with a delay of a data path system. There is also a path analysis method. This path analysis method has an advantage of less omission in verification as compared with a method based on logic simulation, but has a disadvantage of outputting many pseudo errors.

The explanation of the above logic simulation is described in 2.3.
2 Based on CAD for logic verification.

Furthermore, in order to cope with an increase in TAT (turn around time) accompanying an increase in circuit scale, there is a method of realizing a higher-speed logic simulation execution, in which element delay is treated as zero.

In this kind of logic simulation, in a simulation of a common element of a plurality of stages, a means for collecting delay values of a common element of a plurality of stages and adding the delay value to an element of a subsequent stage to make the delay value of a preceding element zero. It was done.

This method is described in IEE, Design and Test, April (1987) pp. 46-54 (IEEE, DESIGN
& TEST, April, 1987, pp. 46-54).

Means for realizing the simulation with the delay value of the element set to zero include the 25th ACM / IEE, Design Automation Conference pp.218-224 (25th., ACM / IEEE, DESIGN
AUTOMATION CONFERENCE pp.218-224).

[Problems to be solved by the invention]

Logic simulation for verifying the logic of a logic circuit
In order to improve the processing speed of the silicic acid machine, the simulation of the clock synchronous method which treats the element delay as zero has become mainstream.

However, in the conventional logic simulation that treats element delay as zero, signal delay due to a cable (wiring) that physically connects printed circuit boards is not taken into consideration, and a basic element (AND) existing between flip-flops is not considered. , OR, Exclusive OR) consideration when the gate delay time of the signal transmission source flip-flop and the signal reception destination flip-flop is larger than the operation time of the flip-flop, that is, the interval width of the clock signal for operating each flip-flop. Was not done.

Therefore, signal propagation delay due to cable (wiring),
The signal propagation delay time by the combination logic of the basic elements is
If the clock signal interval width of the flip-flop is larger than the actual logical basic operation in the operation of each flip-flop, different from the logical operation in the logical simulation, inconsistency occurs, and the operation check is extremely performed. It was a situation that could not be done.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems of the prior art, and to realize a clock synchronous type which does not contradict the logic operation of each flip-flop even when the signal propagation time between the flip-flops is larger than the clock signal interval. An object of the present invention is to provide a logic circuit simulation method for realizing a zero delay simulation and improving the processing efficiency of the logic simulation.

[Means for solving the problem]

In order to achieve the above object, a logic circuit simulation method according to the present invention provides a flip-flop in a zero-delay clock synchronization simulation in which a logic simulation is performed in synchronization with a clock signal of a flip-flop input terminal of a logic circuit model by setting an element delay to zero. The delay time of each element of the combinational logic circuit between them and the delay time due to the wiring between the elements are sequentially added, and when the sum of the delay times is larger than the clock interval between flip-flops, A virtual delay element is inserted into a signal line connected to an output terminal of the element, and signal propagation is transmitted by the number of clocks corresponding to the delay time of the element and wiring of the combinational logic circuit to perform simulation.

[Action]

In the present invention, in the zero-delay clock synchronization simulation, first, an output signal value is calculated from a signal value of an input terminal of the flip-flop in synchronization with a clock signal for operating each flip-flop. Then, the combinational logic (AND, OR, Exclusive) connected to the output terminal
For each element of (OR), the output signal value up to the flip-flop input terminal of the next stage is sequentially calculated without advancing the time.

Next, for a signal selection having a delay value exceeding the operation clock interval of the flip-flop, a specific element for delaying signal propagation processing (hereinafter referred to as a virtual delay element (SDLY)) is provided, and the newly provided virtual delay element (SDLY) is provided. When a signal value propagates to the input terminal of SDLY), the signal value is temporarily stored. The signal value temporarily stored at a time delayed by the number of clocks of the virtual delay element (SDLY) from the time at which the signal value change occurs is propagated to the subsequent stage, and the element that needs to calculate the output value at that time When the time has disappeared, the time is advanced by one clock, and the next clock signal is started.

This allows the signal change of the signal line in which the SDLY is inserted to be propagated to the input terminal of the flip-flop at the subsequent stage when the clock is started with the delay value delayed by the delay value, thereby preventing inconsistency with the operation of the flip-flop by logic simulation.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a logic circuit to be subjected to a logic simulation according to the present invention.

It comprises five flip-flops 101, 102, 105, 106, 107 and two AND circuits 103, 104, and a virtual delay element (SDLY) 108 is provided on the output line of the AND 104.

The flip-flop 101 and the flip-flop 102 operate with a clock (C0), and the flip-flop 105, the flip-flop 106, and the flip-flop 107 operate with a clock (C1).

The flip-flop 101 outputs F1 based on the input (I1). The AND circuit 103 receives F1 as input and outputs F1D to the flip-flop 105, and the flip-flop 105 receives F1D as input and outputs O1. Also, the output F1D of the AND circuit 103
Is also input to the AND circuit 104.

The flip-flop 102 outputs F2 based on the input (I2). The output F2 is sent to the flip-flop 107 and becomes the output O3, while the output F1D of the AND circuit 103 is output.
Is input to the AND circuit 104, and the AND circuit 104 outputs F12. The output F12 is input to the flip-flop 106 after a necessary cycle delay by the virtual delay element (SDLY) 108. Then, flip-flop 106 outputs signal O2.

FIG. 2 is a timing chart showing the actual physical operation timing of each signal in the logic circuit shown in FIG. 1, and shows an element AND circuit 103 and an AND circuit 104 between flip-flops.
Are assumed to be 10, 20 respectively. The clock (C0) and clock (C1) at this time
Is 20.

Now, the signal change of the flip-flop 101 (from I1 to F
Is transmitted to F12 after 30 due to the delay value (10) of the AND circuit 103 and the delay value (20) of the AND circuit 104. Therefore, at the rising edge () of the clock (C1) 20 after the clock (C2), the clock (C1) cannot be taken into the flip-flop 106 and is shifted by one cycle. That is, at the second rising edge () of the clock (C1), the flip-flop 106
And the flip-flop 106 outputs O2.

However, in a zero-delay synchronization simulation in which the calculation is performed at high speed by regarding the delay values of the AND circuits 103 and 104 as 0 (zero), the value of the signal F1 is propagated to F12, and thus the first clock (C1) is started. () Will be captured.

However, in FIG. 1, since the virtual delay element (SDLY) is inserted on the signal line of the signal (F12), the above contradiction does not occur.

That is, in a zero-delay clock synchronization simulation in which a logic simulation is performed with the element delay set to zero, a virtual delay element (SD) that delays a signal propagation element with respect to a signal line having a delay value exceeding a clock interval.
LY) is inserted, and when the signal value of the input terminal of the virtual delay element (SDLY) changes during simulation execution, the signal is propagated to the output terminal by delaying by the number of clocks corresponding to the delay value. . Further, for the signal delay time generated in the cable connecting the boards, the delay time is provided on a netlist indicating the connection between the elements, and when the corresponding delay time is larger than the clock interval, the signal delay By inserting a virtual delay element (SDLY) and delaying signal propagation by the number of clocks corresponding to the delay time, inconsistency does not occur between the flip-flop operation by the logic simulation and the physical flip-flop operation.

FIG. 3 is a developed view of a net list representing connections between elements in the logic circuit of FIG.

The list 301 is a list of the input signals I1 and is associated with the list 3101 of the signal pointer (SP) flip-flop 101. When a signal change occurs in the input signal I1, the list 3101 indicated by the signal pointer (SP) is activated. At the time of processing the list 3101, the signal value of the list indicated by the fine pointer (FIO) of the list to be the input signal is changed. Read and calculate output value based on element function.

A list 302 shows a list of clock signals. There are two types of clocks, one of which is a clock signal.
C0 has an interval of another clock signal C1 and 20, and is associated with the list 3101 of the flip-flop 101 and the list 3106 of the flip-flop 106 by the signal pointer (SP) of each clock signal.

The list 303 is a list of the signal F1, and its signal pointer (SP) indicates the position of the fan-out section (FOP) of the flip-flop 3101. When the signal value of the list 3101 changes, the signal value is read. Used as a key for

A list 3101 is a list of the flip-flops 101 and has a function and a value of an element. Fan-in pointer (FI
From the list of areas indicated by P), a value is calculated from the value of the input signal I1 and the value of the clock terminal C0 according to the function of the element, and after calculating the value, the list 3103 indicated by the fan-out pointer (FOP) is: This is a list of the AND circuit 103, which has the function and value of the element as well as the list 3010, and the delay value.
Have ten. A value is calculated based on the event from Listing 3101, and a list 310 indicated by a fan-out pointer (FOP)
4 and an event is generated to the list 3105 of the flip-flop 105.

The list 3104 is a list of the AND circuits 104, and is similar to the list 3103, and has a delay value of 20. Events from Listing 3103 and Listing 3 of flip-flops 102 not shown
A value is calculated based on the event from 102, and an event is generated in the list 3106 of the flip-flop 106 indicated by the fan-out pointer (FOP).

A list 3106 is a list of the flip-flops 106. A value is calculated from the event from the list 3104 and the value of the clock terminal C0 of the list 302 in accordance with the function of the element. Pass to the list 304 shown.

The list 304 is a list of the signal O2, and the signal pointer (SP) is the list 3106 of the flip-flop 106.
Indicates the position of the fan-out section (FOP), and is used as a key for reading the signal value when the signal value in the list 3106 changes.

FIG. 4 is a netlist showing that a list 401 of virtual delay elements (SDLY) 108 has been added to the net risk of FIG. This shows that the list 401 of the virtual delay element (SDLY) 108 is added between the list 3104 and the list 3106. That is, the signal F12, which has been sent from the AND circuit 104 to the flip-flop 106 directly at the timing of zero delay, is now sent via the virtual delay element (SDLY) 108.

FIG. 5 shows a delay table, in which a virtual delay element (SDL
Y) is a table for processing. List 501 NO.
Corresponds to the number of the virtual delay element (SDLY) in FIG. 4, and transfers the input signal value to the list 502. In the list 501 of the delay table, NO. And the pointer are repeated. The signal change generated for the same virtual delay element (SDLY) is linked and registered from the list 502 by the next pointer (NP), and is disconnected when the delay time is reached,
Virtual delay element (SDLY) with the same number on the netlist
An event is generated for the list connected to the fan-out pointer (FOP), that is, the list 3106.

FIG. 6 is an event table of an element having a virtual delay element (SDLY) and having a signal propagation time equal to or longer than a clock interval.

The connection destination, signal propagation delay time and signal value are registered,
Based on this table, an appropriately delayed operation timing is obtained.

FIG. 7 is a flowchart showing the execution operation of the logic simulation according to the present invention.

The logic circuit shown in FIG. 1 is simulated without causing inconsistency with the operation of a physical flip-flop.

First, the connection information of the logic circuit shown in FIG.
The function of each logic element is developed so that it can be processed as a Boolean algebra, and a netlist shown in FIG. 3 is created (step 701).

Next, a list of clock signals is created in advance as shown in 302 in FIG. 3 from the contents designated by parameters or the like as input data for simulation as input data, and the simulation time is set to an initial set, for example, 0.
Is set (step 702).

After that, the maximum delay time of each element output signal line of the combinational logic circuit of elements such as AND and OR existing between each flip-flop is calculated, and when the delay time is longer than the clock interval specified by a parameter or the like. Then, a virtual delay element (SDLY) is inserted into the connection part of the netlist (step 703). FIG. 4 shows the state of a netlist as an example of inserting a virtual delay element (SDLY). A simulation is executed based on the netlist created in this way.

The execution process of the simulation is, first, of the signal change information specified in advance by a parameter or the like, for a signal whose time matches, or a signal change information whose time is smaller than the simulation time and the signal input process has not been performed yet. Then, a signal value is set for the netlist corresponding to the specified content (step 704). The signal propagation time at this time is set to 0.

After setting all input signal values below the simulation time, if a virtual delay element (SDLY) is connected to the netlist whose signal value has changed, if the signal propagation time for that net is greater than or equal to the clock interval If the fifth
The signal value and the delay time are registered for the corresponding SDLY number (NO.) In the delay table in FIG.
5, 706, 708).

When the virtual delay element (SDLY) is not connected, and when the signal propagation time is smaller than the clock interval even if it is connected, the output value of the element connected to the netlist is changed to the input signal line of each element. Calculated from the signal value, and when the output value changes, the delay time of the element is added to the delay time of each input signal line and propagated to the subsequent element as an event (step 707).

The propagation of the signal line is shown in the event table shown in FIG.
Event (1) 601 or event (2) 6
02, and in step 709, when an unprocessed event exists in any of the event tables, the output event table and the input event table are switched.
For the element of the address indicated by the FOP of the element registered in the input event table in step 704, the output value is calculated by giving the signal value, and when the output value changes,
The address FOP of the element to which the output value should propagate and the signal value,
Further, a set of the delay time of the calculated element is registered in the output event table with the delay time of the input event table.

After calculating all signal changes within the same simulation time by repeating steps 704 to 709, a clock signal that matches the simulation time is activated (step 710), and the output value of the flip-flop connected to the activated clock (Step 71
1).

After the output calculations of all flip-flops connected to the clock are completed, the delay time of each SDLY registered in the delay table shown in FIG. 5 is extracted, and the signal values corresponding to those below the simulation time are corresponded. The output value of the SDLY is propagated to the destination (step 712).

After carrying out signal transfer for all SDLYs, the time obtained by adding the clock interval to the simulation time is registered as a new simulation time (step 713),
The processing from step 704 is repeated until the time reaches the simulation end time given in advance by parameters or the like (step 714). When the simulation end time comes, the simulation result is output to a list or the like, and the simulation ends (step 71).
Five).

Thus, according to the present embodiment, the signal in FIG.
Since the delay element is inserted on the signal line of F12, the above contradiction does not occur.

Also, regarding a cable or the like existing between boards, a physical operation is realized by simulation by inserting a delay time according to the length of the cable into the netlist.

As described above, according to the present embodiment, even when the signal propagation time between the flip-flops is greater than the clock signal interval, a logic simulation is performed with zero element delay that does not contradict the logic operation of each flip-flop. Thus, the signal propagation delay of the combinational logic can be handled by a clock-synchronized zero-delay simulation.

Then, in a circuit having a delay time equal to or longer than the clock interval, simulation can be performed in synchronization with the delay time of each logic element divided by the clock, so that a signal change that occurs every minimum unit of the gate delay time, for example, every 1 ns, When calculating, the number of processing steps when it is necessary to update the simulation time in 1 ns unit only needs to calculate the signal change within the same clock, and the processing time can be greatly reduced. In addition, wiring delays, cable delays, and the like can be easily handled in the zero delay clock synchronization simulation.

〔The invention's effect〕

According to the present invention, even when the signal propagation time between the flip-flops is larger than the clock signal interval, a clock-synchronous zero-delay simulation that does not contradict the logic operation of each flip-flop can be realized. Processing efficiency can be improved.

[Brief description of the drawings]

1 shows an embodiment of the present invention, FIG. 1 is a circuit diagram showing a logic circuit to be subjected to a logic simulation according to the present invention, and FIG. 2 is an actual operation timing of each signal of the logic circuit in FIG. FIG. 3 is a development view of a net list showing connections between respective elements of the logic circuit in FIG. 1, and FIG. 4 shows that a virtual delay element (SDLY) is added to the net list in FIG. FIG. 5 is a virtual delay element (SD) shown in FIG.
LY), a development view showing a delay table for processing
FIG. 7 is a development view showing an event table of an element having a virtual delay element (SDLY) and having a signal propagation time equal to or longer than a clock interval. FIG. 7 is a flowchart showing an operation of a logic simulation according to the present invention. 101, 102: flip-flop, 103, 104: AND circuit, 105-107:
Flip-flop, 108: virtual delay element (SDLY), 301: list of input signals I1, 302: list of clock signals, 303: list of signal F1, 304: list of signal O2, 401: virtual delay element (SDLY) List, 501-503: delay table list, 60
1: Event table (1), 602: Event table (2), 3101: Flip-flop (101) list, 3103: A
List of ND circuits (103), 3104: List of AND circuits (104),
3105: list of flip-flops (105), 3106: list of flip-flops (106).

Claims (1)

(57) [Claims] In a zero-delay clock synchronization simulation for performing a logic simulation in synchronism with a clock signal at a flip-flop input terminal of a logic circuit model, an element delay is set to zero. A signal line connected to an output terminal of an element of the combinational logic circuit when the delay time of each element and the delay time due to wiring between the elements are sequentially added, and when the total of the delay times is larger than the clock interval between the flip-flops. A logic circuit simulation method, wherein a virtual delay element is inserted into the logic circuit and the simulation is performed by delaying signal propagation by the number of clocks corresponding to the delay time due to the element and wiring of the combinational logic circuit.