JP2953384B2 - Clock tree forming method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout of a semiconductor integrated circuit, and more particularly, to a method of arranging and routing clock signal distribution portions of an LSI.

[0002]

2. Description of the Related Art In a conventional layout method using CAD of an LSI, in a placement and routing process, a delay is calculated based on delay values of elements and wiring registered in a CAD library, and a buffer is inserted into a circuit. The overall delay was adjusted by adjusting the wiring length.

FIG. 5 shows a conventional LS for comparison with the present invention.
FIG. 10 is a circuit diagram showing a first application example of the clock tree forming method designed by the layout method of I, and reference numeral 50 in the figure.
Reference numerals 1, 502, 503, and 504 denote buffers forming clock trees, 505, 506, 507, 508, and 50, respectively.
9, 510 are flip-flops, 511, 512, 51
3 is a combination circuit.

[0004] 511 is a circuit between 505 and 506, 512 is a circuit between 507 and 508, and 513 is a circuit between 509 and 510. It is assumed that the connection between 506 and 507 and the connection between 508 and 509 are made only by wiring. At this time,
The delay by 511, 512 and 513 is large enough to satisfy the hold time constraint between each flip-flop, and small enough to satisfy the setup time from the relation of the clock cycle. For flip-flops connected only by wiring, it is assumed that the flip-flops are small enough to satisfy the setup time due to the relationship between clock cycles. At this time, a problem in forming the clock tree is a restriction on a hold time between flip-flops connected only by wiring.

FIG. 6 shows a conventional LS for comparison with the present invention.
FIG. 15 is a circuit diagram showing a second application example of the clock tree forming method designed by the layout method I, and reference numeral 60 in the figure.
1, 604, 605, 606, 607 are buffers forming a clock tree, and 602, 603 are clock trees.
AND gates 608, 609, 610, 6
11, 612, 613, 614, 615 are flip-flops, 616 is a buffer with a small delay, 617, 61
8, 619 are combinational circuits.

At this time, the delay by 617, 618, and 619 is large enough to satisfy the hold time constraint between the flip-flops, and small enough to satisfy the setup time due to the relationship between clock cycles. For flip-flops connected only by wiring, it is assumed that the flip-flops are small enough to satisfy the setup time due to the relationship between clock cycles. It is also assumed that the buffer 616 is small enough to satisfy the setup time for the flip-flop connected via the buffer due to the relationship of the clock cycle.

[0007]

In a conventional delay adjustment method used for synthesizing a clock tree, which is a whole path for distributing a clock signal to flip-flops, a CA is used.
Estimate the delay using the delay value or the delay parameter value based on the data of the library D, and from the output terminal of the clock driver that is the source of the clock signal,
The adjustment is made so that the delay difference, that is, the clock skew, to the clock input terminal of each flip-flop becomes small. However, the actual delay varies due to various conditions in manufacturing an LSI. In consideration of this variation, if the adjustment is made based solely on the values of the library, the deviation of the delay will be larger than the calculation at the time of the layout at the part where the variation is physically large, and the clock scan cannot be ignored for the calculated value. May be you.

Since this variation cannot be generally considered in a layout CAD, it is treated as a margin with respect to the layout CAD. Therefore,
This margin cannot be adjusted by layout CAD, and by taking this margin into account uniformly, it is necessary to consider a margin more than necessary even in a circuit portion where physical variation is small, and as a result, the accuracy of clock skew adjustment And imposes unnecessary restrictions on circuit design.

As an example, in the first application example of the conventional clock tree forming method shown in FIG. 5, the delay that cannot be adjusted when forming the clock tree includes the entire delay including the physical delay variation. It must be processed as an indeterminate value. That is, it is necessary to consider it as a margin. In this case, 501, 502, 503, and 504 are buffers constituting a clock tree. At this time, 502,
The uncertainty values of the delays before 503 and 504 and 501
It is necessary to adjust the skew in consideration of the uncertainty value uniformly without distinction of the uncertainty value of the delay that exists. For this reason, it may be difficult to adjust the skew. As a result, the delay constraint is not satisfied between flip-flops connected only by wiring, ie, between 506 and 507, and between 508 and 509, and the circuit is not re-established. It may be necessary to change the configuration and perform clock tree formation. For example, in this circuit, if the flip-flops are connected by wiring, it may be necessary to insert a buffer or the like between the flip-flops and add a delay between the flip-flops.

Also, in the second application example of the conventional clock tree forming method shown in FIG. 6, the delay which cannot be adjusted when forming the clock tree is an uncertain value as a whole, including physical delay variations. Need to be processed as That is, it is necessary to consider it as a margin. In this case, 6
04, 605, 606, and 607, the uncertainty value of the delay ahead of 602, 603, and the uncertainty value of the delay ahead of 601 are not particularly distinguished. It is necessary to adjust the skew in consideration of the uncertain value. For this reason, skew adjustment may be difficult. As a result, between flip-flops connected only by wiring, that is, between flip-flops 609 and 610, between flip-flops 612 and 613, and between flip-flops 611 and 612 connected only through a buffer having a small delay,
In some cases, the delay constraint is not satisfied, and the circuit configuration must be changed again to form a clock tree. In this circuit, if the flip-flops are connected by wiring or connected only via a buffer having a small delay, a buffer or the like is inserted between them and a delay is added between the flip-flops. May need to be done.

An object of the present invention is to improve the accuracy of clock skew adjustment and impose unnecessarily high restrictions on circuit design without considering unnecessary margins for circuit portions with small physical variations. It is an object of the present invention to provide a method for forming a clock tree of a semiconductor integrated circuit without any problem.

[0012]

A clock tree forming method for a semiconductor integrated circuit according to the present invention is a method for forming a clock tree for a semiconductor integrated circuit using CAD, wherein a delay corresponding to the form of elements and wiring forming the clock circuit is provided. Is registered for each connection method .

[0013] For all pairs of flip-flops with a connection to each other physician analyzes the maximum delay amount and the minimum delay amount, with respect to all the pairs, the most common physical variation of the delay which is registered for each connection method From the connection method to the least connection method, verify whether the delay considering the physical fluctuation amount satisfies the constraint of the hold time and the setup time of the flip-flop, and is applicable to the pair. By registering the connection method with the largest amount of physical fluctuation, and grouping all flip-flops using the connection method registered for each pair to form a clock tree, the physical fluctuation amount can be reduced from the parts with severe timing constraints. less connection method of preferentially use.

Further, the method of connecting the clock input of the pair of scan-connected flip-flops via a different buffer is referred to as method 1, and the clock input of the pair of scan-connected flip-flops is wired without passing through the buffer. A method of connecting only by using only the method 2 is registered as the method 2, and the method 2 is preferentially used as a connection method with a small amount of physical fluctuation from a part with strict timing restrictions, and clock inputs of a pair of flip-flops connected by scan are different. The method of inserting and connecting a buffer with a multi-input logic gate is referred to as method 1, the method of connecting the clock inputs of a pair of scan-connected flip-flops via different buffers is referred to as method 2, and the scan-connected flip-flops are referred to as method 2. The clock input of a pair of Register the method of connection as scheme 3, a small connection method most physical variation of scheme 3,
The method 2 is used next as the connection method with the least amount of physical fluctuation, with priority given to parts with strict timing constraints.

The clock tree generation method according to the present invention employs a CA
In the LSI circuit design by D, the physical fluctuation amount generated by various manufacturing conditions such as the form of the LSI element and the wiring is registered for each type. Has a mechanism to preferentially use the data, so that it is not necessary to consider a margin more than necessary in forming the clock tree.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of the circuit design processing according to the first embodiment of this invention. S10
1 to S113 indicate steps of each processing.

When the circuit design is started (S101), first, a delay which can be guaranteed by a program for reducing clock skew, such as a clock tree synthesis technique, which is a technique for arranging and wiring so as to reduce clock skew in a layout, is described. The range, that is, the delay that can be adjusted by software, and the variation in delay caused by physical manufacturing variation related to the manufacturing process and the like are added for each method of forming the clock tree, and this is added to each of the methods of forming the clock tree. It is determined as an uncertain delay for each method and registered in the library (S102). This process need not be performed for each process for each circuit if it is registered in advance in the library as an uncertain delay. In the flow of the first embodiment, processing when the method of forming a clock tree is classified into two methods is shown. Hereinafter, a method with a large delay variation is referred to as a method 1, and a method with a small delay is referred to as a method 2.

Next, the worst delay analysis between flip-flops is performed for the entire circuit. In this step, the worst delay is obtained for all pairs of flip-flops connected to each other. Here, the worst delay value indicates both the maximum delay and the minimum delay when various conditions are considered. The worst delay value is obtained by ignoring the delay difference up to the clock input of each flip-flop (S10).
3). Next, a determination process of the pair processing end of all the flip-flops is performed. If the processing of all the flip-flops is not completed, the flip-flop pairs are taken out one by one and the primary The process proceeds to constraint analysis S105, and if the process is completed for all flip-flops, the process proceeds to flip-flop grouping process S111 (S104).

Processing has not been completed, and 1
When the process proceeds to the next constraint analysis process S105, the worst delay between flip-flops obtained in S103 is compared with the method 1
Analyze constraints considering the uncertain delay value of. In other words, for the minimum delay, the uncertain delay value of the method 1 is subtracted from the minimum delay, and it is verified whether or not the value satisfies the constraint of the hold time of the flip-flop on the data receiving side. On the other hand, the uncertain delay value of the method 1 is added to the maximum delay, and it is verified whether or not the clock cycle and the setup time of the flip-flop receiving the data are satisfied (S105).

A determination is made as to whether or not the processing result satisfies the primary constraint. If the processing result satisfies the restriction, no special processing is performed, and the flow returns to the determination processing S104. Is not completed, the same processing is repeated for the next pair of flip-flops. If the verification result of the primary constraint is not satisfied, the process proceeds to analysis of the secondary constraint between the next flip-flops S107 (S106).

In the secondary constraint analysis between flip-flops, the constraint is analyzed with respect to the worst delay between flip-flops obtained in S103, taking into account the uncertain delay value of method 2. In other words, for the minimum delay, the uncertain delay value of the method 2 is subtracted from the minimum delay, and it is verified whether or not the value satisfies the constraint of the hold time of the flip-flop receiving the data. On the other hand, the indeterminate delay value of the method 2 is added to the maximum delay, and it is verified whether or not the clock cycle and the setup time of the flip-flop on the data receiving side are satisfied (S107).

A determination is made as to whether or not the processing result satisfies the secondary constraint. If the processing result satisfies the restriction, the process proceeds to flip-flop pair registration processing S110.
Register a pair of flip-flops. If the verification result of the secondary constraint is not satisfied, it means that the delay constraint is not satisfied even if the best clock tree formation method is used, and therefore, the process proceeds to the circuit delay readjustment processing S109 (S108). ).

After the circuit delay readjustment processing S109 is performed, the worst delay analysis S103 between flip-flops is performed.
And the process is repeated again. Here, when processing is performed on the circuit whose delay has been adjusted in consideration of the uncertain delay for the method 2 in advance, it is assumed that the circuit is generated so as to satisfy the quadratic constraint in S106. For those determined not to satisfy the primary constraint in the determination of, the processing of S107, S108, and S109 is unnecessary, and
Immediately, a flip-flop pair registration process S110
(S109).

After the registration processing of the flip-flop pairs, the process returns to step S104 to determine whether or not the processing of all the flip-flop pairs has been completed (S110). If the processing of all the flip-flop pairs is not completed, the processing is continued for the next flip-flop pair. When all flip-flop pairs have been processed,
The process proceeds to flip-flop grouping processing S111.

In the flip-flop grouping process,
Since the flip-flop pair is registered by the registration process of S110, first, one pair of flip-flops is set as a group. The groups are combined, that is, all flip-flops included in the two groups form a new group. This process is performed on the group formed by all the flip-flop pairs at the beginning. In this process, groups that have not been combined with each other ultimately remain as independent groups (S111).

Flip-flop grouping processing S11
After 1 is completed, the flow shifts to clock tree generation processing S112. In the clock tree generation process, a clock tree is formed using the method 2 for flip-flops included in the same group and the method 1 for the others in the groups grouped in S111 ( S1
12), and end (S113).

FIG. 2 shows L according to the first embodiment of the present invention.
FIG. 9 is a circuit diagram showing an application example of a clock tree forming method designed by an SI layout method.
02, 203 and 204 are buffers forming a clock tree, 205, 206, 207, 208, 209 and 21
0 is a flip-flop, and 211, 212, and 213 are combinational circuits. This figure corresponds to the first application example of the related art shown in FIG. 5, and the same reference numerals in the last two digits correspond to each other.

As described above, in the first application example of the conventional clock tree forming method shown in FIG. 5, the delay that cannot be adjusted when forming the clock tree includes the entire delay including the physical delay variation. Must be processed as an uncertain value. That is, it is necessary to consider it as a margin.
In this case, 501, 502, 503, and 504 are buffers constituting a clock tree. At this time, 50
The uncertainty values of the delays ahead of 2, 503 and 504 and 5
It is necessary to adjust the skew in consideration of the uncertainty value uniformly without distinguishing the uncertainty value of the delay from 01 in particular. For this reason, it may be difficult to adjust the skew. As a result, the delay constraint is not satisfied between flip-flops connected only by wiring, that is, between 506 and 507, and between 508 and 509, and the circuit is not re-established. It may be necessary to change the configuration and perform clock tree formation. For example, in this circuit, if the flip-flops are connected by wiring, it may be necessary to insert a buffer or the like between the flip-flops and add a delay between the flip-flops.

On the other hand, the clock tree forming method of the present invention shown in FIG.
Considering the variation of the physical delay, the method is divided into a plurality of schemes, and a scheme with less variation is adopted between flip-flops with severe restrictions. In this example, a clock connection between a pair of flip-flops that are scan-path connected to each other (when the output of one flip-flop and the scan input of another flip-flop are connected, it is assumed that they are scan-connected). The method of connecting the clock input of the flip-flop via a buffer (there is a portion using a different buffer from the original clock) is the method 1, the wiring is not provided between the clock input of the flip-flop and only the wiring Are connected as the second clock (all are connected by the same buffer from the original clock).

Here, the delay constraint which becomes a problem in this circuit is the hold time of the flip-flop, and the circuit portion which becomes a problem is a portion where only the wiring is connected between the flip-flops, that is, in FIG. 20
6 and 207 and flip-flops 208 and 209
In FIG. 5, flip-flops 506 and 507 are used.
And between flip-flops 508 and 509. According to the conventional scheme, flip-flops 506 and 507 and flip-flop 508 as shown in FIG.
And 509 are connected to clock circuits via different buffers. In the clock tree forming method of the present invention shown in FIG. 2, the flip-flops 206 and 20 are directly wired between the flip-flops.
7 and the clock input to the flip-flops 208 and 209, the clock circuit via the same buffer, that is, scheme 2 is adopted. As described above, the method 2 is preferentially applied to the part where the delay restriction is a problem, and the method 1 is employed to the other parts. This allows
It is not necessary to consider a margin more than necessary, and unnecessary delay adjustment becomes unnecessary.

FIG. 3 is a flowchart of a circuit design process according to the second embodiment of the present invention. S301 to S314 show the steps of each processing. In the present embodiment, it is assumed that each uncertain delay for each clock tree formation method is registered in the library in advance. Also, this flow shows the processing when the clock tree formation method is classified into n according to the magnitude of delay variation. Hereinafter, in order from the method with the largest delay variation,
Methods 1 and 2 are used, and a method having the minimum delay variation is referred to as a method n. Now, when k is an integer of 1 or more and n or less, the k-th order constraint is a delay constraint that must be satisfied when the variation of the method k is considered, and the k-th order group satisfies the k-th order constraint. , A set of flip-flop pairs. However, in this grouping, the smallest constraint k that satisfies is taken and called a k-th group.

When the process is started (S301), first, a worst-case delay analysis between flip-flops is performed over the entire circuit, thereby obtaining the worst-case delay for all pairs of flip-flops connected to each other. Here, the worst delay value indicates both the maximum delay and the minimum delay when various conditions are considered. The worst delay value is obtained by ignoring the delay difference up to the clock input of each flip-flop (S302).

Next, assuming that k = 0, an initial value of k is determined (S303). Then, in the next step, k is incremented (S304). Next, it is determined whether or not k is equal to or less than n. If k is greater than n, the process proceeds to flip-flop grouping processing S312. If k is equal to or less than n, it is determined whether or not processing of all flip-flop pairs has been completed S30
6 (S305). When it is determined whether the processing of all the flip-flop pairs has been completed, if there are unverified flip-flop pairs, the flip-flop pairs are taken out one by one, and the k-th order constraint analysis processing S307 between the flip-flops is performed. Move to If the processing is completed for all flip-flops, it is determined that the processing has been completed, and S304 is performed.
(S306). In S304, k is incremented, and the same processing as the previous time is repeated.

In step S306, there is an unverified pair of flip-flops, and a k-th order constraint analysis process between the flip-flops is performed.
When the process proceeds to step 307, a constraint analysis is performed on the worst delay between flip-flops obtained in step S302, in consideration of the uncertain delay value of the method k. In other words, for the minimum delay, the uncertain delay value of the method k is subtracted from the minimum delay, and it is verified whether or not the value satisfies the constraint of the hold time of the flip-flop receiving the data. , The uncertain delay value of the method k is added to the maximum delay, and it is verified whether or not the clock cycle and the setup time of the flip-flop on the data receiving side are satisfied (S307).

In this processing result, in the judgment S308 as to whether or not the k-th order constraint is satisfied, a pair of flip-flops is registered as a k-th order group if the constraint is satisfied. However, if the pair has already been registered in the past, that is, if it has been registered in a group of order k-1 or less, it is not registered. After the processing S310, it is determined whether the processing of all the flip-flop pairs is completed S3.
The process moves to 06 (S310).

In the determination of whether or not the k-th order constraint is satisfied, if the k-th order constraint is not satisfied in S 308, the process proceeds to S 309.
When k = n, it means that adjustment was impossible even if the best delay variation method was used, so the flow proceeds to delay readjustment processing S311. The process returns to step S306 to determine whether the processing of all the flip-flop pairs is completed, and repeats the processing (S30).
9). In the delay readjustment process S311, the delay of the circuit is readjusted, and after the readjustment, the worst delay analysis S
The process returns to 302 and the process is repeated (S311).

If it is determined in step S306 that the processing of all the flip-flop pairs has been completed, if the processing between all the flip-flops has been completed, the processing proceeds to step S304.
Then, k is incremented, and processing for the next k is performed. In the determination in S305, if k exceeds n, that is, if the analysis for the delay constraint up to k = n has been completed between all the flip-flops,
A flip-flop grouping process S312 is performed.

Flip-flop grouping processing S31
In No. 2, since a pair of flip-flops is registered by the registration processing of S310, first, one pair of flip-flops is set as a group, and at least one of the groups is set.
For groups sharing one flip-flop, the two groups are combined, that is, a new group is formed by all flip-flops included in the two groups. This process is performed on the group formed by all the flip-flop pairs at the beginning. In this process, groups that have not been combined with each other remain as independent groups (S312).

Flip-flop grouping processing S31
After the completion of Step 2, the flow shifts to clock tree generation processing S313. In the clock tree generation processing S313, S31
A clock tree is formed between flip-flops included in the k-th order group by using a method of order k or more, with respect to those grouped by 0. here,
Since the primary group is a case where the worst is considered, no special processing is required (S313). When the clock tree is completed, the process ends (S314).

FIG. 4 shows L according to the second embodiment of the present invention.
FIG. 9 is a circuit diagram showing an application example of a clock tree forming method designed by an SI layout method.
Reference numerals 04, 405, 406, and 407 denote buffers for forming a clock tree, reference numerals 402 and 403 denote AND gates for forming a clock tree, and reference numerals 408, 409, 410, and 411.
412, 413, 414 and 415 are flip-flops,
416 is a buffer with a small delay, 417, 418, 41
9 is a combination circuit. This figure corresponds to the second application example of the related art shown in FIG. 6, and the same reference numerals in the last two digits correspond to each other.

As described above, in the second application example of the conventional clock tree forming method shown in FIG. 6, the delay which cannot be adjusted when forming the clock tree includes the entire delay including the physical delay variation. It must be processed as an indeterminate value. That is, it is necessary to consider it as a margin. In this case, there is no particular distinction between the uncertainty value of the delay ahead of 604, 605, 606, 607, the uncertainty value of the delay ahead of 602, 603, and the uncertainty value of the delay ahead of 601. It is necessary to adjust the skew in consideration of the uncertain value. For this reason, skew adjustment may be difficult. As a result, between flip-flops connected only by wiring, that is, between 609 and 610, and between 612 and 61
The delay constraint is not satisfied between the flip-flops 611 and 612 connected only between the three buffers and the buffer having a small delay, and the circuit configuration is changed again.
Clock tree formation may need to be performed. In this circuit, if the flip-flops are connected by wiring or connected only via a buffer having a small delay, a buffer or the like is inserted between them and a delay is added between the flip-flops. May need to be done.

On the other hand, in the clock tree forming method of the present invention shown in FIG. 4, the method of forming the clock tree is divided into a plurality of methods in consideration of the variation of the physical delay, and the method is restricted. For flip-flops with strict requirements, a method with less variation is adopted.

In this example, the method of forming a clock tree is divided into three stages, and a pair of flip-flops that are scan-path connected to each other (the output of one flip-flop and the scan input of another flip-flop are connected). In the case of a clock connection, scan connection is used), and a buffer is not connected between clock inputs of flip-flops, and only wiring is used (all clocks are connected by the same buffer from the original clock). Method 3 is a method in which the clock input of the flip-flop is connected by adjusting a buffer by inserting one stage (a part uses a different buffer from the original clock). Gates and buffers are inserted one by one (from the original clock, different AND gates and different buffers It is distinguished by being there is a portion) scheme used as a method 1.

The restriction of the hold time between flip-flops in which data input / output of flip-flops are connected only by wiring is limited only by the method 3, and the restriction on delay of a portion connected via a buffer having a small delay is determined by the method. It shall be satisfied if 2 or 3 is used.

Here, the delay constraint which becomes a problem in this circuit is the hold time of the flip-flop. The circuit portion which becomes a problem is a portion where the flip-flops are connected only by wiring, ie, flip-flops 409 and 41.
0, 412 and 413, and the parts connected only by buffers having a small delay, that is, flip-flops 411 and 412.

According to the conventional method, as shown in FIG. 6, clock circuits via the same buffer are connected to the clock inputs of the flip-flops 612 and 613, but different buffers are connected to the flip-flops 609 and 610. And a clock circuit via a different AND gate and a buffer is connected to the clock inputs of the flip-flops 611 and 612. On the other hand, in the clock tree forming method of the present invention shown in FIG. 4, the clock circuits which pass through the same buffer are all provided to the clock inputs of the flip-flops 409 and 410 and the flip-flops 412 and 413, which are directly wired between the flip-flops. Method 3 is connected, and flip-flops 411 and 412 have
A clock circuit having a common AND gate and passing through different buffers, that is, scheme 2 is connected.

According to the present invention, the method 3 is preferentially adopted for the part where the delay restriction is a problem, and only the buffer having a small difference is used for the direct wiring part. Method 2 or 3 is preferentially adopted for connected parts, and method 1 is used for other parts.
Is adopted. As a result, there is no need to consider a margin more than necessary, and unnecessary delay adjustment is unnecessary.

[0048]

As described above, according to the present invention, delay variations caused by physical manufacturing variations related to manufacturing processes and the like that differ depending on the form of elements and wirings are determined for each clock tree formation method. In addition, by changing the margin to be considered for each method, it is not necessary to consider an excessive margin for a portion with small physical variation, and there is little variation for a portion that is a problem of delay constraint. By applying the method, there is an effect that it is not necessary to impose unnecessary restrictions on circuit design.

[Brief description of the drawings]

FIG. 1 is a flowchart of a circuit design process according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an application example of a clock tree forming method designed by an LSI layout method according to the first embodiment of the present invention.

FIG. 3 is a flowchart of a circuit design process according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an application example of a clock tree forming method designed by an LSI layout method according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first application example of a clock tree forming method designed by a conventional LSI layout method for comparison with the present invention.

FIG. 6 is a circuit diagram showing a second application example of a clock tree forming method designed by a conventional LSI layout method for comparison with the present invention.

[Explanation of symbols]

201, 202, 203, 204, 401, 404, 4
05, 406, 407, 501, 502, 503, 50
4, 601 604 605 606 607 Buffers 205, 206, 207, 208, 209, 210, 4 forming a clock tree
08, 409, 410, 411, 412, 413, 41
4, 415, 505, 506, 507, 508, 50
9, 510, 608, 609, 610, 611, 61
2, 613, 614, 615 Flip-flops 211, 212, 213, 417, 418, 419, 5
11, 512, 513, 617, 618, 619 Combinational circuit 402, 403, 602, 603 AND gate 416, 616 forming a clock tree Buffer with small delay S101-S113, S301-S314

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/04 D (58) Investigated field (Int.Cl. ⁶ , DB name) G06F 17/50 G06F 1/10 H01L 21 / 82 H01L 21/822 H01L 27/04 JICST file (JOIS) Patent file (PATOLIS)

Claims (3)

(57) [Claims] In a method for forming a clock tree of a semiconductor integrated circuit using CAD, a physical variation of a delay corresponding to an element or a wiring form forming a clock circuit is registered for each connection method, and a connection is established. For every pair of flip-flops
Analyze the maximum delay amount and the minimum delay amount by using
The connection method with the largest physical variation of the delay
In the order of the smaller connection methods,
The considered delay is the hold time of the flip-flop.
Validate whether constraints of setup and setup time are satisfied
And the connection with the largest physical variation applicable to the pair
Register the connection method and use the connection method registered for each pair.
Grouping lops to form a clock tree
Thereby, from the strict part of the timing constraint, characterized by preferentially using the connection method with a small amount of physical variation,
A method for forming a clock tree of a semiconductor integrated circuit. 2. A method of connecting clock inputs of a pair of flip-flops connected in scan connection via different buffers is referred to as a method 1, wherein clock inputs of pairs of flip-flops connected in scan connection are wired without passing through a buffer. The semiconductor integrated circuit according to claim 1, wherein a method of connecting only by means of the method is registered as method 2, and method 2 is preferentially used as the connection method having a small amount of physical variation, from a part having strict timing constraints. Clock tree formation method. 3. A method in which a clock input of a pair of scan-connected flip-flops is connected by inserting a buffer with a different multi-input logic gate and a buffer, and a clock input of a pair of scan-connected flip-flops is used. The method of connecting via different buffers is called method 2,
A method in which the clock inputs of the flip-flop pairs connected in scan connection are connected only by wiring without using a buffer is registered as method 3, method 3 is the connection method having the least physical variation, and method 2 is 2. The clock tree forming method for a semiconductor integrated circuit according to claim 1, wherein a connection method having a small amount of physical fluctuation is preferentially used from a portion having strict timing constraints.