JP3387847B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of hierarchical macros mounted thereon, and more particularly to a clock skew (Clock Skew) in each lower hierarchical macro.
The present invention relates to a semiconductor integrated circuit capable of high speed processing by reducing w).

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor integrated circuit, C
When laying out using AD (computer aided design),
CTS (Clock T which is an input part of each layer macro
In the design process of reeSynthesis), the delay value is calculated based on the delay value of the element and the wiring registered in the CAD library, and the buffer is inserted into the circuit or the wiring length is adjusted according to the calculation result, and the total delay is calculated. Was being adjusted.

For example, as shown in FIGS. 3 and 4, when the upper layer macro 105 is provided for the four lower layer macros 101 to 104, the CTS process is performed by the lower layer macros 101 to 104 and the upper layer macro 105. It is roughly divided into two.

First, the CTS process in each of the lower hierarchy macros 101 to 104 is performed. That is, in the lower layer macro 101, the clock propagation delay from the CTS buffer 121 to the flip-flop (hereinafter abbreviated as FF) circuit 131 is set to a predetermined value based on the calculated value. Similarly, in each of the lower hierarchy macros 102 to 104, the clock propagation delay from each of the CTS buffers 122 to 124 to each of the FF circuits 132 to 134 is set to a predetermined value based on each of the calculated values.

Next, each of the above-mentioned lower layer macros 101
.. to 104, the FF circuits 131 to 13 inside the CTS buffer 125 of the upper layer macro 105 to the lower layer macros 101 to 104, respectively.
Buffer insertion or wiring length adjustment is performed so that the propagation delays up to 4 are the same.

At the time of this adjustment, the lower layer macros 101 to 1
When the respective internal delay differences 04 are large, the delay adjustment width in the CTS process performed in the upper layer macro 105 becomes diverse. For example, as illustrated, the CTS buffer 125 in the upper layer to the FF circuit 13 in the macro 101 in the lower layer.
In the cases up to 1, the wiring is long, but the delay adjustment buffer is not required in the gate. On the other hand, in the case of the upper layer CTS buffer 125 to the FF circuit 132 of the lower layer macro 102, the wiring is short, but a large number of delay adjustment buffers exist as gates.

[0007]

The above-described conventional semiconductor integrated circuit has a problem that high-speed processing cannot be performed because the clock skew for each of a plurality of hierarchical macros deteriorates.

The reason is that the clock propagation delay from the upper layer macro to the lower layer macro is adjusted comprehensively to the flip-flop circuits in each of the lower layer macros. In such an adjustment, various states occur depending on the combination of the wiring length and the delay gate based on the adjustment for each lower layer macro. Therefore, when manufacturing a semiconductor integrated circuit, the process variation of the transistor gate for each layer macro or This is because the wiring length variation becomes large.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit capable of high speed processing by reducing the clock skew in each lower layer macro.

[0010]

A semiconductor integrated circuit according to the present invention, when a plurality of hierarchical macros are mounted, is provided with a phase locked loop (PLL) macro for adjusting the clock phase inside each hierarchical macro. ing.

Therefore, since the phases of the PLLs of the macros of the respective layers can be matched with each other by adjusting the phase, in the CTS processing in the upper layer, it is only necessary to take measures against the delay until the PLL input of the lower layer macro.

In the semiconductor integrated circuit having such means, the delay difference from the CTS buffer in the upper layer to the input in each of the plurality of lower layer macros connected to the CTS buffer is small. Can be the same.

Therefore, even the lower layer macros may be adjusted so that they have the same delay.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block plan view showing an embodiment of the present invention, and FIG. 2 is a block connection diagram in which FIG. 1 is rearranged by hierarchy.

As shown in FIG. 1, the semiconductor integrated circuit 10
Is equipped with four lower layer macros 1 to 4 and an upper layer macro 5, and has a two-stage configuration. PLL macros 11 to 15 are mounted on the lower layer macros 1 to 4 and the upper layer macros 5, respectively. Therefore, for example, the PLL macro 11 receives an input to the macro and forms a loop up to the final stage buffer connected to the flip-flop (FF) circuit 31 in the lower hierarchy macro 1 via the CTS buffer 21. The same applies to the other PLL macros 12 to 14. The PLL macro 15 matches the clock input to the semiconductor integrated circuit 10 with the clock phase up to the input point of the lower layer macro.

The difference from the prior art is that the lower hierarchy macros 1 to 4 are
That is, the PLL macros 11 to 14 are respectively mounted, and all the delay adjustment buffers that are partially required as delay gates are deleted from between the upper layer macro and the lower layer macro.

In each layer macro 1 to 5, the PLL macro 1
Since the clock phase can be matched between the input and the output by each of 1 to 15, after matching the phases, C
CTS processing for delay adjustment is executed by each of the TS buffers 21 to 25. Therefore, each layer macro 1
The CTS process of No. 5 may be started from any hierarchical macro, and the order thereof is arbitrary.

When the lower layer macro 1 is used, clock propagation delay from the CTS buffer 21 to the FF circuit 31 is performed by inserting the buffer and adjusting the wiring length. Similarly, the other lower layer macros 2 to 4 are adjusted by buffer insertion and wiring length so that the same clock propagation delay can be obtained.

On the other hand, in the case of the upper layer macro 5, the PLL macros 11 to 1 are provided inside the lower layer macros 1 to 4, respectively.
4, the phase difference can be eliminated, so the upper layer macro 5
The CTS process of CTS25 is performed from
Clock propagation delay up to the input points of the four PLL macros 11 to 14 is performed by inserting a buffer and adjusting the wiring length.

The PLL macro 25 of the upper layer macro 5 is
From the input point of this PLL 25 to the F of the lower hierarchy macros 1 to 4
Clock phase matching with other semiconductor integrated circuits is performed without the phase difference up to the input points of the F circuits 31 to 34.

The upper layer macro 5 to the lower layer macros 1 to 1
As for the total characteristics up to 4, the PLL macros 11 to 14 inside the lower layer macros 1 to 4 perform the phase adjustment so that the phases of the clock propagation delays are matched with each other. In the CTS process of No. 25, P, which is the entrance to each of the lower layer macros 1 to 4
It is only necessary to consider the delays to the input points of the LL macros 11 to 14.

Therefore, in the CTS processing in the upper layer macro 5, it is not necessary to consider the clock propagation delays to the FF circuits 31 to 34 of the lower layer macros 1 to 4, respectively. As a result, in the CTS process of the upper layer macro 5, the adjustment width of the clock propagation delay is small, and the delay adjustment can be easily performed only by adjusting the wiring length, so that the delay adjustment by inserting the delay buffer is unnecessary.

[0024]

As described above, according to the present invention, each lower layer macro is provided with a PLL macro, and the phase with respect to the clock propagation delay in the lower layer macro can be matched to eliminate the phase difference. Macro CTS
In the processing, it is not necessary to consider the clock propagation delay in the lower layer macro, and the adjustment range of the clock propagation delay up to the input point of the lower layer macro is small. Therefore, not only the delay can be adjusted only by the wiring, but also the adjustment width is small, so that there is little variation in the wiring. Further, since a buffer for delay adjustment or the like is not used as a delay gate for this CTS processing, the process variation of the transistor is small.

As a result, the effect that the clock skew can be reduced can be obtained.
A high-speed semiconductor integrated circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block plan view showing an embodiment of the present invention.

FIG. 2 is a block connection diagram in which each macro of FIG. 1 is rearranged for each layer.

FIG. 3 is a block plan view showing a conventional example.

FIG. 4 is a block connection diagram in which each macro of FIG. 3 is rearranged for each layer.

[Explanation of symbols]

1, 2, 3, 4 Lower layer macro 5 Upper layer macro 10 Semiconductor integrated circuits 11, 12, 13, 14, 15 PLL (phase locked loop) macros 21, 22, 23, 24, 25 CTS buffers 31, 32, 33 , 34 FF (flip-flop)
circuit

Continuation of the front page (56) References Japanese Patent Laid-Open No. 10-161769 (JP, A) Japanese Patent Laid-Open No. 11-65699 (JP, A) Minobu Hayashi, Iwao Sasase, Shinsaku Mori, etc. Digital signal processing type in each rank Phase difference of PLL Dependent synchronous network with different average frequency, The Institute of Electronics, Information and Communication Engineers, B- ▲ I ▼, Nihon, February 1991, VOL. 74 NO. 2, P. 129-135 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 21/82 H01L 27/04 JISST file (JOIS)

Claims (6)

(57) [Claims] 1. A semiconductor integrated circuit having a plurality of hierarchical macros, wherein each hierarchical macro is provided with a phase locked loop (PLL) macro for adjusting a clock phase therein. 2. The phase-locked loop in the upper layer macro according to claim 1, wherein the clock phases of the input of the semiconductor integrated circuit and the respective inputs of the respective lower layer macros match, and the phase-locked loop of each lower layer macro is respectively A semiconductor integrated circuit characterized in that the clock phases in the macro of are matched. 3. The C of the upper layer macro according to claim 2.
A semiconductor integrated circuit having wirings having the same clock delay from a TS (Clock Tree Synthesis) buffer to an input in each of a plurality of lower layer macros that are multiple-connected to the clock propagation delay buffer. 4. The semiconductor integrated circuit according to claim 3, wherein inside each of the plurality of lower layer macros, each lower layer macro has a clock propagation delay buffer having the same clock delay and an internal wiring. 5. A method of manufacturing a semiconductor integrated circuit having a plurality of hierarchical macros, wherein a phase-locked loop macro is provided inside each hierarchical macro, and a circuit for matching clock phases within each hierarchical macro is formed. A method of manufacturing a semiconductor integrated circuit, comprising: 6. The wiring according to claim 5, wherein the wiring connecting the output of the upper layer macro to the input of each of the plurality of connecting lower layer macros is adjusted to have the same clock delay, while A method for manufacturing a semiconductor integrated circuit, wherein each of the lower layer macros is adjusted so that at least one of an internal clock propagation delay buffer and a wiring has the same clock delay.