JP2908447B1 - Layout method of semiconductor integrated circuit - Google Patents

Abstract

Abstract: [PROBLEMS] Without impairing the result of fine adjustment of delay amount,
Provided is a layout method of a semiconductor integrated circuit which can reduce congestion on wiring and obtain good wiring performance by CTS. SOLUTION: The layout method of the semiconductor integrated circuit includes a step of arranging functional blocks D2 and D4 in an internal logic area and a step of connecting a clock wiring to each of the functional blocks D2 and D4 by CT.
A step of dividing the S target nets D3, D5, and D6 into CTS non-target nets 13 other than the CTS target net;
Arranging the target nets D3, D5, D6. The layout method further includes a CTS target net D3,
A step of saving the wiring length data of D5 and D6 in the memory, a step of arranging the non-CTS target net 13 after the saving of the wiring length data, a step of extracting data related to the wiring congestion, and reading from the wiring congestion part data and the memory CTS target nets D3, D5, D
6 is arranged while bypassing the wiring congested portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly, to a layout method for a semiconductor integrated circuit for improving wiring properties.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as LSIs)
In this case, one clock signal or a plurality of clock signals having different phases are input, and this clock signal is distributed to each flip-flop in the LSI, and is synchronized with the clock signal to perform various operations or decode and memory. And operations such as read and write. Here, if the wiring length from the clock signal distribution source to each supply destination is different, a so-called clock skew occurs in which the timing of arrival of the clock signal at each supply destination is shifted due to wiring delay. When the clock skew increases, an erroneous signal is captured by a flip-flop, or a noise pulse is generated at an output of a logic gate, which may lead to a malfunction of the LSI.
Thus, in a clock-synchronous LSI, the performance such as the operating speed is determined by the clock skew.

A conventional delay adjustment method for adjusting clock skew is described in Japanese Patent Application Laid-Open No. 8-272480. FIGS. 8A and 8B are diagrams for explaining the delay adjustment method described in this publication. FIG. 8A is a plan view schematically showing a part of the wiring, FIG. 8B is a side view of FIG. (c) is a side view schematically showing a part of the wiring after delay adjustment.

In FIGS. 8 (a) and 8 (b), terminals H2 and H3 for inputting and outputting data to and from the outside of a functional block (or a basic logic cell) are arranged at a predetermined interval. Logic cells are interconnected by an inter-cell wiring H1. Between the terminals H2 and H3, a delay adjusting means for adjusting a wiring delay by changing a resistance value is included.

The delay adjusting means includes an inter-cell wiring H1;
A delay adjustment wiring H4 that is arranged in a wiring layer different from the inter-cell wiring H1 and has a higher resistance value than the inter-cell wiring H1; and an overlapping area H where the inter-cell wiring H1 and the delay adjustment wiring H4 overlap.
11 and contacts H5 and H6 for connecting the inter-cell wiring H1 and the delay adjustment wiring H4 in the overlapping area H11. On the delay adjustment wiring H4, the contacts H5 and H
6 are arranged at an interval to form a data propagation path H7 before delay adjustment.

In FIG. 8C, the contact H5 shown in FIG. 8B is moved to the terminal H3 by the distance H10 to form the contact H8, whereby the data propagation path H9 after the delay adjustment is obtained. Thereby, the data propagation path H
9 is different from the data propagation path H7, and the delay adjustment is completed. However, in such a delay adjustment method, the adjustment of the skew value has priority over the wiring property, and a high-resistance layer such as the delay adjustment wiring H4 is separately provided as a wiring layer dedicated to the resistance. Must be arranged, and the wiring is congested, resulting in impaired good wiring performance.

As another conventional delay adjustment method, by using a wiring method called Clock Tree Synthesis (hereinafter, simply referred to as CTS), a clock line is formed into a tree structure of a high-drive buffer to each block. Attempts have been made to minimize the relative skew of the clock inputs.

The other conventional delay adjustment method has a function block arranging step, a CTS execution step, and a wiring step between function blocks.
Design: the layout data is created while executing each step by CAD. In the function block arranging step, the function blocks are arranged in the internal logic area of the semiconductor integrated circuit. In the CTS execution step, CTS target nets that make the delay amount (skew value) of each branch net branching from a common node substantially equal are distributed to each functional block. Furthermore, in the inter-functional-block wiring step, a non-CTS target net other than the CTS target net is placed with the CTS target net placed in the internal logical area.

[0009]

In the above conventional delay adjustment method, a CTS target net is arranged in an internal logic area while finely adjusting a skew value according to a wiring length.
The nets not subject to the CTS are arranged while maintaining the finely adjusted wiring state. For this reason, the wiring process of the non-CTS target net may not be performed smoothly, or the non-CTS target net may overlap with the CTS target net, resulting in congestion of the wiring, thereby deteriorating good wiring properties.

In view of the above, the present invention reduces the degree of congestion on the wiring without impairing the result of fine adjustment of the delay amount,
An object of the present invention is to provide a layout method of a semiconductor integrated circuit that can obtain good wiring properties by CTS.

[0011]

In order to achieve the above object, a semiconductor integrated circuit layout method according to the present invention is a semiconductor integrated circuit layout method for creating layout data by computer-aided design. Arranging a functional block in a logical area, and connecting a clock wiring to each of the functional blocks with a CT for substantially equalizing delay amounts of respective branch nets branching from a common node.
Classifying the S target net and a CTS non-target net other than the CTS target net, arranging the CTS target net, saving the wiring length data of the arranged CTS target net to a memory, Arranging the non-CTS target net after saving the wiring length data;
Extracting data related to wiring congestion in the internal logic area; and performing CT calculation based on the data related to wiring congestion and the wiring length data read from the memory.
And arranging the S target net while bypassing the wiring congested portion.

A "functional block" in the present invention is a term that includes a basic logic cell, and is referred to as a block even if there is only one functional element such as a transistor.
In the present invention, “CTS” means a wiring method called Clock Tree Synthesis. In this wiring method, a clock line is assigned to each functional block arranged in an internal logical area by a tree of functional blocks. Wiring is performed so as to have a structure, and the delay amounts (skew values) of the respective branch nets branching from the common node are made substantially equal.

In the layout method of the semiconductor integrated circuit according to the present invention, the delay amount is finely adjusted according to the wiring length of the CTS target net, and the fine-adjusted wiring length data is temporarily saved in the memory, and then the non-CTS target net is removed. Place it smoothly. Further, a CTS target net whose delay amount has been fine-tuned with respect to the wired CTS non-target net is arranged so as to bypass the wiring congested portion. Thereby, the CTS of the CTS target wiring is
Alleviates the congestion of wiring without impairing the function.

Here, it is preferable that the displayed CTS target net is deleted from the screen when executing the respective steps while displaying the above steps on the screen in the computer assisted design and saving the wiring length data. Thereby, CTS
The placement of non-target nets is performed well.

Preferably, the memory comprises a database memory in computer-aided design. In this case, it is not necessary to separately prepare a special memory for storing the wiring length data.

[0016]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a diagram schematically showing a process of creating an LSI by a layout method according to the embodiment.
(A) is the state before the placement of the CTS target net, (b) is the state before C
The state after the placement of the TS target net is shown. The layout is performed by computer aided design (CAD).

In FIG. 1A, one CTS root buffer D1 arranged in an internal logic area is provided to a plurality of functional blocks (basic logic cells) D4 such as flip-flops and latches operated by a supplied clock. Are connected via the wiring.

In FIG. 1B, the CT shown in FIG.
Between the S route buffer D1 and each functional block D4,
A functional block D2 such as a buffer for obtaining a tree structure of clock lines is inserted by CTS wiring. CT
By appropriately arranging functional blocks D2 having different resistance values and the like at each branch point in the subsequent stage of the S root buffer D1, the delay amount from the CTS root buffer D1 to each functional block D4 is roughly adjusted. I have. C
The TS route buffer D1 and the functional block D2 are CTS
The target block D6 is connected to each other, the preceding and subsequent functional blocks D2 are connected to each other by a CTS target net D5, and the subsequent functional blocks D2 and D4 are connected to each other by a CTS target net D3. I have. In such a CTS wiring, the delay amount that could not be adjusted only by the arrangement of each functional block D2 is increased by the CTS target net D
Fine adjustment is made by adjusting the wiring lengths of 6, D5 and D3.

FIG. 2 is a diagram showing an actual layout image of each element corresponding to FIG. In FIG. 2, E1 corresponds to the CTS root buffer D1 of FIG. 1, and E2, C corresponds to the functional block D2 for obtaining the tree structure.
E3 corresponding to TS target net D3, functional block D4
E4 are respectively arranged corresponding to. The CTS route buffer E1 and the functional block E2 are connected to each other by a CTS target net E6, the preceding and subsequent functional blocks E2 are connected to each other by a CTS target net E5, and the subsequent functional blocks E2 and E4 are connected to each other. Are connected to each other by a CTS target net E3.

FIG. 3 shows the layout image of FIG.
FIG. 13 is a diagram illustrating a state in which wiring is congested due to the addition of a net that is not an S target. F1 indicates an area where the CTS non-target net 13 is connected to the corresponding functional blocks 11 and 12. In the figure, the wiring is congested because the CTS target net E3 is held on the CAD.

FIG. 4 is a layout image of FIG.
It is a figure showing the state where S subject net E3 was bypassed. In FIG. 4, the wiring length data once saved in the memory in the CTS wiring process described later is read and used as reference data, and the wiring is routed around the CTS target net E3 in a non-congested direction. Has been alleviated.

Next, a detailed description will be given of a layout method according to the present embodiment for reducing the congestion of wiring. FIG.
9 is a flowchart showing a procedure in the layout method. This layout method includes a functional block arranging step, a CTS executing step, and a wiring step between functional blocks.

In step A1, a function block arranging step of arranging each function block in the internal logic area of the semiconductor integrated circuit is performed. That is, a circuit design for determining a circuit configuration and element characteristics at a transistor level that satisfies given circuit specifications is executed, and each functional block required for this is initially arranged in an internal logic area.

In step A2, the CTS for making the delay amounts of the respective branch nets branching from the common node substantially equal
The target net is distributed to each functional block, and a CTS execution step of storing wiring length data for each clock net in a memory of a database used in CAD and temporarily saving the data is performed. That is, according to the logical connection information of the designed circuit, the clock nets are distributed to form a tree-like CTS.
Wiring is created, and a functional block (buffer) is inserted into the logical connection information of the circuit so that the load capacity at each stage matches. CT between buffers in each stage
The S target nets are equal in length and capacity, and
The buffers are designed so that the number of fan-outs in each buffer is the same. At this time, in the CTS wiring, the clock skew which cannot be sufficiently absorbed only by the arrangement of the functional blocks such as the buffer is changed by the CTS connecting each functional block.
Fine adjustment is made according to the wiring length of the TS target net (E3, E5, E6 in FIG. 3), and the wiring length data is stored in a memory and saved. At this time, the images of the CTS target nets (E3, E5, E6) are deleted from the screen used in CAD.

In step A3, the CTS target net (E3, E5, FIG. 3 in FIG. 3) is determined based on the estimated data related to the wiring congested portion and the wiring length data read from the memory.
An inter-functional-block wiring step of arranging E6) while bypassing the congested portion of the non-CTS target net (13 in FIG. 3) is performed. In other words, a CTS non-target net is placed while maintaining the wiring route of the CTS target net. At this time, the degree of wiring congestion is estimated, and if a fault exists on the CTS wiring,
At step A2, the wiring length data saved in the memory is read out, and the detour direction of the CTS target net is determined based on the wiring length data and the wiring congestion portion data.
As described above, since the wiring route of the CTS target net can be changed without changing the once adjusted delay amount, a good net arrangement is possible.

FIG. 6 is a flowchart sequentially showing the steps included in the CTS execution step described with reference to FIG. CTS
The execution step includes a step of acquiring a CTS target wiring name, a CTS tree structure creation step, and a CTS wiring step.

In step B1, each wiring name of the CTS target net and the CTS non-target net is obtained, that is,
The clock wiring to each of the functional blocks is configured such that the delay amounts of the respective branch nets branching from the common node are made substantially equal.
TS target net and CTS other than this CTS target net
A CTS target wiring name or the like obtaining step for classifying the target net into a non-target net is performed.

In step B2, a CTS tree structure forming step of forming a clock line tree structure while inserting and arranging each functional block for CTS by a general CTS technique is performed. In step B3, in addition to executing the fine adjustment of the delay amount by changing the wiring length, which is a part of the prior art, the step of saving the capacitance of each branch wiring of the CTS tree, that is, the wiring length data after wiring, to a memory. CT to execute
An S wiring process is performed. At this time, the image of the CTS target net is deleted from the screen.

FIG. 7 is a flowchart sequentially showing the steps included in the inter-functional-block wiring step described with reference to FIG. The wiring step between the functional blocks includes a schematic wiring step, CTS
It includes a target net wiring step, a CTS non-target net wiring step, a wiring congestion part extracting step, and a CTS wiring bypass step.

In step C1, the degree of wiring congestion between functional blocks is estimated by a known congestion estimating method using wiring check software or the like, and a general wiring step of determining an overall rough wiring path is performed. In step C2, CT
A CTS target net wiring process for wiring the S target net is performed. In step C3, a non-CTS target net wiring step of arranging a non-CTS target net is performed. In step C4, a congested portion of all wirings is extracted, and C
A wiring congestion portion extraction step is performed to check whether or not the TS target net is involved.

In step C5, when the CTS target net is involved in the wiring congestion, the wiring length data saved in the CTS wiring step of step B3 is read out, and the congested part extracted in the wiring congested part extracting step is avoided. Search for directions. Further, based on the wiring congestion part data and the wiring length data, which are the search results, the CTS target net E3 in the congested area F1 in FIG. 3 is detoured by the same length as shown in FIG. 4 as it is. (CTS wiring bypass step).

As described above, in the layout method according to this embodiment, the delay amount is finely adjusted according to the wiring length of the CTS target net, and the finely adjusted wiring length data is temporarily saved in the memory, and then the CTS is adjusted. Non-target nets can be arranged smoothly. In addition, a redundant wiring for a CTS target net whose delay amount has been fine-tuned can be arranged for the wired CTS non-target net while bypassing the wiring congestion part.

Although the present invention has been described based on the preferred embodiment, the layout method of the semiconductor integrated circuit according to the present invention is not limited to the above-described embodiment. Various modified and changed layout methods for a semiconductor integrated circuit are also included in the scope of the present invention.

[0034]

As described above, according to the layout method of the semiconductor integrated circuit of the present invention, the degree of congestion on the wiring can be reduced without impairing the result of fine adjustment of the delay amount,
Good wiring properties by TS can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a process of creating an LSI by a layout method according to an embodiment of the present invention;
(A) is the state before the placement of the CTS target net, (b) is the state before C
The state after the placement of the TS target net is shown.

FIG. 2 is a diagram showing an actual layout image of each element corresponding to FIG. 1 (b).

FIG. 3 is a diagram illustrating a state in which wiring is congested due to the addition of a non-CTS target net to the layout image of FIG. 2;

FIG. 4 is a diagram showing a state in which a CTS target net is bypassed in the layout image of FIG. 3;

FIG. 5 is a flowchart illustrating a procedure in a layout method according to the embodiment.

FIG. 6 is a flowchart sequentially showing each step included in the CTS execution step described in FIG. 5;

FIG. 7 is a flowchart sequentially showing each step included in the inter-functional-block wiring step described with reference to FIG. 5;

8A and 8B are diagrams for explaining a conventional delay adjustment method, in which FIG. 8A is a plan view schematically showing a part of a wiring, and FIG.
3A is a side view schematically showing a part of the wiring after delay adjustment. FIG.

[Explanation of symbols]

D1, E1: CTS root buffer D2, E2: functional block D3, D5, D6, E3, E5, E6: CTS target net D4, E4: functional block

──────────────────────────────────────────────────の Continued on the front page (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50 JICST file (JOIS) Patent file (PATOLIS)

Claims (3)

(57) [Claims] In a layout method of a semiconductor integrated circuit for creating layout data by computer-aided design, a step of arranging functional blocks in an internal logic area of the semiconductor integrated circuit; CTS target net and CTS other than the CTS target net for making the delay amounts of the respective branch nets branching from the node substantially equal
A step of categorizing the CTS target net; a step of saving the wiring length data of the placed CTS target net in a memory; and a step of saving the wiring length data in the memory. Arranging the CTS target net based on the data related to the wiring congestion and the wiring length data read from the memory based on the data related to the wiring congestion in the internal logic area. And arranging the semiconductor integrated circuit while detouring. 2. The computer-aided design according to claim 1, wherein said steps are executed while being displayed on a screen, and when the wiring length data is saved, the displayed CTS target net is erased from the screen. 2. The layout method for a semiconductor integrated circuit according to item 1. 3. The layout method for a semiconductor integrated circuit according to claim 1, wherein the memory comprises a database memory in a computer-aided design.