JP2692608B2 - Integrated circuit placement apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design of a semiconductor integrated circuit, and more particularly to an integrated circuit placement device and method.

[0002]

2. Description of the Related Art A technique for arranging cells by division is one of typical techniques for determining the arrangement of cells in a layout design of a semiconductor integrated circuit.

Here, the technique of arranging by placement is a technique of determining the position of each cell by repeatedly dividing a given circuit and chip area by cut lines (division lines) that are hierarchically set. is there. However, when dividing, the number of nets that cross the cut line (hereinafter, the number of cuts) should be minimized. Here, the net is
It is a wiring that connects cells to each other. This technique will be described below with reference to FIG.

When the cells 601 to 616 of FIG. 6 are arranged in the chip area 617, first, the circuit and the chip area 617 are divided into two by the cut line 618 as shown in FIG. Subsequently, as shown in FIG. 6B, each circuit and area (rectangular area divided by the cut line) are divided into two by a cut line 619 in a direction perpendicular to the previous cut line 618. In this way, the horizontal and vertical cut lines 61
By alternately dividing the circuits and areas by 8 to 623, each cell is assigned to each area as shown in FIG. 6 (c). After that, the cells assigned to each area are arranged at optimum positions in the area, and the arrangement position of each cell is determined.

Among the techniques for arranging by the division as described above, DA symposium '93 Proceedings (199) has been proposed as a technique considering the prevention of circuit malfunction due to signal delay.
(Published August 26, 2013, Publisher: Information Processing Society of Japan) 29
There is a technology described on pages 32 to 32 (Title: Delayed placement method based on minicut method, author: Susumu Kobayashi, Masaki Ishikawa, Tomoyuki Fujita)

The purpose of this prior art is to place a timing constraint (signal delay constraint) on a circuit so that the constraint is satisfied and the total wiring length is shortened. Timing constraints are given to the terminal pairs of cells in the circuit with the maximum allowable delay time therebetween.

FIG. 5 is an explanatory diagram of timing constraints. This figure shows a part of the circuit, and the terminal 501
The path (signal path) between the and the terminal 502 is shown. Cells 503-508 are cells on these paths. Terminal 501
When a timing constraint is given between the terminal and the terminal 502, the signal delay time in all paths between these two terminals must be less than or equal to the maximum allowable delay time given by the timing constraint.

In this conventional technique, the division of the circuit and the area by the cut line is repeated as described above.
When dividing the circuit by each cut line, first divide the circuit so that the number of cuts is as small as possible, and then select a critical path (a timing constraint is violated) from among the paths between the pin pairs with timing constraints. Path that is likely to be). Then, the cell on the critical path is moved to improve the delay of the critical path.

The cell moving method at this time will be described with reference to FIGS.
An explanation will be given using (b). FIG. 3A shows a part of the chip area in the middle of the placement process, and cells 302 to 308 are a part of the cells in the circuit. Treated cut line 31
The division processing has already been completed for 0 to 313, and division by the cut line 309 being processed is currently being performed.
Critical path 301 is from cell 302 to cells 303, 304, 305,
It is the path to cell 307 via 306. In this conventional technique, first, a cell that needs to be moved is extracted in order to shorten the length of the critical path 301. Since it is not possible to move cells beyond the processed cutlines 310 to 313, in order to shorten the length of the critical path 301 in this case, cells 304 and 305 should be cutline that is being processed.
There is no choice but to move it to the left side of 309 as shown in Fig. 3 (b). Therefore, move the cells 304 and 305 to the critical path.
Shorten the length of 301. As a result, the signal delay in this path is reduced.

In this conventional technique, the timing constraint violation is minimized by moving the cell in consideration of such delay every time division is performed by one cut line.

[0011]

The above-mentioned prior art attempts to improve the signal delay by shortening the length of the critical path by reducing the number of times the critical path crosses the cut line. May relate to the magnitude of signal delay not only to cells on the path but also to other cells. This will be described with reference to FIG.

FIG. 4 shows some of the cells in the circuit and the nets that connect them, and the critical path 401 is the cell.
This is a path from 402 to cell 406 via cells 403, 404, and 405. In this figure, net 40 on critical path 401
The signal delay at 8 is related not only to the location of cells 403, 404, but also to the location of cell 407. Cell 407 is cell
Far from 403 and 404, the wiring capacitance of the net 408 increases, and as a result, the delay from the cell 403 to the cell 404 increases. A cell which is not on the critical path like the cell 407 but whose position affects the signal delay of the critical path is called a fan-out cell.

In the above-mentioned conventional technique, since the delay improvement due to the movement of the fan-out cell is not considered, even if the length of the critical path is shortened, the fan-out cell is far away from the path and the delay improving effect is obtained. Was sometimes small.

An object of the present invention is to provide an integrated circuit placement device and method for extracting fan-out cells having an improvement effect by movement and moving those cells to further reduce the delay of the critical path as compared with the prior art. To do.

[0015]

The integrated circuit placement device of the present invention minimizes the number of wirings that cross the dividing line between the input device for inputting the placement data and the signal delay constraint data and the circuit in the placement data. So divided, the mini-cut device that describes the result in the placement data, a timing analysis device that outputs signal delay data by calculating the signal delay in the circuit in the placement data, based on the signal delay data, On-path cell moving device that changes the arrangement position information of the cells on the critical path in the arrangement data so that the signal delay constraint described in the signal delay constraint data is satisfied, and based on the signal delay data, the Connect to the net included in the critical path in the placement data so that the signal delay constraint described in the signal delay constraint data is satisfied. And a fan-out cell moving device for changing the arrangement position information of cells not on the critical path, and an output device for outputting the arrangement position information of all cells described in the arrangement data. It is characterized by

According to the integrated circuit placement method of the present invention, the first step of inputting placement data and signal delay constraint data, and dividing the circuit in the placement data so that the number of wirings crossing the dividing line is minimized, The second step of writing the result in the arrangement data, the third step of calculating the signal delay in the circuit in the arrangement data and outputting the signal delay data, and the signal delay constraint data based on the signal delay data The fourth step of changing the arrangement position information of the cells on the critical path in the arrangement data so that the signal delay constraint described in (4) is satisfied, and the signal delay constraint data is described based on the signal delay data. In order to satisfy the constraint of the signal delay, in the placement data, connected to the net included in the critical path,
And a fifth step of changing arrangement position information of cells not on the critical path, and a sixth step of outputting arrangement position information of all cells described in the arrangement data. .

[0017]

EXAMPLES Next, examples of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of an integrated circuit placement device according to an embodiment of the present invention. This integrated circuit placement device is an input device.
101, mini-cut device 102, and timing analysis device 10
3, the on-path cell moving device 104, the fan-out cell moving device 105, and the output device 106. The function of each device is as follows.

The input device 101 inputs the arrangement data and the signal delay constraint data, the mini-cut device 102 selects one cut line, and divides the set of cells so that the number of wirings crossing the cut line is minimized. . The timing analysis device 103 calculates the signal delay of the path and creates signal delay data that describes the critical path and its signal delay based on the signal delay constraint data input from the input device 101.
Update. The on-path cell moving device 104 moves cells on the critical path in order to reduce the signal delay of the critical path. The fan-out cell moving device 105 moves the fan-out cell that affects the signal delay of the critical path in order to further reduce the signal delay of the critical path. The output device 106 determines the exact position of each cell based on the result of division by all cut lines, and outputs the result.

FIG. 2 is a flow chart showing the operation of the embodiment of FIG. In FIG. 2, step 201 is an input device, step 202,
Steps 203, 209 and 210 are performed by the mini-cut device, step 204 is performed by the timing analysis device, step 205 is performed by the on-path cell moving device, steps 206, 207 and 208 are performed by the fan-out cell moving device, and steps 211 and 212 are performed by the output device.

Next, each step will be described.

At step 201, the placement data and the signal delay constraint data are input. The placement data includes information about a chip area, information about a cut line, information about a cell, and information about a cell connection relationship. The information about the cut lines includes a list in which the cut lines are arranged in the processing order (hereinafter, an unprocessed cut line list) and position information of each cut line. The information regarding cells includes the arrangement position / size / terminal position of each cell and the information of the area to which each cell belongs. In this step 201, the arrangement position of each cell is undecided.

The designer can set a limit on the signal delay of an arbitrary path, and the signal delay constraint data describes the paths designated by the designer and the delay constraint values between them.

In step 202, the first cut line in the unprocessed cut line list is the cut line to be processed. For this cut line, a set of cells is divided into two in steps 203 to 208.

In step 203, the set of cells is divided into two so as to minimize the number of cuts.

In step 204, the delay of each path to which the signal delay constraint is applied is estimated, and the path whose delay is larger than the constraint value is extracted as the critical path.

In step 205, among the cells on the critical path, cells whose movement can improve the delay of the path are extracted, and those cells are moved to the opposite side of the cut line.

For example, the critical path 301 shown in FIG.
In order to improve the delay of the cell 304, as shown in FIG.
305 may be moved to the left side of the cut line 309 being processed.

In step 206, fan-out cells connected to the nets included in each critical path are extracted. In FIG. 3, the cell 308 corresponds to the fan-out cell.

At step 207, the improvement effect due to the movement of each fan-out cell is calculated. Here, the improvement effect is quantified by comprehensively judging how much the signal delay and the number of cuts of the critical path are improved when the fan-out cell moves to the opposite side of the cut line. .

In step 208, the fan-out cell whose improvement effect is larger than the reference value is moved to the opposite side of the cut line. In the case of FIG. 3 (b), the cell 308 moves to the left side of the cut line 309 being processed as shown in FIG. 3 (c).

In step 209, the cut line being processed is deleted from the unprocessed cut line list.

In step 210, if the unprocessed cut line list is empty, the process proceeds to step 211, and if not, the process proceeds to step 202.

In step 211, the exact position of each cell is determined based on the result of the division process.

At step 212, the placement result is output.

[0036]

According to the present invention, by combining the movement of cells on the critical path and the movement of the fan-out cells, the signal delay on the critical path can be minimized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing the arrangement process of FIG.

FIG. 3 is an explanatory diagram of a delay improvement method.

FIG. 4 is an explanatory diagram of a fan-out cell.

FIG. 5 is an explanatory diagram of timing constraints in the conventional example.

FIG. 6 is an explanatory diagram of an arrangement technique by division of a conventional example.

[Explanation of symbols]

 101 Input device 102 Mini-cut device 103 Timing analysis device 104 Cell moving device on path 105 Fan-out cell moving device 106 Output device 201 Data input step 202 Cut line selection step 203 Mini-cut division step 204 Timing analysis step 205 Cell moving on critical bus Step 206 Fan-out cell extraction step 207 Improvement effect calculation step 208 Fan-out cell movement step 209 Unprocessed cut line list update step 210 Unprocessed cut line existence judgment step 211 Mapping step 212 Placement result output step 301 Critical path 302 to 308 cells 309 Cutline in process 310-313 Cutline in process 401 Critical path 402-407 Cell 408 Net

Claims (6)

(57) [Claims] 1. An input device for inputting arrangement data and signal delay constraint data, and a circuit in the arrangement data are divided so that the number of wirings crossing a dividing line is minimized, and the result is described in the arrangement data. A mini-cut device, a timing analysis device that calculates signal delay in a circuit in the arrangement data and outputs signal delay data, and a signal delay constraint described in the signal delay constraint data based on the signal delay data. The on-path cell moving device that changes the arrangement position information of the cells on the critical path in the arrangement data so that is satisfied, and the signal delay constraint described in the signal delay constraint data is based on the signal delay data. In order to be satisfied, a cell that is connected to a net included in the critical path and is not on the critical path in the placement data. An integrated circuit placement device, comprising: a fan-out cell moving device that changes placement position information of a cell; and an output device that outputs placement position information of all cells described in the placement data. 2. A first step of inputting layout data and signal delay constraint data, dividing a circuit in the layout data so that the number of wirings crossing a dividing line is minimized, and the result is stored in the layout data. A second step described, a third step of calculating the signal delay in the circuit in the arrangement data and outputting the signal delay data, and a signal delay described in the signal delay constraint data based on the signal delay data. A fourth step of changing the arrangement position information of the cells on the critical path in the arrangement data so that the constraint is satisfied, and the signal delay constraint described in the signal delay constraint data is satisfied based on the signal delay data. As described above, the placement position of the cell in the placement data that is connected to the net included in the critical path and is not on the critical path An integrated circuit placement method comprising: a fifth step of changing placement information; and a sixth step of outputting placement position information of all cells described in the placement data. 3. The arrangement data includes information about a chip area, information about a cut line, information about a cell,
The information about the connection relation of the cells is included, and the information about the cut line includes a list in which the cut lines are arranged in the order of processing and the position information of each cut line, and the information about the cell includes each cell. 2. The integrated circuit arrangement device according to claim 1, further comprising information on the arrangement position, size, terminal position, and area to which each cell belongs. 4. The arrangement data includes information about a chip area, information about a cut line, information about a cell,
The information about the connection relation of the cells is included, and the information about the cut line includes a list in which the cut lines are arranged in the order of processing and the position information of each cut line, and the information about the cell includes each cell. 3. The integrated circuit arranging method according to claim 2, further comprising information on the arrangement position, size, terminal position, and area to which each cell belongs. 5. The integrated circuit placement device according to claim 1, wherein the signal delay constraint data includes a path designated by a designer and a delay constraint value therebetween. 6. The integrated circuit placement method according to claim 2, wherein the signal delay constraint data includes a path designated by a designer and a delay constraint value therebetween.