JP2960601B2 - How to place logic cells - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for arranging logic cells in an automatic layout system for semiconductor integrated circuits, and more particularly to an arrangement method for initially dividing a plurality of unarranged logic cells into arrangement areas.

[0002]

2. Description of the Related Art With the recent miniaturization and large scale of VLSI, signal propagation delay time caused by wiring capacitance, which has not been much considered in the past, has become a problem. Furthermore, the number of chips that require high-speed operation is increasing, and the necessity of considering signal propagation is increasing.

[0003] The problem of timing assurance is to suppress the delay time of a path consisting of a logic gate-wiring-logic gate chain within a required time. Factors of the delay include a delay due to the logic gate itself and a delay due to the wiring. The delay of the logic gate itself is difficult to change in the layout because the logic gate to be used in the netlist as the input of the layout processing is given in advance. Therefore,
In the layout processing, timing restrictions are guaranteed by controlling the wiring length.

The automatic layout system includes automatic arrangement for determining the position of a logic cell on a chip and automatic wiring for determining a wiring path between logical cells having a connection relationship.

In the automatic placement process, a two-stage placement method is currently widely used. This method is divided into a stage of initially assigning a logic cell (initial placement process) and a stage of performing replacement improvement (placement improvement process), and the processes are performed in this order.

In the automatic wiring process, a step of determining a rough wiring path between logical cells having a connection relationship (schematic wiring processing) and a step of determining a detailed wiring path according to the rough wiring path (detailed wiring processing) The processing is performed separately.

When the processing is performed in this order, the final arrangement result (integration degree,
Electrical characteristics). for that reason,
It is important to consider the timing from the early stages of the layout.

In the conventional initial arrangement processing, a method of determining a cell allocation region by repeatedly performing a two-partitioning process (initial division process and division improvement process) (M. Burstein, "Timin
g Influenced Layout Desighn ", 22nd DAC, pp.124-13
0, 1985).

The initial dividing process generally aims at minimizing the number of wirings across the regions while making the total area of the cells divided into the assigned regions almost uniform in each region. Similar to the initial division processing, the division improvement processing aims at minimizing the number of cuts between the areas (mini-cut processing).

However, when the initial division processing is performed by the above-described method, a path that violates the timing constraint after the initial division processing may occur. Further, since the final layout result largely depends on the initial stage of the layout, removing the violating path after the end of the initial division may impose a burden on the subsequent layout processing and deteriorate the quality of the layout. .

Although there is hardly any timing in the initial division process, the slack value (required delay time-actual delay time) is used when constructively selecting and positioning cells. By taking into account,
Some attempt to meet timing constraints (S.Sutant
havibul and E. Shragowitz, "An Adaptive Timing-Driv
en Layout for High Speed VLSI ", Proc. of 27th DAC,
pp.90-95,1990).

However, this method does not guarantee timing constraints, and the number of cuts straddling a cut line arbitrarily drawn on a chip tends to increase.

As described above, in the initial placement processing in the conventional automatic layout system, it is not possible to increase the degree of integration while taking electrical characteristics into consideration.

[0014]

As described above, in the conventional initial dividing process, little consideration is given to the timing constraint, and a path that violates the timing constraint may occur after the initial dividing process. In addition, if an attempt is made to remove a path that violates the processing after the initial division, the quality of the arrangement tends to deteriorate.

The present invention solves such a problem and provides a method of arranging logic cells in an automatic layout system which satisfies timing constraints and enables effective use and high integration of a chip substrate. The purpose is to:

[0016]

In order to achieve the above object, the present invention comprises a step of calculating a connection strength of each of the unplaced logic cells in each of the placement areas; Allocating and calculating the virtual wire length of each critical net connected to the unplaced logic cell, and calculating the slack value of each critical net from the calculated virtual wire length and the upper limit of each critical net length And selecting an unplaced logic cell having the maximum connection strength from the unplaced logic cell group having the smallest slack value. Allocating to the arrangement area having the largest connection strength in the arrangement area group having the maximum slack value.

[0017]

According to the present invention, when initially placing a plurality of unplaced logic cells in a divided placement area when an upper limit is set for a critical net length belonging to a critical path, the unplaced logic cell Calculating the connection strength in each of the placement areas, temporarily assigning the unplaced logic cell to each placement area, calculating the virtual wiring length of each critical net connected to the unplaced logic cell, and calculating the calculated virtual From the wiring length and the upper limit value of each critical net length, calculate the slack value of each critical net, and among the unplaced logic cell group having the smallest slack value, the unplaced logic cell having the maximum connection strength is determined. The selected unallocated logic cell is allocated to the layout area having the highest connection strength in the layout area group in which the slack value is positive or the slack value is the maximum.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

The feature of the initial division processing in the present invention is to consider the net length of the critical net when determining the cell allocation position.

That is, before performing the initial division processing, a timing analysis based on the virtual wiring length is performed to extract a critical path that causes a delay specification over. A case will be described in which a net length upper limit constraint (hereinafter, referred to as an ideal wiring length) is set for a critical net belonging to a critical path in consideration of the driving force of a cell.

Since the initial arrangement process is basically a repetition of the two-divided process, the algorithm of the two-divided process will be described below with reference to the flowchart (FIG. 1).
Here, an initial division process for dividing a certain arrangement region into two regions (L, R) will be described.

In step 1, the connection strength (CiL-CiR) of the unplaced logic cell with the placed cell (including the external terminal) is calculated (updated). Here, CiL is the number of connections to the existing cells in the L area, and CiR is the number of connections to the existing cells in the R area.

If it is determined in step 2 that there is an unplaced logic cell to be connected to the critical net (hereinafter referred to as a critical cell), the process proceeds to step 3. If not, go to step 5.

In step 3, one critical cell is extracted, and the virtual wiring length of the critical net when it is assigned to each of the regions L and R is calculated.

In step 4, a slack value (ideal wiring length−virtual wiring length) when a critical cell is temporarily allocated to each of the regions L and R is calculated, and the same processing is repeated until the critical cell dies.

In step 5, a critical cell having a maximum connection strength | CiL-CiR | is selected from a group of critical cells having a minimum slack value.

In step 6, an area having the maximum connection strength is selected from the allocation candidate area group in which the slack value is positive or the slack value is the maximum.

In step 7, if the predetermined constraint condition (allocation area size) is not satisfied, the next candidate cell (the cell having the next largest connection strength) is selected.
What. If so, go to step 8.

In step 8, the selected unplaced logic cell is allocated to the selected allocation candidate area.

In step 9, if there is an unplaced logic cell, go to step 1. If not, end.

FIG. 2 is a schematic diagram showing the difference between the present method and the conventional method after the initial division. In the figure, circles represent logic cells,
Crosses indicate external terminals, thin solid lines indicate general signal lines, and thick solid lines indicate critical paths.

As can be seen from this figure, in the conventional method (b) in which no timing constraint is taken into account, the wiring length of the critical path tends to increase. However, if the method (a) is used, the path length of the critical path can be reduced.

For data of about 3000 cells,
FIG. 3 shows the result of executing the conventional method and the present method. The conventional method with a timing constraint uses a critical net multiplied by a net weight. In addition, a timing analysis was performed in a non-arranged state, and 61 critical paths were extracted.

In the figure, [1] is the ratio of the number of cuts straddling the first cut line, [2] is the ratio of the total wiring length, and [3]
Is the number of paths that have exceeded the timing specification.

As can be seen from [3], in the net weight method generally used in the past, there were 29 paths where the delay specification exceeded after the initial placement processing, but in this method, all paths satisfy the constraint. I was able to do it. In addition, the evaluation value of the arrangement of the number of cuts in [1] and the total wiring length in [2] was significantly reduced as compared with the previous method.

As described above, when the present method is used, the timing specifications can be satisfied without significantly deteriorating the number of cuts and the total wiring length even when a timing constraint is added.

[0037]

As described above, according to the method for arranging logic cells of the present invention, when allocating critical cells, the slack value of the critical net is taken into consideration, and the allocation to the area where the slack value is always positive is considered. Is performed, timing constraints can be finally satisfied. Further, since the number of cuts and the total wiring length can be reduced, the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a processing procedure of the present invention.

FIG. 2 is a schematic diagram comparing a state after initial division according to the present invention with a conventional state.

FIG. 3 is a table showing results of comparison between a conventional method and the present method.

Claims (1)

(57) [Claims] When a plurality of unplaced logic cells are initially placed in a divided placement area when an upper limit is set for a length of a critical net belonging to a critical path, Calculating the connection strength in each of the placement areas; temporarily assigning the unplaced logic cells to each of the placement areas; and calculating the virtual wiring length of each critical net connected to the unplaced logic cells. Calculating the slack value of each critical net from the virtual wire length and the upper limit value of each critical net length; and determining the slack value of the unplaced logical cell group having the smallest slack value. Selecting a placement logic cell; and selecting the selected unplaced logic cell in the placement area group where the slack value is positive or the slack value is maximum. Method of arranging logic cells continued strength, comprising the step of allocating the maximum placement area.