JP2803495B2 - Semiconductor integrated circuit wiring length prediction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring length estimating method for estimating a wiring length by floor planning for LSI timing design, and more particularly to a wiring length estimating method of a standard cell layout of a building block system.

[0002]

2. Description of the Related Art In conventional logic design, even when the layout of macrocells is reflected in the wiring length prediction by floor planning, as shown in FIG. 13,
Since the delay simulation is performed by estimating the wiring length of the predicted wiring 11 before wiring to the wirings 14, 15, and 16, and the position of the external terminal of the macro changes after performing the real wiring 20 as shown in FIG. In some cases, the wiring length may be significantly changed (IEICE Technical Report ICD90-7)
5).

[0003]

As described above, according to the conventional wiring length estimation based on floor planning, if the macro terminal positions are significantly changed after arranging and wiring the cells in the macro, the result of the actual layout results may be reduced. The accuracy of the delay simulation based on the wiring length prediction deteriorates. This tendency becomes more pronounced as the macro scale becomes larger. However, as the size of chips becomes larger and more detailed delay simulation becomes necessary as the submicron manufacturing process progresses, such inaccurate wiring length prediction is performed. Then, there is a problem that timing design becomes impossible.

An object of the present invention is to provide a method for estimating the wiring length of a semiconductor integrated circuit which improves the accuracy of the wiring length prediction.

[0005]

In order to achieve the above object, a method for estimating a wiring length of a semiconductor integrated circuit according to the present invention comprises:
A wiring length prediction method for a semiconductor integrated circuit for predicting a wiring length of a standard cell layout by performing a dimensional processing and a wiring length processing, wherein the dimensional processing calculates a chip size, a macro size in a chip, and a Manhattan distance between macros. When the estimated macro size is larger than the input error tolerance and the required accuracy cannot be obtained for the estimated wiring length, the wiring layer processing proceeds to the level of the macro until the required accuracy can be ensured. By lowering the group arrangement, the arrangement range of the cells in the macro and the external terminals is limited, and the predicted wiring length is obtained.

[0006]

When the macro size is large and the error between the predicted wiring length and the actual wiring length exceeds an allowable range, the wiring length is predicted after the macro is lowered and the groups are arranged.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing a wiring length prediction method according to one embodiment of the present invention. FIG. 2 is a chip-level macro layout diagram showing the layout of undesigned macros 12 and designed macros 16 and one wiring length predicted from connection information. FIG. 3 shows the result of actual layout with the arrangement of FIG.
FIG. 9 is a diagram illustrating an actual wiring length when a terminal position of an undesigned macro 12 has moved.

When the difference between the predicted wiring length in FIG. 2 and the actual wiring length in FIG. 3 becomes a problem, the present invention performs the following processing as shown in FIG. Within the allowable range. That is, in the floor planning 1 of the chip, the size of the chip 17 of FIG. 4 is predicted in the chip size prediction processing 2 and the designed macros 13, 14, 15, and 16 in the chip 17 are arranged in the hard macro placement processing 3. , A floor plan as shown in FIG. 2 is obtained.

The allowable error input processing 4 inputs the allowable error range of the wiring length in the chip 17, and the macro arrangement processing and size prediction processing 5 performs the arrangement and size prediction of the undesigned macro 12. For this predicted size, it is determined whether or not the condition input in process 4 is satisfied in check process 6,
If the macro size is within the error range, the wiring length of the predicted wiring 11 is calculated from the Manhattan distance between the macros 12 and 16 in the wiring length prediction processing 9 as it is. In this case, if it is out of the range, it is lowered by one layer by processing 7 and the inside of the undesigned macro is subjected to group division, size prediction and arrangement, and the size prediction of each group 18 is performed.

Next, in the check processing 8, it is determined whether or not each group 18 satisfies the condition of the allowable error range of the wiring length similarly to the check processing 6. If satisfied, the process proceeds to the wiring length prediction processing 9 to predict the wiring length of the predicted wiring 30 from the Manhattan distance between the group 18 and the macro 16 in the undesigned macro 31.

In the checking process 8, if it is determined that the group is out of the range, the process returns to the process 7, and the group is divided, arranged, and the size of each group is predicted in the lower hierarchy for that group. By repeating this, the wiring length is predicted in a state where everything is within the allowable range, and the delay simulation 10 is performed based on the predicted wiring length.

[0012]

As described above, according to the present invention, in the floor planning of a chip, when the size of a macro is large and the error between the predicted wiring length and the actual wiring length exceeds an allowable range, the macro hierarchy is lowered and the group is arranged. Since the wiring length prediction is performed after the above, the arrangement range of the cells in the macro and the external terminals of the macro in the actual layout is limited, and the accuracy of the wiring length prediction can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of the present invention.

FIG. 2 is a chip diagram when a terminal position of an undesigned macro is predicted based on an intra-chip macro arrangement and macro connection information to predict a wiring length.

FIG. 3 is a chip diagram showing actual wiring lengths after placement and wiring by a conventional method.

FIG. 4 is a chip diagram showing a case where a group is arranged in a lower hierarchy of an undesigned macro, a terminal position is predicted, and a wiring length is predicted.

[Explanation of symbols]

1 Floor Planning 2 Chip Size Prediction Processing 3 Hard Macro Placement Processing 4 Wiring Length Tolerance Input Processing 5 Undesigned Macro Placement and Size Prediction Processing 6 Checking if Estimated Macro Size is Error Permissible Range 7 Macro Size is Error Range If the number exceeds the limit, a process of lowering the hierarchy and performing group division, size prediction, and placement in the undesigned macro 8 A process of predicting the size of the divided group and checking whether the size is within an allowable error range 9 Wiring Length prediction processing 10 Delay simulation 12 Undesigned soft macros 13, 14, 15, 16 Hard macros already designed 17 Chips 18 Macro-divided groups 20 Actual wiring length after layout is executed by conventional method 30 Wiring after group placement in the undesigned macro by the method of 31 Group division in the lower hierarchy Ming manner, arranged non-designed macros

Claims (1)

(57) [Claims] 1. A wiring length prediction method for a semiconductor integrated circuit for predicting a wiring length of a standard cell layout by performing dimensional processing and wiring length processing, wherein the dimensional processing includes a chip size, a macro size in a chip,
Calculates the Manhattan distance between macros. Wiring length processing can secure the required accuracy when the estimated macro size is larger than the input error tolerance and the required accuracy cannot be obtained for the predicted wiring length. A method for estimating a wiring length of a semiconductor integrated circuit, wherein a macro wiring is reduced to a level and group arrangement is performed, thereby limiting the arrangement range of cells in a macro and external terminals and obtaining a predicted wiring length.