JPH0677323A - Automatic layout system - Google Patents

Abstract

PURPOSE:To provide an automatic layout system that can automatically process automatic layout wiring having small wiring capacity at high speed, in an automatic layout system for an IC that requires a high operation frequency. CONSTITUTION:An automatic layout system comprises: a circuit diagram file 12 that houses a circuit diagram of an IC; an automatic layout wiring system 1 that carries out automatic layout wiring from a layout cell 11 corresponding to gates constituting the circuit diagram; a cell/net detecting system 2 that detects connections between the layout cell and lines from a result of the layout wiring; and an unnecessary aluminum removal system 3 which removes an unnecessary line on the cell in the layout wiring from the detection result of the cell/net detecting system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout system, and more particularly to an automatic layout system for ICs which requires a high operating frequency.

[0002]

2. Description of the Related Art As shown in FIG. 8, a conventional automatic layout system 10 which requires high-speed operation uses a delay simulation system 20. In the automatic layout system 10, the automatic placement and wiring 13 is performed based on the information from the layout cell 11 and the circuit diagram file 12 to calculate the wiring capacitance 14 after the layout.

A delay simulation 22 is carried out based on the wiring capacitance 14, the circuit diagram of the technology file 21, and the data of the current supply capacity for the load of the gate.
When the result 23 of this simulation is NG (defective), the wiring at the speed neck portion is shortened again,
Automatic placement and routing is performed, and the wiring capacitance and delay simulation after this routing are performed.

The automatic placement and routing is repeated until the delay simulation result is OK (good), and layout data is obtained.

Further, in order to reduce the wiring capacity as much as possible, unnecessary wirings, mainly aluminum wirings on the cells of the layout corresponding to the gates, are manually deleted from the layout data 15 after the layout.

[0006]

In the above-mentioned conventional automatic layout system requiring high-speed operation, the result of the delay simulation may be NG even if the automatic placement and routing is repeated many times. In order to reduce the number of problems, it is necessary to manually remove unnecessary aluminum wiring, which causes problems such as occurrence of mistakes and increase in man-hours.

Therefore, a technical object of the present invention is to provide an automatic layout system capable of automatically performing high-speed processing for automatic placement and routing with a small wiring capacity.

[0008]

In order to solve the above problems, the automatic layout system of the present invention has the following (1)
Alternatively, it has any one of the configurations of item (2). (1) A circuit diagram file containing a circuit diagram of an IC, an automatic placement and routing system for automatically placing and routing from layout cells corresponding to gates forming the circuit diagram, and a layout cell based on the result after placement and routing. It is characterized by having a cell / net detection system that detects the connection part of wiring, and an unnecessary aluminum deletion system that deletes wiring on cells that are unnecessary in the layout wiring based on the detection result of this cell / net detection system. . (2) In the above item (1), the cell net detection system detects from the connection information of the cells of the automatic placement and routing whether or not the wiring connects one of the four contacts. And

[0009]

In the present invention, unnecessary aluminum wiring is automatically deleted after automatic placement and wiring.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram of an automatic layout system according to a first embodiment of the present invention. As shown in FIG. 1, the automatic placement and routing system 1
Lays out the chip based on the information from the circuit diagram file of the IC and the layout cell of the gate.

Next, the cell net detection system 2 outputs cell net connection information from the data after the automatic placement and routing.

Next, the unnecessary aluminum removing system 3
Unnecessary aluminum is deleted from the net connection information to complete the layout data.

The above is an outline of the processes in the automatic layout system, and the contents of each process will be described in more detail below.

First, the contents of the automatic placement and routing system 1 for laying out a chip from the IC circuit diagram file and the layout data of the layout cells corresponding to the gates forming the circuit diagram will be described.

FIG. 2 is a diagram showing a gate of a 2-input NAND element, FIG. 3 is a diagram showing a layout cell of a 2-input NAND element, and FIG. 4 is a diagram showing cell data which is an input of an automatic layout of a 2-input NAND element.

Basically, the cell data shown in FIG.
It contains the outline of the cell indicating the size of the layout cell and the coordinates indicating the position of the input / output pin.

As shown in FIG. 3, the 2-input NAND element includes a first aluminum, a second aluminum, a polysilicon, a polysilicon-first aluminum contact, a first aluminum-second aluminum contact, a diffusion layer-first aluminum contact, It has a diffusion layer and the like.

In FIG. 3, the two gate inputs and the drain output of the NAND element are from the first aluminum-second aluminum contact, the second aluminum is running up and down on the cell, and the input / output signals are up and down the cell. It can be taken out from either side.

Automatic placement and routing system 1 at this stage
Automatically arranges layout cells based on the circuit diagram data and layout cell data, and also automatically performs wiring between cells. However, when wiring is performed, as shown in FIG. Two contacts for signals, eg 1NO
Since there are (A) and 1NO (B), either one can be connected.

Next, the contents of the cell net detection system 2 will be described. In this cell net detection system, it is detected from the connection information of the cell after automatic placement and routing whether the wiring connects one of the two contacts.

As a result, cell / net connection information indicating which contact is connected to each of the cells for which automatic placement and routing has been performed is output. An example thereof is shown in FIG.
FIG. 5 shows the contacts corresponding to the input / output pins of each element.

Next, the unnecessary aluminum removing system 3 will be described. FIG. 6 is a diagram in which only the second aluminum wiring is taken out and placed in the layout of the 2NAND element shown in FIG. As can be seen from FIGS. 3, 5 and 6, the second
Two types of aluminum wiring are registered, and the second aluminum wiring from the A side contact of each I / O pin to the first aluminum-second aluminum contact is the A side contact second aluminum and the B side contact is the first aluminum second The second aluminum wiring up to the aluminum-to-aluminum contact is the B-side contact second aluminum. The above second aluminum wiring is reflected in the layout cell.

Subsequently, the unnecessary second aluminum wiring on the layout cell is selected from the cell net connection information output from the cell net detection system 2 and is deleted.
For example, assuming that the contact of the input pin INO of the 2NAND having the element name NR2 is B in FIG. 5, the second contact on the A side of the aluminum wiring of the INO on the layout cell of the 2NAND in FIG.
Remove the aluminum.

As described above, by removing the unnecessary second aluminum, the wiring capacity is reduced and high-speed operation is facilitated. For example, in FIG. 6, the second contact on the A side of the input pin INO
When aluminum is removed, it decreases by 0.025 pF, and when several of them are combined, the capacitance of 0.1 pF or more is cut, the operation speed becomes about 2 ns, and the effect is remarkably exhibited in the critical net. (Second Embodiment) In the first embodiment, which has already been described, the second aluminum on the layout cell runs vertically, but in the second embodiment of the present invention, the second aluminum is not limited to the top and bottom but the four directions of the cell. It has become possible to run in a high degree, and the degree of freedom in automatic wiring is high.

Instead, the layout is automatically arranged horizontally by the building block method in the first example, whereas in this example, a large cell such as a macro cell is automatically arranged and wired on the chip.

The layout data of the macro cell used in the second embodiment is shown in FIG. However, in FIG. 7, only aluminum wiring and signal names are specified. As shown in FIG. 7, each input / output pin has four contacts (A side, B side, C side, D side).

In the second embodiment of the present invention, the automatic placement and routing system 1 connects any one of the four, and the cell net detection system 2 detects which contact is connected. Further, the unnecessary aluminum deleting system 3 deletes the aluminum wiring on the side not connected.

[0028]

As described above, according to the present invention,
Unnecessary aluminum wiring is automatically deleted from the data after automatic placement and wiring, thereby reducing the wiring capacity and eliminating mistakes due to manpower and increase in man-hours.

[Brief description of drawings]

FIG. 1 is a block diagram of an automatic layout system according to a first exemplary embodiment of the present invention.

FIG. 2 is an explanatory diagram of a gate of a 2-input NAND element according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a layout cell of a 2-input NAND element according to the first embodiment of the present invention.

FIG. 4 is a diagram showing cell data of a 2-input NAND element according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of cell-net connection information according to the first embodiment of the present invention.

FIG. 6 is a diagram showing only the second aluminum wiring in the layout of the 2NAND element according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating layout data of a macro cell according to a second embodiment of the present invention.

FIG. 8 is a block diagram including an automatic layout system that requires a conventional high-speed operation.

[Explanation of symbols]

 1 Automatic Place and Route System 2 Cell / Net Detection System 3 Unnecessary Aluminum Removal System 10 Automatic Layout System 11 Layout Cell 12 Schematic File 13 Automatic Place and Route 14 Wiring Capacity 15 Layout Data 20 Delay Simulation System 21 Technology File 22 Delay Simulation 23 Results

Claims (2)

[Claims] 1. A circuit diagram file containing a circuit diagram of an IC, an automatic placement and routing system for automatically placing and routing a layout cell corresponding to a gate forming the circuit diagram, and a layout based on a result after the placement and routing. A cell net detection system that detects the connection between cells and wiring
An automatic layout system characterized by having an unnecessary aluminum deleting system for deleting unnecessary wiring on a cell in a wiring on a layout based on a detection result of a net detection system. 2. The automatic layout system according to claim 1, wherein the cell net detection system determines that among the four contact points, the wiring is based on the cell connection information of the automatic placement and wiring.
An automatic layout system characterized by detecting whether one of them is connected.