JP3398710B2 - General-purpose memory macro processing apparatus and general-purpose memory macro processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose memory macro conversion processing device and a general-purpose memory macro conversion processing method.

[0002]

2. Description of the Related Art Demand for silicon-on-chip has been increasing in recent years, and future expectations for ASIC products equipped with memories are great.

Currently, the main use is a sound skip prevention function for CD and MD players, etc., and a small memory capacity is sufficient, but in the future, a large amount of memory (corresponding to a general-purpose memory) for image processing, voice recognition, etc. will be required. There is expected to be demand for a silicon-on-chip embedded with DRAM memory.

Therefore, there is a demand for a technique for mounting a general-purpose memory as a large-scale memory macro on an ASIC chip by using the conventional technique.

[0005]

However, the conventional technique has the following problems.

The first problem is that the layout is changed and the development TAT becomes enormous. The reason is that the input / output terminals of the general-purpose memory are connected to the outside by bonding via a lead frame. Therefore, when the general-purpose memory is mounted on the ASIC chip as it is, the input / output terminals of the general-purpose memory cannot be connected because the design is not made considering the area for wiring the signal wiring (hereinafter, LOGIC signal) on the ASIC side.

As a solution to this problem, considering that the conventional mega macro design technique is used to connect the LOGIC signal line, as shown in FIG. 8, a general memory input / output terminal can be connected to the LOGIC signal at a position (side surface). A layout change to move to (draw out) can be considered.

However, the second problem here is that a huge number of TATs are required to change the layout from the general-purpose memory, and a buffer is added on the memory side by moving (drawing) the terminal to the side surface. However, it is necessary to re-simulate the circuit in the memory, and the worst problem is that the same characteristics as the general-purpose memory cannot be guaranteed.

FIG. 7 shows a layout / wiring processing flow having the above contents. General-purpose memory layout data creation (6
After 1), it is determined whether the mask pattern database (62) is used as a general-purpose memory or a memory macro (63), and when it is used as a general-purpose memory, the process is terminated (64). ASIC as a memory macro
In case of mounting on the board, the data of the mask pattern database that arranges the input / output terminals on the side so that it can be connected to the ASIC signal is changed (65), and the circuit connection information (66) and the automatic placement and routing database (67) are used to automatically The placement and routing (69) and the merge process (70) are performed, and the process ends (7
1) Do.

Further, instead of the mega-macro design technique of arranging the general-purpose memory input / output terminal on the side surface, the general-purpose memory input / output terminal, ESD
It is conceivable to delete the area by changing the element layout and use the deleted area as a layout wiring area between the general-purpose memory macro and the LOGIC.

However, as a third problem, this method requires a memory macro after the layout change to LOGIC.
There is a problem that waste occurs in the inter-wiring area. The reason is that the maximum number of used IOs is 16 (hereinafter referred to as × 16), and the number of used IOs is 8 and 4 (hereinafter referred to as × 8 and × 4).
It will be explained by using the case where it is variable. When using the input / output terminal (PAD) of the general-purpose memory and the ESD element arrangement area as the arrangement wiring between the general-purpose memory macro and LOGIC, the area including the maximum number of used IOs, in this case 16IOs, and the margin for automatic wiring is secured. It becomes a memory macro. However, when the number of used IOs in the memory macro is 4 (hereinafter referred to as x4), 16-4 = 12 (Equation 11) This 12 IO memory macro-LOGIC wiring area is left. Considering a large-scale DRAM memory with a memory capacity of 128 M, the long-side direction is approximately 10 mm (10000 μm).
m), when the automatic wiring grid has a pitch of 0.56 μm 0.56 μm × 12 IO = 6.72 μm (Equation 12) 6.72 μm × 10000 μm = 67200 μm 2 (Equation 13) UnitCellSize on the LOGIC side is 9.3 μm 2. In this case, the area in which 67200 μm 2 ÷ 9.3 μm 2 = about 7225 unit cells (Formula 14) can be arranged is wasted. As a solution to the above contents, each number of used IOs (3 macros in total)
It is possible to create a memory macro.

However, as a fourth problem, data management becomes complicated.

[0013]

A general-purpose memory macro conversion processing device of the present invention stores layout data of general-purpose memory, including layout data of a predetermined element and a predetermined wiring portion which are unnecessary as a memory macro. It has a database means, a selection means for selecting whether the database data is used as a general-purpose memory or a memory macro, and setting means for setting an area between the memory macro and the logic when the database data is used as a memory macro. Is characterized by.

The setting means obtains the number of automatic wiring grids between the memory macro and the logic from the number of terminals and the number of buffers of the memory macro, and arranges and wires the memory macro by leaving an area for the number of grids. , A means for determining the number of grids used for wiring in the left and right boundary portions of the memory macro, and a means for setting and arranging a large number of the calculated number of grids as the memory macro and logic automatic wiring grid number .

A general-purpose memory macro processor according to the present invention is
Database means for storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring portion which are unnecessary as a memory macro, and whether the database data is used as a general-purpose memory or a memory macro Is selected and used as a memory macro, it is characterized by having wiring means for wiring the logic section after deleting the unnecessary layout data.

The general-purpose memory macro processing method of the present invention is
A step of storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring part unnecessary as a memory macro, and whether the database data is used as a general-purpose memory or a memory macro. It has a selecting step of selecting and a setting step of setting an area between the memory macro and the logic when used as a memory macro.

In the setting step, a step of obtaining an automatic wiring grid number between the memory macro and the logic from the number of terminals and the number of buffers of the memory macro, and arranging and wiring the memory macros by leaving an area for the number of grids , A step of obtaining the number of grids used for wiring at the left and right boundary portions of the memory macro, and a step of setting and arranging a large number of the obtained number of grids as a memory macro and an automatic wiring grid number between logics .

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor integrated device and a general-purpose memory macro processing method according to the present invention enable a LOC (read-on-chip) type general-purpose memory to be used in advance as an ASIC memory macro when creating layout data.
A semiconductor integrated device having a layout configuration capable of removing unnecessary parts according to a processing flow when created as a layout having a hierarchy capable of removing unnecessary parts and used as an ASIC memory macro, and all terminals of used memory macros Number, buffer number, memory macro ~ L
After determining the number of automatic wiring grids between OGICs, placing and allocating memory macros for the wiring grids, and after wiring, find the number of grids used for wiring at the left and right boundaries of the memory macros, and the larger number is the automatic wiring grid between memory macros and LOGICs. Optimal memory macro characterized by the number and setting, and re-arranging and wiring ~ L
This is a general-purpose memory macro processing method for obtaining an inter-OGIC area.

First, the features of the layout configuration will be described. FIG. 1B is an enlarged view of the layout configuration according to the basic embodiment of the present invention, which is an enlarged view of 8 parts of FIG.

In FIG. 1B, the PAD 1, the ESD element 2, the input / output signal wiring 3, and the passing signal wiring 4 are arranged in a cell data hierarchy that can be collectively deleted, so that the input / output signal line 3 after batch deletion of cell data is performed. Is, as shown in FIG.
It exists only at the edge 5 of the block placement area. As shown in FIG. 1B, the input / output signal line 3 exists at the edge 5 of the block arrangement area after the cell data is collectively deleted.
Further, the pass signal wiring 4 passing vertically between the block arrangement areas (1) and (2) on the paper surface also has a cell data structure that can be collectively deleted in the same manner as described above. The signal wiring portion included in the block arrangement area (1), the signal wiring portion included in the block arrangement area (2), and other portions (target area this time: PAD, ESD element, input / output signal in FIG. 1C) Wiring and passage signal wiring cell arrangement area 8) can be divided into three parts and separated. No data other than the above-mentioned data is arranged in these areas.

By using the processing method shown in FIG. 2 in the layout configuration having the above characteristics, the optimum memory macro to LO
The feature is that macroscopic processing is performed by obtaining the inter-GIC area.

In FIG. 2, it is judged (11) whether the mask pattern database (14) created in advance with a layout configuration having the above characteristics is used in a general-purpose memory or a memory macro, and is used as a general-purpose memory. If so, the layout data is used as it is (12), and the process is ended (13).

When used as a memory macro, circuit connection information (15), automatic placement and routing database (16)
Is used to obtain the number of automatic wiring grids between the memory macro and LOGIC from all terminals of the memory macro used and the number of buffers. (1
7) Next, the area between the memory macro and the LOGIC and the total area for buffer placement are obtained (18).

Next, the area between the memory macro and the LOGIC is compared (19) with the total buffer arrangement area. If the total area of the buffer arrangement is large, the area between the memory macro and the LOGIC is made larger than the total buffer arrangement area. An area between the memory macro and the LOGIC is added with a wiring grid in two steps (20), and the process returns to (19). Memory macro ~ L
If the inter-OGIC region is large, the process proceeds to (21) for creating an automatic placement and routing database.

Next, it is judged whether the area has been optimized (22). The judgment criterion is based on the comparison between the memory macro-LOGIC area initially obtained in the processing of (18) and the memory macro-LOGIC area after the processing of (19). (1
If the area after the processing in 9) is larger than or equal to the area obtained in the processing in (18), optimization is not completed. If it is smaller, it is determined that optimization is completed.

When it is judged in the process of (22) that the optimization has not been completed, after the automatic placement and routing (23), the number of grids used in the wiring is obtained at the left and right boundaries of the memory macro, and a large number is automatically set between the memory macro and the LOGIC. After setting (24) the number of wiring grids, the process returns to (19) described above to continue the processing.

When it is judged that the optimization of the area is completed, after the automatic placement and routing (25), the mask pattern is merged (2
6) Then, all the processing ends (27). With the processing method having the above characteristics, the optimum memory macro-LOGI
Placement and wiring can be performed in the signal area between Cs.

As shown in FIG. 1B, the input / output signal line 3 is present at the edge 5 of the block arrangement area after the cell data is collectively deleted. Further, the pass signal wiring 4 passing vertically between the block arrangement areas (1) and (2) on the paper surface also has a cell data structure that can be collectively deleted in the same manner as described above. Block placement area (1)
Signal wiring portion included in, the signal wiring portion included in the block placement area (2) and other portions (target area this time: PAD, ESD element, input / output signal wiring, passing signal wiring cell in FIG. 1A) It can be separated by dividing it into three placement areas 8).

By the way, the automatic placement and routing database (1
In 6), in addition to the automatic placement / wiring database for ASIC, a wiring prohibited area having the same size as the general-purpose memory, data having input / output terminals, PAD in the general-purpose memory, and ESD arrangement area size are provided. The automatic wiring prohibited area is the memory cell portion including the peripheral circuit of the general-purpose memory, and the input / output terminals are provided near the PAD position in the general-purpose memory.
In FIG. 1B, the block placement area edge 1 of the block placement area (1) or the block placement area (2) in which the initial block is placed.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

3 to 5 show a general-purpose memory macro processing method according to an embodiment of the present invention.

As a specific example of application, the number of used IOs is 16 (×
16), 34 other terminals, 50 total I / O terminals
It is assumed that a general-purpose memory for terminals is mounted on an ASIC chip.

In FIG. 3, a mask pattern database (14) of a general-purpose memory, which is created in advance so that it can be changed to a memory macro, is used to determine (11) whether to use as a general-purpose memory or a memory macro.

If it is determined that the memory macro will be used, a process for reading the circuit connection information (15) and the automatic placement and routing database (16) is started.

The case where it is determined that the mask pattern database is used as a general-purpose memory will be described. The mask pattern database is used 12 as it is, and the process is ended 13.

The description will be continued assuming that the memory macro is used.

After reading (37) the circuit connection information (15) and the automatic placement and routing database (16), the used configuration of the memory macro and the number of used IOs are retrieved (38) from the read information. The number of IOs used is the circuit connection information (15)
This is done by searching for the number of output terminals written in the connection description of the memory macro part. IO used in this example
The number is 16 terminals.

Next, the total number of grids between the memory macro and LOGIC is calculated (39). The total number of grids is calculated by adding the number of used IOs and the number of other memory macro used terminals. In this example, it is calculated as 16 + 34 = 50 (Equation 1). Next, the number of buffers arranged between the memory macro and LOGIC and its area are obtained. (40) The number of buffers is searched from the buffer circuit connected to the previous stage of the memory macro in the circuit connection information (15). The area is derived from the cell configuration of the automatic placement and routing database, and finally the total used area is calculated from the total number of used buffers.

For example, the area per buffer is 10 μm.
If m2 and the total number of used buffers are 100, then 10 μm2 × 100 = 1000 μm2 (Equation 2). Next, moving to FIG. 4, the area between the memory macro and the LOGIC is obtained. (41) The formula to be obtained is the short side between the memory macro and the LOGIC = (total number of signals between the memory macro and the LOGIC) × (wiring pitch described in the automatic placement and wiring database) (Equation 3) memory macro to the LOGIC Therefore, the long side between the memory macro and the LOGIC = the short side between the memory macro and the LOGIC × the long side between the memory macro and the LOGIC (equation 5).

This time, the wiring grid pitch described in the automatic placement and routing database is 0.56 μm, the memory macro long side length is 10000 μm, and the memory macro short side length is 40.
If the short side size of the PAD / ESD arrangement area in the general-purpose memory is 200 μm, the short side between the memory macro and LOGIC = 50 lines × 0.56 μm = 28 μm (Equation 6) The long side between the memory macro and LOGIC = 10000 μm (Equation 7) Area between memory macro and LOGIC = 28 μm × 10000 μm = 280000 μm 2 (Equation 8)

The obtained memory macro-LOGIC area is compared with the previously obtained buffer placement total area (19),
If the area between the memory macro and LOGIC is larger, the process proceeds to the next process (42). If the total area for buffer arrangement is larger, the area between the memory macro and LOGIC is made larger than the area between the memory macro and LOGIC. The wiring grid is added (20) to the area between the macro and the LOGIC in two steps, and the process returns to (19). The purpose is to secure the area necessary for arranging the buffer blocks.

Next, in order to perform automatic placement and routing, a memory macro automatic placement and routing database reflecting the obtained memory macro-LOGIC area is created (42). The contents of the memory macro automatic placement and routing database are as described above, and the description is omitted.

First, the basic memory macro automatic arrangement / wiring data existing above 1/2 of the height direction (memory macro short side length) of the basic memory macro automatic arrangement / wiring data is
The area is moved by a value obtained by subtracting the size of the short side of the memory macro-LOGIC area previously obtained from the size of the short side of the PAD / ESD arrangement area in the general-purpose memory. Here, since the short side length of the memory macro is 4000 μm and the short side size of the PAD / ESD arrangement area in the general-purpose memory is 200 μm, 4000 μm / 2 = 2000 μm (Equation 9) 200 μm-28 μm = 172 μm (Equation 10) , 2000 μm in the basic memory macro automatic placement and routing data existing above 1/2 of the height direction (memory macro short side length) of the basic memory macro automatic placement and routing data
172μ in the height direction only for data with larger values
Subtract m minutes.

Further, the mask pattern database 14
The passing signal wiring 4 passing vertically between the block areas (1) and (2) in FIG. 1B in the figure is also adjusted. In the adjustment, the length in the vertical direction on the paper surface of the wiring cell data divided into three at the edge 5 of the block arrangement area in FIG. 1B is the area between the memory macro and the LOGIC obtained by (Equation 6). The short side size length is 28 μm in this case.

Next, it is judged whether the area is optimized (22).
Then, proceed to automatic placement and routing. Since the judgment criteria have been described above, the description thereof will be omitted here. Since it is not optimized at the beginning, the process proceeds to automatic placement and routing processing for optimization. After the arrangement of memory macros (43), the buffer arrangement in the memory macro-LOGIC area (44), and the memory macro-LOGIC area allocation prohibition definition (45),
The arrangement of other LOGIC blocks (46) and the priority wiring (47) between the memory macro and LOGIC are performed in this order.

After the priority wiring between the memory macro and the LOGIC is completed, the number of signal wirings passing through these boundary portions is counted at the memory macro right side boundary portion 11 and the memory macro left side boundary portion 12 shown in FIG. The side with the largest number is set as the number of automatic placement / wiring grids between the memory macro and LOGIC (2
4) Do. This is the optimization area.

For example, the number of signal wirings passing through the boundary portion 11 on the right side of the memory macro is 10, and the boundary portion 12 on the left side of the memory macro.
If the number of signal wires passing through is 40, the memory macro
The number of automatic placement and routing grids between LOGICs is 40.

After the optimization area is determined, the memory macro to LOG
Compare IC area is larger than total buffer area (19)
If there is a problem, the area between the memory macro and the LOGIC is added (20) in two steps so that the area between the memory macro and the LOGIC is larger than the area between the memory macro and the LOGIC, and the process returns to step (19). . If there is no problem, create a memory macro automatic placement and routing database (4
Repeat step 2). In this example, from (Equation 8), the area between the memory macro and the LOGIC is 280000 μm 2,
From (Equation 2), the total buffer area is 1000 μm 2, and the process of adding the wiring grid is not performed.

Next, it is judged whether the area between the memory macro and the LOGIC is optimized (22). Since it is optimized, the process proceeds to the final placement and wiring.

Similar to the layout and wiring performed first, the memory macro-LOGIC area is optimized to have a memory macro layout (48), the memory macro-LOGIC area is provided with a buffer (49), and the memory macro-LOGIC area is allocated. After the placement prohibition definition (50), the other LOGIC blocks are placed (51), the priority wiring between the memory macro and the LOGIC (52), the priority wiring is fixed (53), and the other wiring is performed (54), and the placement is performed. The wiring result output (55) and the mask pattern database are merged (26), and the process ends (27).

According to the present invention, when the layout of the general-purpose memory is created, it is created beforehand as a layout having a hierarchy in which unnecessary parts can be removed as the ASIC memory macro, and when it is used as the ASIC memory macro, it is unnecessary according to the processing flow. Although the processing method that can remove the part was explained, conversely, when creating the layout of the ASIC memory macro, it is created as a layout configuration that can take in the necessary parts as the general-purpose memory in advance, and the processing when using it as the general-purpose memory The method will be described.

FIG. 10 shows a processing method of the above contents. Here, the layout configuration capable of preliminarily incorporating the necessary components as the general-purpose memory can be considered in the reverse manner of the layout configuration of the present invention, and thus the description thereof will be omitted.

In FIG. 10, it is judged (11) whether the mask pattern database (14) created in advance with a layout configuration having the above characteristics is used as a general-purpose memory or a memory macro, and is used as a memory macro. In this case, the layout data is used as it is (12), and the automatic placement and routing (2) is performed using the circuit connection information (15) and the automatic placement and routing database (16).
5) is performed, the merge process (26) is performed, and then the process ends (27).

When used as a general-purpose memory, PAD, ESD previously described in the database (81)
The element, the input / output signal wiring, and the passage signal wiring cell arrangement area size are read (82), the area is expanded by the read size, and the PAD, the ESD element, the input / output signal wiring, and the passage signal wiring cell are arranged (83) and processed. Ends (13).

[0055]

The first effect is that when a general-purpose memory layout is used as a memory macro that can be mounted on an ASIC, it has a layout configuration in which unnecessary parts can be removed in advance, and it is also used as a memory macro. In such a case, the development TAT due to the layout change does not occur because it is automatically created according to the processing flow.

The second effect is that the circuit is connected to the signal wiring on the ASIC side at the same position as in the general-purpose memory, so that the circuit simulation is not necessary on the memory side again, and the same specifications as the general-purpose memory can be obtained.

The third effect is that since the automatic placement and routing area can be made variable depending on the memory configuration and the number of used buffers, no waste occurs in the placement and routing area between the memory macro and LOGIC, and depending on the IO configuration used, the LOGIC placement area can be used. Can be increased over conventional macros.

The fourth effect is that since it is not necessary to create and register a mask pattern for each IO configuration used, data management can be facilitated.

[Brief description of drawings]

FIG. 1 is an enlarged view of a general-purpose memory layout configuration according to a basic embodiment of the present invention.

FIG. 2 is a diagram showing a flow of a general-purpose memory macro processing method according to a basic embodiment of the present invention.

FIG. 3 is a diagram showing a flow of a general-purpose memory macro processing method according to an embodiment of the present invention.

FIG. 4 is a diagram showing a flow of a general-purpose memory macro processing method according to an embodiment of the present invention.

FIG. 5 is a diagram showing a flow of a general-purpose memory macro processing method according to an embodiment of the present invention.

FIG. 6 is a diagram showing a flow of a general-purpose memory macro processing method according to an embodiment of the present invention.

FIG. 7 is a diagram showing a flow of a general-purpose memory macro conversion processing method according to a conventional example.

FIG. 8 is a diagram showing a macro connection according to a conventional example.

FIG. 9 is a diagram showing a memory macro.

FIG. 10 is a diagram showing a flow of a processing method according to another embodiment of the present invention.

[Explanation of symbols]

1 PAD 2 ESD element 3 I / O signal wiring 4 Passing signal wiring 5 Block placement area edge 6 memory cells 9 I / O terminals

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 27/10 H01L 27/04

Claims (8)

(57) [Claims] 1. A database means for storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring portion which are unnecessary as a memory macro, and whether or not the database data is used as a general-purpose memory. A general-purpose memory macro conversion processing device having a selection means for selecting whether to use as a macro and a setting means for setting an area between the memory macro and the logic when used as a memory macro. 2. The setting means obtains the number of automatic wiring grids between the memory macro and the logic from the number of terminals and the number of buffers of the memory macro, and arranges the memory macro to leave an area for the number of grids. Means for arranging and determining the number of grids used in wiring at the left and right boundary portions of the memory macro; and means for setting and arranging a large number of the calculated number of grids as the memory macro and logic automatic wiring grid number 2. The general-purpose memory macro conversion processing device according to claim 1, comprising: 3. The general-purpose memory macro conversion processing device according to claim 1, further comprising means for directly using the data of the database as a mask pattern of the general-purpose memory when the data is selected by the selecting means as a general-purpose memory. 4. A database means for storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring portion unnecessary as a memory macro, and whether the database data is used as a general-purpose memory or a memory. A general-purpose memory macro conversion processing device having wiring means for selecting whether to use as a macro and, when using as a memory macro, deleting the unnecessary layout data and then wiring to a logic section. 5. A step of storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring part which are unnecessary as a memory macro, and whether the database data is used as a general-purpose memory or a memory macro. A general-purpose memory macro conversion processing method comprising: a selection step of selecting whether to use as a memory macro and a setting step of setting an area between the memory macro and the logic when used as a memory macro. 6. The setting step includes the step of obtaining an automatic wiring grid number between the memory macro and the logic from the number of terminals and the number of buffers of the memory macro; Wiring and determining the number of grids used in the wiring at the left and right boundary portions of the memory macro, and a step of setting and allocating a large number of the obtained number of grids as the number of memory macro and logic automatic wiring grids The general-purpose memory macro processing method according to claim 5, further comprising: 7. The general-purpose memory macro conversion processing method according to claim 5, further comprising the step of using the data of the database as it is as a mask pattern of the general-purpose memory when it is selected to be used as a general-purpose memory in the selecting step. 8. A step of storing layout data which is layout data of a general-purpose memory and also includes layout data of a predetermined element and a predetermined wiring portion which are unnecessary as a memory macro, and whether the database data is used as a general-purpose memory or a memory macro. A general-purpose memory macro conversion processing method, which comprises a wiring step of performing wiring with a logic part after deleting the unnecessary layout data when selecting whether to use as a memory macro and using as a memory macro.