JPH09232436A - Method and apparatus for logic synthesis, and method for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the design period of a semiconductor integrated circuit. SOLUTION: In a logic synthetic operation, a circuit at a gate level is generated in units of blocks. After that, (1) the size of every block is decided on the basis of the total area of a cell inside the block or on the basis of the number of gates, and the block in the size is arranged inside a floor. Then, (2) the cell is arranged approximately inside the block, and cells at the inside and the outside of the block are wired globally. Then, (3) the number of interconnections between blocks, a part in which a wiring density is at a set value or higher and a critical path passing a plurality of blocks in a semiconductor integrated circuit are displayed. Then, (4) when it is judged that a correction is required by looking at a displayed result, a floor planning operation to be returned to (2) is performed after every block is resized or moved. The length of a shortest route connecting centers of gravity of different blocks by using a line parallel to the side of the floor is found as a virtual wiring length between cells in the different blocks so as to be used for a wiring adjustment. The result of the floor planning operation is used to design a layout.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis method and device, and a semiconductor integrated circuit design method.

[0002]

2. Description of the Related Art In automatic design of a semiconductor integrated circuit, a gate-level circuit is generated by inputting the function and structure specifications of the semiconductor integrated circuit described in HDL (Hardware Description Language) to a logic synthesis tool. To be done. The generated circuit is layout-designed using an automatic placement and routing tool.

In order to reduce the timing error after layout design, the logic synthesis tool automatically determines whether or not the drive input of the cell is insufficient based on the sum of the virtual wiring capacitance between cells and the input capacitance of the cell. If it is determined that the cell driving ability is insufficient, a driver cell is inserted between the cells. Since it is before the layout design, FIG. 8 (A)
The inter-cell virtual wiring capacity can be estimated from the relationship shown in. The horizontal axis represents the gate size of the block, and the vertical axis represents the virtual wiring capacity between cells in the block. For example, FIG.
The number of gates of blocks A and B shown in FIG.
A and NB, and the virtual wiring capacitance between cells in each block is the virtual wiring capacitance C1. In this case, cell 1 in block A and cell 2 in block B
The virtual capacitance of the wiring 3 between (the positions of the cells 1 and 2 in the block are not determined) is N gates in FIG.
It is estimated as the virtual wiring capacity C2 between cells in the block S of S = NA + NB. When the sum C2 + Ci of the virtual wiring capacitance C2 of the wiring 3 and the input capacitance Ci of the cell 2 exceeds the driving capability of the cell 1, the driver cell is inserted in the wiring 3. Further, the buffer cell is inserted or the cell size (cell input capacitance) is changed so that the signal propagation delay time between the terminals designated at the design stage falls within the allowable range.

By such processing, the timing error after layout design is reduced.

[0005]

However, due to miniaturization of circuit elements, the capacitance ratio = (inter-cell wiring capacitance) / (cell input capacitance) becomes large, and this ratio is almost the same in an LSI having a wiring width of 0.5 μm. Becomes 1. The larger the capacitance ratio, the larger (virtual wiring capacitance)-(real wiring capacitance), the virtual wiring capacitance becomes inaccurate, and the timing error after layout design increases. Partially modifying the circuit to eliminate timing errors in one part affects the timing in another part. Therefore, it is necessary to repeatedly modify the circuit structure described in HDL (insert drive cells for timing adjustment), logic synthesis, and layout design, which causes a long design period.

In view of such problems, an object of the present invention is to provide a logic synthesizing method and device and a semiconductor integrated circuit designing method which can shorten the design period of the semiconductor integrated circuit.

[0007]

According to the present invention, a specification of a semiconductor integrated circuit described in a hardware description language (HDL) is used as an input, a gate level circuit is generated in block units, and virtual wiring is performed. A logic synthesis method of determining whether or not the driving capability of the cell is insufficient based on the sum of the capacitance and the input capacitance of the cell, and inserting a driver cell between the cells when determining that the cell driving capability is insufficient. After generating the gate level circuit and before the determination,
Perform floor planning to determine the placement of the block,
The length of the shortest path connecting the centers of gravity of different blocks with a line parallel to the side of the floor corresponding to the chip area is obtained as the virtual wiring length between cells of different blocks, and the virtual wiring capacity between cells of different blocks Is calculated based on the virtual wiring length.

According to the present invention, the floor wiring at the logic synthesis stage makes the virtual wiring capacitance between cells of different blocks more accurate than before, so that the timing adjustment is performed more accurately and the timing after the layout design is performed. The number of errors has been reduced and the circuit specifications written in HDL have been corrected.
The number of times of repeating logic synthesis and layout design is reduced, and the design period is shortened.

Further, for the same reason, the number of driver cells to be inserted is reduced as compared with the prior art, so that the signal propagation delay time is reduced and the system clock frequency can be increased. In the first aspect of the present invention, in the floor planning described above, (1) the size of the block is determined based on the total area of the cells or the number of gates in the block, and the block having the size is arranged in the floor, (2) When cells are roughly arranged in a block, global wiring is performed between cells inside and outside the block, (3) global wiring result is displayed on a display device, and (4) when it is determined that correction is necessary by looking at the display result, the block is After resizing or moving, the procedure returns to (2).

In the second aspect of the present invention, in the above (3), the number of wirings between blocks and the portion where the wiring density is equal to or more than the set value are displayed. According to the second aspect, it is possible to easily determine whether to resize or move the block. In the third aspect of the present invention, in (3) above, the critical path passing through a plurality of blocks of the semiconductor integrated circuit is also displayed.

According to the third aspect, the block can be moved so that the critical path is shortened, so that the system clock can be raised. A fourth aspect of the present invention is a logic synthesizing apparatus including a computer for implementing any one of the above logic synthesizing methods.

A fifth aspect of the present invention is a semiconductor integrated circuit designing method for carrying out any one of the above logic synthesis methods, and then performing a layout design based on the result of the floor planning. In this method, since the result of the floor planning performed in the logic synthesis stage is used in the layout design, the logic synthesis and the layout design can be prevented from becoming complicated,
Since the effects of the above invention can be obtained, the significance is great.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a CAD for a semiconductor integrated circuit.
1 shows a schematic configuration of a system. This system includes a logic synthesis device 10 and a simulation & layout design device 2
It consists of 0. The logic synthesizer 10 is a computer 11
And external storage devices 12 to 14, and manual operation input device 15
And a display device 16, which is a general computer system. The external storage devices 12, 13 and 14 are functionally divided and described.
The design data described in DL is stored, and the external storage device 13 stores the cell type, size, macrocell structure, and cell pattern used in the semiconductor integrated circuit. There are two types of cells, a basic cell and a macro cell that is a combination of basic cells. The basic cells are, for example, a NAND gate, a NOR gate, an inverter, and a flip-flop. The cell type, size, and macrocell structure are used in the computer 11, and the cell pattern is used in the simulation & layout design apparatus 20. The external storage device 14 stores a netlist and floorplanning data, which are calculation results of the computer 11, and these are used by the simulation & layout design device 20.

The outline of the processing by the logic synthesizer 10 is shown in FIG.
Shown in In conventional logic synthesis, steps 30-36, 3
Although the processing of 8 and 39 was performed, in this proposal,
The process of step 37 is performed between step 36 and step 38. Hereinafter, the numbers in parentheses are step identification numbers in the drawings. (30) L described in HDL, for example, Verirog HDL
The SI design data is read from the external storage device 12.

(31) This design data is translated, and the functional specification portion is converted into a logical expression. (32) Referring to the external storage device 13, the macro cell is expanded by the basic cell. (33) Allocate the I / O buffer in the peripheral area of the chip by manual input. (34) The logical expression is optimized so that the configuration becomes simple. (35) Perform technology mapping. That is, the optimization is performed by allocating the basic cells stored in the external storage device 13 in accordance with the logical expression and locally deleting redundant gates and wirings to reduce the area and the delay time. .

(36) Optimization between blocks is performed. For example, when the output terminal of the inverter of block A is connected to the input terminal of the inverter of block B, both redundant inverters are deleted. However, HD for timing adjustment
The driver cell (buffer gate) whose structure is described by L is left as it is. (37) The floor planning, which has been conventionally performed in the layout design by the simulation & layout designing apparatus 20 of FIG. 1, is performed at this stage. This floor planning includes calculation of inter-block virtual wiring capacity and display of a critical path, which have not been performed conventionally. Details of the process of step 37 are shown in FIG.

(370) Using the cell size data stored in the external storage device 13, the size of each block is estimated. For example, the total area of the cells in the block is calculated, and a value obtained by multiplying this by 1.4 is used as the block area. For simplification, the length of one side is calculated assuming that the block is a square. The block area may be a constant multiple of the number of gates in the block. This block is placed on the floor corresponding to the chip area.

(371) The virtual wiring length between blocks is calculated. For example, as shown in FIG.
When D is arranged, the length of the path connecting the center of gravity of block B and the center of gravity of block A with a straight line parallel to the side of floor 40 is defined as the cell in block B and the cell in block D. Calculated as the virtual wiring length between This virtual wiring length is, for example, the same as the length of the route passing through the dotted line in the figure,
Various routes of the same length are possible. The same applies to other blocks.

(372) The cells are roughly arranged in each block. In this schematic arrangement, the design rule is weakened, for example, by ignoring the partial overlap between cells, and instead, the grid spacing is made larger than in the actual arrangement.
Global wiring is performed between cells inside and outside the block. The (373) wiring result is displayed on the display device 16 of FIG. 1 as shown in FIGS. 5 (A), 5 (B) and 6. Further, the critical path of the semiconductor integrated circuit, which is designated in advance, is also displayed. FIG. 5A shows the number of wirings Nij between block i and block j (i and j are any of blocks A to D).
Is shown. In FIG. 5B, the congested portion where the wiring density is equal to or higher than the set value is hatched. FIG. 6 shows a critical path B → D → A → C passing through a plurality of blocks by a polygonal line passing through the center of gravity of the block. The designer judges the necessity of correction by looking at these displays.

(375) When it is judged that the correction is necessary, in order to reduce the portion where the wiring density is the set value or more, shorten the average wiring length between blocks, and shorten the critical path, for example, FIG. Resize or move the block as shown in. The polygonal line display of the critical path changes according to this change and movement. Figure 7
Replaces the positions of block A and block D in FIG.
The shapes of blocks A, C, and D are changed to block A ′,
The case of changing to C'and D'is shown.

Then, the process returns to step 371. (376) If it is determined that the correction is unnecessary in step 374, the floor planning data, that is, the size and arrangement of the block, the arrangement of the cells in the block, and the data of the global wiring between the cells inside and outside the block are output, and the data of FIG. It is stored in the external storage device 14.

(38) Timing adjustment is performed based on the sum of inter-cell wiring capacitance and cell input capacitance. That is, when this sum exceeds the driving capability of the cell, the driver cell is inserted into the inter-cell wiring so as to be less than the driving capability. Also, insert a buffer cell between the terminals or change the size of the cell connected between the terminals (input capacitance of the cell) so that the signal propagation delay time between the terminals specified in advance falls within the allowable range. To do.

For example, the adjustment is performed as described above with reference to FIG. However, as the virtual wiring capacity between blocks such as the wiring 3, a value obtained by multiplying the virtual wiring length obtained in step 371 of FIG. 3 by a constant (wiring capacity of unit length) is used. When the block size is small, the error in the inter-cell virtual wiring capacitance obtained from the relationship shown in FIG. 8A is relatively small. Therefore, the above timing adjustment between cells in the same block is performed as in the conventional case. The virtual wiring capacitance between cells obtained by the relationship shown in (A) is used.

(39) The netlist is output and stored in the external storage device 14. After performing the logic synthesis processing as described above, the simulation & layout design apparatus 2 of FIG.
With 0, simulation is performed based on the netlist stored in the external storage device 14, and the operation is confirmed.
Next, a layout design is performed by automatically performing cell placement and inter-cell wiring based on the netlist, floor planning data stored in the external storage device 14 and cell pattern data stored in the external storage device 13. To do. Since there is floor planning data, floor layout, which has been conventionally performed, can be omitted in this layout design. Next, an inter-cell delay time is calculated based on the layout pattern, and a more accurate simulation is performed using this.

According to this embodiment, since the virtual wiring capacitance between cells of different blocks is more accurate than before by the floor planning in step 37, the timing adjustment is performed more accurately, and the layout adjustment after the layout design is performed. The number of timing errors is reduced, the number of times of repeating the circuit specifications described in HDL, logic synthesis, and layout design is reduced, and the design period is shortened.

For the same reason, the number of driver cells to be inserted is reduced as compared with the conventional case, the signal propagation delay time is reduced, and the system clock frequency can be increased. Further, in the floor planning, the critical path can be displayed and the block can be moved so that the critical path becomes shorter. Therefore, the system clock can be increased also from this point.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a CAD system for a semiconductor integrated circuit.

FIG. 2 is a schematic flowchart of logic synthesis.

FIG. 3 is a detailed flowchart of step 37 of FIG.

FIG. 4 is an explanatory diagram of step 371 in FIG.

5 is an explanatory diagram of step 373 in FIG. 3. FIG.

FIG. 6 is an explanatory diagram of step 373 in FIG.

FIG. 7 is an explanatory diagram of step 375 in FIG.

FIG. 8 is an explanatory diagram of a conventional inter-cell virtual wiring capacity.

[Explanation of symbols]

 10 Logic Synthesizer 20 Simulation & Layout Design Device 11 Computer 12-14 External Storage Device 15 Manual Operation Input Device 16 Display Device 40 Floor A-D, S, A ', C', D'Block

Claims (6)

[Claims] 1. A cell is driven on the basis of a sum of a virtual wiring capacitance and an input capacitance of a cell by inputting a specification of a semiconductor integrated circuit described in a hardware description language as an input and generating a circuit at a gate level in a block unit. A logic synthesis method of determining whether or not the capacity is insufficient, and inserting a driver cell between cells when it is determined that the cell driving capacity is insufficient, which is performed after the gate level circuit is generated and before the determination. , Floor placement is performed to determine the layout of the blocks, and the length of the shortest path connecting the centers of gravity of different blocks with a line parallel to the side of the floor corresponding to the chip area is used as the virtual wiring between cells of different blocks. And a virtual wiring capacity between cells of different blocks based on the virtual wiring length. 2. In the floor planning, (1) the size of the block is determined based on the total area of the cells in the block or the number of gates, and the block having the size is arranged in the floor, and (2) in the block. When cells are roughly arranged, global wiring is performed between cells inside and outside the block, (3) global wiring result is displayed on a display device, and (4) when it is determined that correction is necessary by looking at the display result, the block is resized or The logic synthesis method according to claim 1, wherein the process returns to (2) after the move. 3. The logic synthesis method according to claim 2, wherein in (3), the number of wirings between blocks and a portion where the wiring density is equal to or more than a set value are displayed. 4. The logic synthesis method according to claim 3, wherein in (3), a critical path passing through a plurality of blocks of the semiconductor integrated circuit is also displayed. 5. A logic synthesizing apparatus comprising a computer for carrying out the logic synthesizing method according to any one of claims 1 to 4. 6. A semiconductor integrated circuit design method, comprising: performing the logic synthesis method according to claim 1, and then performing layout design based on a result of the floor planning.