JP2006338090A - Method and device for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and device for designing a semiconductor integrated circuit, capable of shortening the design period or facilitating the design. <P>SOLUTION: When the whole chip is divided to a top and a plurality of blocks, and placement and routing of the plurality of blocks are performed (S102 and S104), a block ILM including extracted data belonging to those except the own block and related to signal input and output to the own block (logic data, physical data and RC data) is used. The placement and routing of the blocks using the block ILM is performed in two steps. In one step (S102), for example, a block ILM including RC data based on temporary placement is used, and in the other step (S104), a block ILM including RC data based on actual placement and routing (S102 and S104) is used. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design method and design apparatus, and more particularly to a technique effectively applied to a large-scale semiconductor integrated circuit layout design method and design apparatus represented by a microcomputer.

  For example, a technique called hierarchical design and a technique called timing budget are widely used as layout design techniques for semiconductor integrated circuits. Hierarchical design method means a large-scale semiconductor integrated circuit, for example, a lower hierarchy (multiple blocks) with a circuit scale that can be handled by an automatic layout tool, and an upper hierarchy (top) that integrates these blocks. It is a technique to design by dividing into and. The timing budget is a method for automatically generating a constraint file (timing condition or the like) for each block from the top constraint and environment in such a hierarchical design. Therefore, each block can be designed in parallel based on the generated constraint file. Note that timing budget processing is generally called budgeting.

  By the way, as a result of the study of the present inventor on the design method of the semiconductor integrated circuit as described above, the following has been clarified.

  First, a detailed design method using the hierarchical design and timing budget described above will be described. FIG. 13 is a flowchart showing an example of the layout design flow in the semiconductor integrated circuit design method studied as a premise of the present invention.

  In the design flow shown in FIG. 13, first, partition creation and budgeting are performed on top-level floor plan (FP) data (S1201). That is, it is divided into top data and a plurality of blocks of data by hierarchical design. At this time, budgeting is performed together with a static timing analysis (STA) on a full chip using a full chip constraint file (full chip SDC). As a result, a constraint file (post-budget SDC) for each block is generated. Further, logic optimization processing considering timing, such as IPO (Inplace Optimization), is performed.

  As the above-described constraint file, for example, a so-called SDC (Synopsys Design Constraint) which is a standard format for expressing timing constraints is widely known. Therefore, for convenience, in the drawings and the following description, the constraint file may be referred to as SDC.

  Next, the placement and routing of each block is performed so as to satisfy the top placement and routing (P & R) and post-budget SDC (S1202). After that, the top data and block data after placement and routing are combined to extract high-accuracy actual load data such as each cell and path, and this actual load data is used again together with the STA on the full chip. Budgeting is performed (S1203). As a result, a constraint file (post-re-budget SDC) is generated again, and based on this, highly accurate placement and routing (so-called fine adjustment) of the block and the top is performed again (S1204). Through such processing, the chip layout is completed (S1205).

  In addition, in block placement and routing, for example, when the block is viewed from the top, a timing model that reduces the amount of information can be generated by specializing only in the input / output portion with the top level. Is possible. As such a timing model, for example, an ILM (Interface Logic Model) having RC data based on logical data (net list) of input / output portions and logical data is known.

  However, as a result of examination of the design flow by the present inventor, for example, the following problems have been clarified.

  (1) Budgeting as described above requires a full-chip STA, which increases the load on the design tool and increases the analysis time. In some cases, daily analysis time may be required. FIG. 14 is a circuit example for explaining the problem of budgeting in the design flow of FIG.

  In FIG. 14, for example, clock generation circuits CPG1 and CPG2 for generating clock signals clk1 and clk2 and a flip-flop FF1 are provided on the top TP, and a flip-flop FF2 is provided on the block BLK. Clk1 or clk2 is input to FF1, and clk1 or clk2 is input to FF2 via the clock input terminal CIN of BLK. The output signal of FF1 is input to FF2 via the BLK signal input terminal DIN.

  When budgeting is performed for such a configuration, for example, values of X1, X2, Y, and Z need to be obtained as SDC. X1 and X2 are delay times required for clk1 and clk2 generated by CPG1 and CPG2 to reach CIN, respectively. Y and Z are delay times required from when CPG1 and CPG2 generate clk1 and clk2 to when a signal is input to DIN by FF1. In order to obtain such a value, STA in a full chip state including TP and BLK is essential.

  (2) When performing budgeting as described above, the timing of block boundaries may become complicated, leading to an increase in the number of constraints. This increases the load on the design tool and may increase the analysis time. FIG. 15 is a circuit example for explaining another problem of the budgeting in the design flow of FIG.

  In FIG. 15, for example, clock generation circuits CPG1 and CPG2 for generating clock signals clk1 and clk2 and flip-flops FF1 and FF2 are provided on the top TP, and a flip-flop FF3 is provided on the block BLK. . Clk1 or clk2 is input to FF1 and FF2, and clk1 or clk2 is input to FF3 via the clock input terminal CIN of BLK. The signal output from the FF1 is input to the FF3 via the BLK signal input terminal DIN. Here, it is assumed that a maximum delay is set for the signal transfer as a user-set timing constraint.

  On the other hand, the signal output from FF2 is input to FF3 via DIN. Here, in this signal transfer, it is assumed that a multi-cycle path is set as a user-set timing constraint. In this way, especially when a plurality of clock signals are included and the maximum delay or multi-cycle path is restricted, many restrictions occur when converting it into a DIN restriction by budgeting. become. In FIG. 15, for example, eight types of constraint conditions are generated. In some cases, the originally necessary constraint conditions may not be sufficiently generated. Further, such complications may cause software problems.

  (3) There is a possibility that the design period may be increased due to the iteration accompanying the budgeting. FIG. 16 is a diagram for explaining still another problem of the budgeting in the design flow of FIG. As shown in FIG. 16, the iteration is a series in which after performing budgeting using a full-chip SDC, the SDC generated thereby is checked, the cause of the timing violation is investigated, and feedback is performed. Say the work.

  Examples of the timing violation include a case where there is a problem with the full-chip SDC, a case where there is a problem with the budgeting process itself, a case where timing optimization is insufficient, and a case where there is a true timing violation. . Therefore, it is necessary to take these measures and take measures according to the cause. These confirmations are made by a designer or the like, and are usually time-consuming and labor-intensive work. Also, the time required for this depends on the ability of the designer. Depending on the cause of the timing violation and the countermeasure content, for example, a design return often occurs between S1205 and S1202 in FIG.

  (4) Analysis and optimization after placement and routing may be difficult. FIG. 17 is a circuit example for explaining still another problem of the budgeting in the design flow of FIG. In FIG. 17, for example, a clock generation circuit CPG1 that generates a clock signal clk1 and a flip-flop FF1 are provided in the top TP, and a flip-flop FF2 is provided in the block BLK. Clk1 is input to FF1, and clk1 is input to FF2 via the clock input terminal CIN of BLK. The signal output from the FF1 is input to the FF2 via the BLK signal input terminal DIN.

  In such a configuration, for example, when designing a block BLK using a timing constraint generated by budgeting, it is possible to consider the delay time from CIN or DIN to FF2 due to the timing constraint. However, it is difficult to sufficiently take into account variations in delay time due to, for example, jitter and skew of the clock signal clk1.

  That is, the analysis and optimization of such variations are performed by, for example, a process called OCV (On Chip Variation) or a process called CRPR (Clock Regenerative Pessimism Removal). When such a process is used, for example, a variation in delay time is calculated in consideration of a variation in voltage / temperature, and a cell is inserted in a signal path, for example, in order to compensate for this variation. Further, in order to accurately calculate the variation of the clock signal, for example, a process of analyzing a clock path used in common by FF1 and FF2 in FIG. 17 is performed.

  Therefore, for example, in order to analyze and optimize the variation in signal transfer between FF1 and FF2 in FIG. 17 by the above-described processing, processing in a circuit including TP and BLK (ie, a full chip) is eventually required. It becomes. In addition, although it is conceivable to design the BLK by reflecting the processing result of this full chip in, for example, the timing constraint in DIN, it is extremely difficult to reflect the exact variation in the timing constraint in practice. It is. As described above, in the constraint file, information necessary for the design may not be expressed sufficiently, which may cause a design return later.

  In addition to the above (1) to (4), for example, when designing a block, physical information outside the block cannot be seen at all. Therefore, signal integrity, DFM (Design) to be considered at the time of layout. for manufacturing) and chip variation may be insufficiently considered. What has been described above is a problem that cannot be solved as long as the budgeting design method is used. These problems complicate the design and increase the design period.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit design method and design apparatus that can shorten the design period. Another object of the present invention is to provide a semiconductor integrated circuit design method and design apparatus that can facilitate design.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor integrated circuit design method of the present invention performs layout design by dividing the design data of the entire chip into design data of a plurality of blocks using a computer such as a layout design tool. Then, when performing the placement and routing of each block, an interface model that extracts design data related to signal input / output to this block from design data other than its own block as the boundary condition of each block. It is intended to be used. Thereby, the budgeting used in the prior art becomes unnecessary, and it becomes possible to suppress delays in the design period associated with this budgeting and the complexity of the layout design.

  Here, in addition to logical data such as a net list, the interface model design data includes physical data after cell placement and routing or provisional placement and routing, and RC data extracted from the physical data. It is desirable to have it. This makes it possible to consider the timing with high accuracy when performing the placement and routing of each block, thereby realizing a reduction in design period. In addition, when optimizing the boundary of each block with the placement and routing of each block, using the interface model with the design data as described above facilitates optimization and greatly improves the efficiency of optimization. To do.

  The semiconductor integrated circuit design method of the present invention is to perform layout design by dividing the design data of the entire chip into top design data and a plurality of blocks of design data using a computer. The arrangement and wiring of each block using the interface model as described above is performed in two stages. That is, in the first stage placement and routing, cell placement in the top and each block is performed, and in the next stage placement and routing, high-accuracy RC data is extracted from the state where the cell placement is once performed. Fine adjustment of the cell arrangement is performed based on RC data or the like.

  Here, the interface model has two stages along with the two stages of placement and routing. In the first stage interface model (first interface model), in addition to logical data, it is desirable to provide physical data after provisional placement and routing of cells and RC data obtained therefrom. That is, it is desirable to perform temporary placement and routing of cells in advance before placement and routing in the first stage, and generate physical data and RC data of the first interface model from this state. As a result, it is possible to design a layout in consideration of highly accurate timing from an early stage, thereby realizing a reduction in design period.

  Further, in the interface model at the next stage (third interface model), in addition to the logical data, RC data obtained from the placement and routing at the first stage is provided. And by finely adjusting the placement and routing of each block using this interface model, it is possible to easily and accurately perform fine adjustment and optimization of the cell placement in each block for the completion of the layout. become.

  In addition, when performing top placement and routing, an interface model (second interface) in which design data related to signal input / output to the top is extracted from design data other than the top, similarly to the placement and routing of each block described above. Model). And this 2nd interface model is good to give logical data, physical data, and RC data similarly to the 1st interface model. As a result, optimization at the top boundary becomes easy or efficient, and the design period can be shortened.

  If the effects obtained by typical ones of the inventions disclosed in the present application are briefly described, the design period of the semiconductor integrated circuit can be shortened or the design can be facilitated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a flowchart showing an example of a layout design flow in a method for designing a semiconductor integrated circuit according to an embodiment of the present invention. The main feature of the layout design flow of FIG. 1 is that instead of using budgeting SDC as a boundary condition for each block, an ILM for a block that is an interface model is generated, and this ILM for a block is used as a boundary condition. The placement and wiring of each block is performed. Hereinafter, the layout design flow of FIG. 1 will be briefly described, and then detailed processing contents in the layout design flow will be described.

  In the layout design flow shown in FIG. 1, first, a top and a plurality of blocks are cut out from top-level floor plan (FP) data that is data of the entire chip, and an initial block ILM corresponding to each block is obtained. Generate (S101). Next, placement and routing are performed on the cut-out top data and data of a plurality of blocks. Here, when performing placement and routing of the plurality of blocks, the block ILM corresponding to each block is used together with the data of each block (S102). After completion of these placement and routing, the top and the block are once integrated to extract the actual load data, and a readjustment block ILM including the actual load data is generated (S103). Then, using the ILM for the block for readjustment, placement and wiring that is so fine adjustment is performed on the top and the block (S104), thereby completing the layout of the chip (S105).

  Next, an example of detailed processing contents of the layout design flow of FIG. 1 will be described. First, the block ILM created in S101 and S103 is, for example, as follows.

  FIG. 2 is a circuit diagram for explaining an example of logic data of the block ILM in the layout design flow of FIG. In FIG. 2, for example, clock generation circuits CPG1 and CPG2 for generating clock signals clk1 and clk2 and flip-flops FF1 and FF3 are provided on the top TP, and a flip-flop FF2 is provided on the block BLK1. . Clk1 or clk2 is input to FF1 and FF3, and clk1 or clk2 is input to FF2 via the clock input terminal CIN1 of BLK1. The output signal of FF3 is input to FF1 via combinational logic, and the output signal of FF1 is further input to FF2 via signal input terminal DIN1 of BLK1 and the combinational logic before and after that. As shown in FIG. 2, a circuit commonly used in each block represented by a clock circuit is normally assigned to the TP.

  In such a configuration, in the processing of S101 and S103, B_ILM1, which is a partial circuit other than BLK1 (in this example, in the top TP) as shown in FIG. 2, is extracted as the ILM for the block corresponding to BLK1. B_ILM1 in FIG. 2 is a circuit in which an input / output portion to BLK1 is extracted from a circuit directly related to the timing of the input terminals CIN1 and DIN1 of BLK1, that is, a circuit of TP, in the circuit of TP. This is the same as the ILM model described above with reference to FIG. 13, but in FIG. 13, the circuit required when the block is viewed from the top is extracted, whereas here, the block other than that block (here, When looking at the top), the necessary circuits will be extracted.

  In the example of FIG. 2, as B_ILM1, a clock path connected to CIN1 (ie, a clock path to CPG1 and CPG2), a signal path connected to DIN1 (ie, a signal path to FF1), and FF1 The clock path is extracted. Such path extraction can be easily realized by following net list data, for example. Further, B_ILM1 includes physical data and RC data as described in FIG. 3 in addition to logical data (net list data) as shown in FIG. However, since the data amount of B_ILM1 is only the data related to the input / output portion, a small data amount is sufficient.

  FIG. 3 is a layout schematic diagram for explaining an example of physical data included in the block ILM in the layout design flow of FIG. For example, as shown in the left diagram of FIG. 3, it is assumed that there is physical data (floor plan data, cell arrangement data) of the top TP and the two blocks BLK1 and BLK2 as physical data of the entire chip. In such a chip, for example, when performing placement and routing of BLK2, physical data including cell placement information as shown in the right diagram of FIG. 3 and RC data (actual load data) extracted from this physical data are provided. The block ILM (B_ILM2) is used.

  Note that B_ILM2 shown in FIG. 3 is a part of the top TP region as in FIG. 2, but as described later in FIG. 5, as a part of the region other than TP (for example, the region of BLK1). May be present. Also, when performing actual placement and routing of BLK2 using such B_ILM2, physical data at locations not corresponding to the logical data of BLK2 and B_ILM2 is deleted from the floor plan data of the full chip, and the corresponding floor This is done with placement and wiring prohibitions placed at physical locations on the plan data.

  As described above, the block ILM is an interface model in which data of a portion related to signal input / output to / from the block is extracted from data other than the block. The specific contents of the interface model are composed of all or part of logical data, physical data, and RC data. In S102 and S104 of FIG. 1, placement and routing are performed using such a block ILM.

  In this arrangement and wiring, cells are arranged in each block by automatic processing based on full-chip SDC, not SDC by budgeting, and wiring between each cell and each cell is performed. That is, in the top-level floor plan data that is the first data in FIG. 1, for example, in FIG. 3, the framework of each block and the arrangement of hardware modules (modules whose layout is fixed in advance) HM are determined. ing. In block placement and routing, within the framework of the block, a large number of cells CL that are circuit elements are placed and routed so as to satisfy the timing conditions of SDC.

  FIG. 4 is a circuit diagram for explaining another example of the logic data of the block ILM in the layout design flow of FIG. The circuit example illustrated in FIG. 4 includes, for example, a top TP and two blocks BLK1 and BLK2. The TP is provided with clock generation circuits CPG1 and CPG2 that generate clock signals clk1 and clk2, respectively, and flip-flops FF2 and FF3. The block BLK1 is provided with a flip-flop FF4, and the block BLK2 is provided with a flip-flop FF1.

  Clk1 or clk2 is input to FF2 and FF3, and clk1 or clk2 is input to FF1 and FF4 via the clock input terminal CIN2 of BLK2 and the clock input terminal CIN1 of BLK1, respectively. The output signal of FF1 is input to FF2 via the signal output terminal DO2 of BLK2 and the combinational logic before and after that, and the output signal of FF2 is further input to FF3 via the combinational logic. The output signal of FF3 is input to FF4 via the signal input terminal DIN1 of BLK1 and the combinational logic before and after that.

  In such a configuration, the corresponding block ILM is extracted for each of the blocks BLK1 and BLK2 during the processing in S101. That is, the block ILM (B_ILM1) for BLK1 is extracted from circuits other than BLK1, and the block ILM (B_ILM2) for BLK2 is extracted from circuits other than BLK2. B_ILM1 includes a clock path connected to CIN1 (ie, a clock path to CPG1 and CPG2), a signal path connected to DIN1 (ie, a signal path to FF3), and a clock path of FF3. included. B_ILM2 includes a clock path connected to CIN2 (ie, a clock path to CPG1 and CPG2), a signal path connected to DO2 (ie, a signal path to FF2), and a clock path of FF2. included.

  The range for extracting the clock path may be determined according to the required design accuracy. That is, for example, when there is a clock branch point and a clock signal is input from one branch, if the load on the other branch affects the timing of the clock signal on the other branch, the other branch Alternatively, clock paths may be extracted as much as necessary. In S102, the blocks BLK1 and BLK2 are arranged and wired in parallel using the block ILMs (B_ILM1, B_ILM2) corresponding to the respective blocks BLK1, BLK2, respectively.

  FIG. 5 is a circuit diagram for explaining still another example of the logic data of the block ILM in the layout design flow of FIG. The circuit example shown in FIG. 5 includes, for example, a top TP and two blocks BLK1 and BLK2. The TP is provided with clock generation circuits CPG1 and CPG2 for generating clock signals clk1 and clk2, respectively. The block BLK1 is provided with a flip-flop FF2, and the block BLK2 is provided with a flip-flop FF1.

  Clk1 or clk2 is input to FF1 and FF2 via clock input terminal CIN2 of BLK2 and clock input terminal CIN1 of BLK1, respectively. The output signal of FF1 is transmitted to the signal output terminal DO2 of BLK2 through combinational logic, and further transmitted from DO2 to the signal input terminal DIN1 of BLK1 through combinational logic. The signal transmitted to DIN1 is input to FF2 through combinational logic.

  In such a configuration, for example, the circuit in TP and the circuit in BLK2 are included in the block ILM (B_ILM1) of BLK1. That is, B_ILM1 in FIG. 5 includes a clock path connected to CIN1 (ie, a clock path to CPG1 and CPG2 in TP) and a signal path connected to DIN1 (ie, to FF1 in BLK2). Signal path). Although not shown, the block ILM for BLK2 includes a circuit in BLK1, as in the case of B_ILM1.

  FIG. 6 is a schematic diagram showing an example of data included in the initial and readjustment block ILM in the layout design flow of FIG. 1, wherein (a) shows physical data and (b) shows logical data. is there. As described above, the block ILM includes logical data, physical data, and RC data. That is, as shown in FIG. 6, for example, when the block BLK2 is taken as an example, the physical data of the block ILM (B_ILM2) is as shown in FIG. 6A, and the logical data of B_ILM2 is shown in FIG. )become that way. Then, RC (resistance component and capacitance component) data is extracted based on the physical data of each signal path and each clock path in B_ILM2.

  Here, in the layout design flow of FIG. 1, two types of block ILMs are shown. Among them, the initial block ILM performs partition creation, temporary placement and routing of cells, provisional IPO, etc. from a full flat state that is not hierarchized in advance in step S101 in FIG. It is desirable to extract from the state of wiring. In this case, the initial block ILM includes logical data, physical data as temporary placement and routing data, and RC data extracted from the physical data. In some cases, it is also possible to extract from the unarranged state of the cells. However, in this case, for example, logical data, floor plan data as physical data, and RC data based on logical data are provided, but there is a concern that design efficiency and design accuracy may be inferior to the former. The

  On the other hand, the ILM for the block for readjustment is extracted from the state where the placement and wiring of the cells in the top and the block are completed in the process of S102 of FIG. Accordingly, the readjustment block ILM includes logical data, physical data reflecting the placement and routing result, and RC data obtained from the physical data. However, as will be described later with reference to FIG. 9, in the fine adjustment process of the block arrangement and wiring in S104 of FIG. 1, the process for changing the cell arrangement of the ILM for readjustment block is not performed. Physical data is not necessarily required for the ILM.

  FIG. 7 is an explanatory diagram showing an example of timing optimization processing using the initial block ILM in the layout design flow of FIG. This timing optimization processing is performed as part of the placement and routing of the top and block in S102 of FIG. 1, for example. In step S102, the placement and wiring of the top and the block are performed in parallel. Here, as shown in FIG. 7, when optimizing the signal path A1 between BLK2 and the top TP in, for example, the placement and routing of the block BLK2, there are cases where optimization of TP logic is allowed and cases where it is not allowed. It is done.

  In the permitted case, optimization is performed including the signal path of BLK2 and the block ILM (B_ILM2) included in TP. As shown in FIG. 7, on the assumption that a part of the top is a block ILM, this allowed case is, for example, when the top placement and routing is being executed in parallel or when the top logic can be changed. is there. On the other hand, a case where it is not permitted is, for example, a case where the top placement and routing is completed and the top logic is not desired to be changed. That is, for example, there is a case where a layout design flow in which block placement and routing is performed after top placement and routing is used. Further, as will be described later with reference to FIG. 9, this is also the case when performing block optimization at the stage of S104 in FIG.

  In this way, by optimizing the timing using the block ILM, optimization can be performed without dividing the block boundary path as in the case of budgeting, so the processing capability and temporal efficiency are greatly improved. To do. In addition, since the block ILM has physical data, the boundary surface between the top and the block including the cell arrangement can be efficiently optimized.

  In the case where the optimization of the logic of TP is allowed, the logical change of B_ILM2 accompanying the optimization of the block BLK2 described above is not actually reflected, and the actual data of this part is determined by the placement and wiring of the TP. Become. In other words, the block ILM data in the TP optimized in accordance with the block arrangement and wiring is actually replaced with the data for the block ILM determined by the TP arrangement and wiring. This is expected to reduce the degree of optimization slightly. However, since all the data before and after replacement are arranged and routed so as to suppress the maximum delay in principle, there is not much difference, and it is considered that they are within an allowable range in actual use. Further, even if it becomes necessary to readjust the optimization slightly, the process does not require time.

  FIG. 8 is an explanatory diagram showing another example of the timing optimization process using the initial block ILM in the layout design flow of FIG. In the optimization process, for example, there are cases where timing convergence is better when pins are added to block boundaries. That is, for example, as shown in FIG. 8, a critical path load can be reduced by adding a pin to the terminal DIN1 to form the terminals DIN11 and DIN12. In this case, it is necessary to update the pin added in the block with respect to the top, and to perform the placement and wiring of the top reflecting this update. It is also possible to optimize by setting that the pin information at the block boundary is not changed (pin is fixed).

  FIG. 9 is a diagram for explaining an example of timing optimization processing using the readjustment block ILM in the layout design flow of FIG. This timing optimization process is performed as part of the block placement and routing in S104 of FIG. Therefore, at the stage of block placement / wiring in S104, since the cell placement relating to the readjustment block ILM is determined by the top placement / wiring, the area of the readjustment block ILM is changed by optimization. That is not desirable.

  For this reason, the ILM for readjustment block uses the logical data necessary for performing delay calculation or the like in accordance with the optimization process in the block, and the RC data obtained from the result of arrangement and wiring of the logical data. It is not always necessary to provide physical data. Also, even if physical data is provided, it is only referred to. In the example of the timing optimization process of FIG. 9, when the optimization process of the signal path A1 at the block boundary is performed, the block ILM (B_ILM2) for readjustment is not allowed to be changed, but is only referred to, and the block BLK2 The optimization process is performed only in the signal path A2.

  FIG. 10 is a diagram for explaining an example of optimization processing for the top in the layout design flow of FIG. The optimization of the top is performed as part of the placement and wiring of the top in S102 and S104 of FIG. At this time, in order to optimize the top at the boundary between the top and the block, the ILM similar to the conventional technique is used. However, although the ILM of the prior art includes only logical data and RC data, the ILM further includes physical data as shown in FIG. 10, for example. For example, the physical data of the ILM used in the stage of S102 can be temporary placement and routing data, like the initial block ILM described with reference to FIG.

  In this way, by providing physical data to the top ILM as well as the ILM for the block, for example, optimization processing such as changing the pin of the block boundary or passing the signal wiring over the block is facilitated. It becomes possible to do. However, when such boundary change or optimization of over-block passage is performed, it is necessary to re-execute block data extraction and block ILM creation. However, since subsequent layout design becomes easy, it is considered possible to shorten the design period as a whole.

  Next, an example of a design apparatus that performs the processing as described above will be described.

  FIG. 11 is a schematic diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention. The design apparatus shown in FIG. 11 is realized by program processing by a computer, and is an apparatus that performs the processing of S101 before placement and routing in FIG. The configuration includes, for example, an input unit IND1 and an output unit OUD1 realized by a storage medium such as a hard disk, a hierarchical layout data division processing unit PRO1 realized by a CPU, a memory, and the like.

  IND1 stores, for example, a full-chip netlist data, a full-chip floorplan data, a full-chip SDC, a logical library including timing information such as cell delay time, a physical library including information related to cell shape, and the like. Has been. For example, the following processing is performed in PRO1 using such information.

  First, the data of the input unit IND1 as described above is read (S1101), and the cells are arranged and wired on the full chip based on the full chip SDC (S1102). Note that the placement and routing in S1102 is a so-called temporary placement and routing. Further, when using data that has already been provisionally placed and routed, the processing here is not necessary. Next, if necessary, STA and timing improvement processing are performed on the data of the full chip on which temporary placement and routing has been performed (S1103). S1103 is a provisional optimization process (IPO). As described above, if the preliminary optimization process is performed in advance, the subsequent layout design can be performed with high accuracy.

  Next, RC data such as wiring load is extracted from full-chip data based on such temporary placement and routing (S1104). Thereafter, the full-chip timing path is divided into a top, a block, an ILM corresponding to the top, and a block ILM (S1105). Each ILM can be easily extracted by analyzing the timing path. Subsequently, the net list and the physical data are separated corresponding to the separated timing paths (S1106). Then, the data obtained by the above processing is stored in the output unit OUD1 (S1107).

  The OUD 1 includes, for example, a top netlist, floor plan data and cell arrangement information (that is, physical data) regarding the top and its ILM, top ILM data, a block netlist, a block and Stores physical data related to the block ILM, block ILM data, and the like. Here, the data for the top ILM and the data for the block ILM include netlist data and RC data excluding the physical data separately stored as described above.

  FIG. 12 is a schematic diagram showing another example of the configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention. Similarly to FIG. 11, the design apparatus shown in FIG. 12 is realized by a program process by a computer, and is an apparatus that performs the process of S103 after the placement and routing in FIG. The configuration includes, for example, an input unit IND2 and an output unit OUD2 realized by a storage medium such as a hard disk, a hierarchical layout data division processing unit PRO2 realized by a CPU, a memory, and the like.

  IND2 stores, for example, netlist data, actual load data (RC data), and placement and routing data according to S102 in FIG. 1 corresponding to each of the top and block, in addition to the full-chip SDC, logical library, and physical Contains libraries and so on. For example, the following processing is performed in PRO2 using such information.

  First, the data in the input unit IND2 as described above is read (S1201), and a full chip creation process is performed by integrating the top data and the block data (S1202). Next, such full-chip data is again divided into timing paths corresponding to the top, the block, the ILM corresponding to the top, and the ILM for block (S1203). Subsequently, the net list, the physical data, and the actual load data are separated corresponding to the separated timing paths (S1204). Then, the data obtained by the above processing is stored in the output unit OUD2 (S1205).

  The OUD 2 includes, for example, a top netlist, floor plan data and cell arrangement information (that is, physical data) regarding the top and its ILM, top ILM data, a block netlist, a block and Stores physical data related to the block ILM, block ILM data, and the like. Here, the data for the top ILM and the data for the block ILM include netlist data and RC data excluding the physical data separately stored as described above.

  As described above, by using the layout design flow as shown in FIG. 1 and the design apparatus as shown in FIGS. 11 and 12, budgeting becomes unnecessary, and the following effects can be obtained, for example.

  (1) Since a full-chip STA associated with budgeting as described in FIG. 14 is not required, the load on the design tool is reduced, and the processing time of the design tool can be shortened. That is, in the layout design flow of FIG. 1, when a block ILM is created in S101 or the like, a path that is a part of the processing of the full chip STA is extracted. However, the enormous processing required for budgeting, that is, the processing for calculating the delay time of the path extracted to generate the SDC at each terminal of the block at the full chip level becomes unnecessary.

  (2) As described with reference to FIG. 15, the block boundary timing constraint associated with budgeting is not required, and the burden on the design tool can be reduced. Further, by not generating such a complicated timing constraint, it is possible to simplify (simplify) the layout design and suppress a delay in the design period due to a software defect or the like.

  (3) Iterating accompanying budgeting as described in FIG. 16 can be eliminated, and the design period can be shortened. In other words, the layout design is performed in a state where the top and block are not clearly separated as in the case of budgeting, and the boundary is virtually eliminated, so timing violations at the boundary between the top and block that frequently occur in budgeting Will not occur. In addition, since the layout design is simplified (simplified) by virtually eliminating the boundary in this way, even when a timing violation occurs in the vicinity of the actual boundary, both the cause investigation and countermeasures can be easily and quickly performed. It can be done in time.

  (4) Analysis and optimization after placement and routing as described with reference to FIG. 17 can be easily performed. That is, since the actual logical data or the like exists as the block ILM instead of the numerical value of the timing constraint, the state beyond the block boundary can be easily analyzed and optimized.

  In addition to the above (1) to (4), for example, when designing a block, physical data outside the related block can be referred to by the block ILM, so that signal integrity to be considered at the time of layout is required. , DFM, chip variation, etc. can be fully considered. As described above, when designing the layout of a semiconductor integrated circuit, the design period can be shortened or the design can be facilitated. Specifically, for example, by using the block ILM method as shown in FIG. 1, it is expected that the layout design period can be reduced to about 1/3 compared to the budgeting method as shown in FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the description so far, the description has been made using the concept of top and block according to the usual layout design practice, but the present invention can also be applied to a chip composed of only blocks. It is.

  The method and apparatus for designing a semiconductor integrated circuit according to the present invention is a technology that is particularly useful when applied to a layout design method and design tool for a large-scale LSI represented by a system LSI or a microcomputer. However, the present invention can be widely applied as a layout design method and design tool for LSI in general.

FIG. 10 is a flowchart showing an example of the layout design flow in the method of designing a semiconductor integrated circuit according to the embodiment of the present invention. FIG. 2 is a circuit diagram for explaining an example of logic data of a block ILM in the layout design flow of FIG. 1. FIG. 3 is a layout schematic diagram for explaining an example of physical data included in a block ILM in the layout design flow of FIG. 1. FIG. 8 is a circuit diagram for explaining another example of logic data of the block ILM in the layout design flow of FIG. 1. FIG. 10 is a circuit diagram for explaining still another example of the logic data of the block ILM in the layout design flow of FIG. 1. FIG. 2 is a schematic diagram illustrating an example of data included in an initial and readjustment block ILM in the layout design flow of FIG. 1, in which (a) shows physical data and (b) shows logical data. FIG. 2 is an explanatory diagram showing an example of timing optimization processing using an initial block ILM in the layout design flow of FIG. 1. FIG. 10 is an explanatory diagram showing another example of timing optimization processing using an initial block ILM in the layout design flow of FIG. 1. FIG. 2 is a diagram for describing an example of timing optimization processing using a readjustment block ILM in the layout design flow of FIG. 1. FIG. 2 is a diagram for explaining an example of optimization processing for a top in the layout design flow of FIG. 1. 1 is a schematic diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention; FIG. 10 is a schematic diagram showing another example of the configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention; FIG. 10 is a flowchart showing an example of a layout design flow in a semiconductor integrated circuit design method studied as a premise of the present invention. It is a circuit example for demonstrating the problem of the budgeting in the design flow of FIG. 14 is a circuit example for explaining another problem of the budgeting in the design flow of FIG. It is a figure for demonstrating the further another problem of the budgeting in the design flow of FIG. 14 is a circuit example for explaining still another problem of the budgeting in the design flow of FIG.

Explanation of symbols

CPG1, CPG2 clock generation circuit clk1, clk2 clock signal FF1-FF4 flip-flop TP top BLK, BLK1, BLK2 block ILM for B_ILM1, B_ILM2 block
DIN, DIN1, DIN11, DIN12 Signal input terminal CIN, CIN1, CIN2 Clock input terminal DO2 Signal output terminal A1, A2 Signal path HM Hard module CL Cell IND1, IND2 Input section OUD1, OUD2 Output section PRO1, PRO2 Data division for hierarchical layout Processing part

Claims (11)

A method for designing a semiconductor integrated circuit that uses a computer to divide the design data of the entire chip into design data of a plurality of blocks and perform layout design,
For each of the plurality of blocks, design data related to signal input / output to the own block is extracted as an interface model from design data other than the own block, thereby corresponding to each of the plurality of blocks. Processing to generate a plurality of interface models,
A method for designing a semiconductor integrated circuit, comprising: processing to place and route the plurality of blocks by using the generated interface model as a boundary condition for each block. The method for designing a semiconductor integrated circuit according to claim 1,
The design data of the interface model is
Logical data that is the netlist data,
Physical data including cell placement information;
A method for designing a semiconductor integrated circuit, comprising: RC data obtained from the physical data. The method for designing a semiconductor integrated circuit according to claim 1,
The method for designing a semiconductor integrated circuit, wherein the process of performing the placement and routing includes an optimization process. A design method of a semiconductor integrated circuit that uses a computer to divide the design data of the entire chip into top design data and design data of a plurality of blocks and perform layout design,
For each of the plurality of blocks, design data related to signal input / output to the own block is extracted as an interface model from design data other than the own block, thereby corresponding to each of the plurality of blocks. A first process for generating a plurality of first interface models,
A second process for generating, as a second interface model, design data related to signal input / output to the top from among the design data other than the top for the top;
Using the generated first interface model as a boundary condition for each block, a third process for performing placement and routing of the plurality of blocks;
Using the generated second interface model as a boundary condition for the top, a fourth process for performing placement and routing of the top;
Using the design data after the placement and routing of the plurality of blocks and the top, for each of the plurality of blocks after placement and routing, signal input / output from the design data other than the own block to the own block A fifth process of generating a plurality of third interface models respectively corresponding to the plurality of blocks after the placement and routing by extracting design data related to
And a sixth process for finely adjusting the placement and routing of the plurality of blocks by using the generated third interface model as a boundary condition for each block after the placement and routing. Integrated circuit design method. The method of designing a semiconductor integrated circuit according to claim 4,
In the first process, temporary placement and routing of cells is performed on the top and the plurality of blocks,
The design data of the first interface model is
Logical data that is the netlist data,
Physical data which is information after the provisional placement and routing;
A method for designing a semiconductor integrated circuit, comprising: RC data obtained from the physical data. The method of designing a semiconductor integrated circuit according to claim 4,
In the first process, temporary placement and routing of cells is performed on the top and the plurality of blocks,
A design method of a semiconductor integrated circuit, wherein the design data of the second interface model includes physical data which is information after the temporary placement and routing. The method of designing a semiconductor integrated circuit according to claim 4,
The design data of the third interface model is
Logical data that is the netlist data,
RC design data reflecting the result of the placement and routing in the third process and the fourth process. The method of designing a semiconductor integrated circuit according to claim 4,
The third process includes an optimization process,
The semiconductor is characterized in that, when the boundary portions of the plurality of blocks are optimized in the third process, the optimization is performed on both the plurality of blocks and the plurality of first interface models. Integrated circuit design method. The method of designing a semiconductor integrated circuit according to claim 4,
The sixth process includes an optimization process,
When the boundary portions of the plurality of blocks are optimized in the sixth process, the plurality of blocks are optimized with reference to the plurality of third interface models. A method for designing a semiconductor integrated circuit. A semiconductor integrated circuit design apparatus that performs layout design by dividing design data of a whole chip into design data of a plurality of blocks using a computer,
The computer
For each of the plurality of blocks, the design data related to signal input / output to the block itself is automatically extracted from the design data other than the block itself as an interface model. Automatically generating multiple interface models corresponding to each of the
Using the generated interface model as a boundary condition for each block, and automatically performing placement and routing of the plurality of blocks based on preset timing constraints for the entire chip. A semiconductor integrated circuit design device. The apparatus for designing a semiconductor integrated circuit according to claim 10, wherein
The generated interface model design data is:
Logical data that is the netlist data,
Physical data including cell placement information;
A design apparatus for a semiconductor integrated circuit, comprising RC data obtained from the physical data.

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