JP2008210109A - Design method and design device for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing design facilitation method and a design device, facilitating controllability and estimation of wiring between gates important in a timing design without losing the whole optimality of a logic circuit layout design. <P>SOLUTION: The whole circuit is divided into a plurality of logic blocks, and each logic block is divided into a core logic block wherein an FF is set as an input/output cut end and an interface logic block on the periphery thereof. A layout design of the core logic block is performed independently of a layout design of the other logic block and an inter-block wiring design. With respect to the layout design of the wiring between the blocks and the interface logic block, an inter-block wiring design is first performed, a result thereof is fixed, and next, layout design of all the interface logic blocks is performed in a lump in consideration of inter-block wiring delay obtained from the fixed inter-block wiring design result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design method and design apparatus, and more particularly to a design method and design apparatus for designing a semiconductor integrated circuit in consideration of a delay time of a logic circuit.

  A design of a clock synchronous semiconductor circuit (hereinafter also referred to as “LSI”), particularly a timing design in consideration of a delay time of a logic circuit, will be described with reference to FIG.

  In the clock synchronous semiconductor circuit, a logic circuit is provided between clock synchronization elements 101-01 called flip-flops (hereinafter also referred to as “FF”). The logic circuit includes a logic gate 101-02 and a wiring (signal line) 101-03.

  In clock-synchronous semiconductor circuit design, the logic circuit layout design between the FFs (“Placement and routing” so that the delay time of the signal passing through the logic circuit between clock synchronization elements is within the constraint value (timing constraint 101-05) Also called “design”).

  Specifically, the delay time of the signal passing through the logic circuit is composed of the delay time of the logic gate 101-02 and the delay time of the wiring 101-03 connecting the logic gates, and it is necessary to keep this sum within the constraint value. .

  For example, in order to design a circuit that operates at 100 MHz, it is necessary to keep the delay time of all the logical paths 101-04 between FFs within 10 nanoseconds.

  Hereinafter, the set of signal lines 101-03 and logic gates 101-02 appearing from the input terminal of FF101-01 to the other FF101-01 by following the logic circuit in the reverse direction of the signal flow, Call the input logic cone (or logic cone) 101-06. The “delay time” is also simply referred to as “delay”.

  FIG. 12 shows a “flat design method” conventionally used as one of the design methods for this type of semiconductor circuit.

  In the flat design method, the layout design of all the logic circuits is made in one batch with the entire chip as one layout target area without distinguishing the layout design area of the logic gate 101-02 and the inter-logic gate signal line 102-02. Done.

  The flat design method is suitable for minimizing the chip area because there are no regional restrictions on the layout and the degree of freedom and flexibility are high.

  However, in the flat design method, because the placement area and the wiring area are mixed, the logic gate becomes an obstacle, it is difficult to predict what route the wiring between the logic gates will be, and it is difficult to control the route. There is a problem.

  The detour wiring 102-03 shown in FIG. 12 is generated to avoid a region where the logic gates 101-02 are densely arranged.

  In ultra-fine process semiconductors, the proportion of wiring delay in the logical path delay is large, and such wiring bypass is a major factor that makes it difficult to design the timing of a semiconductor circuit.

  Further, the flat design method has a problem that the number of logic gates that can be handled is limited and is not suitable for designing a very large scale circuit.

  FIG. 13 shows a conventionally used “division design method” as a design method for solving “difficulty in wiring path prediction and control” and “restriction of circuit scale that can be handled”, which are problems of the flat design method described above. Show.

  In the division design method, the entire circuit is divided into a plurality of logical block sets (in FIG. 13, it is divided into four logical block sets). Divided into two.

  Since a dedicated layout area 103-02 is provided for the long wiring 103-03 connecting the logic blocks, the problem that “the logic gate becomes a failure and the wiring is detoured” hardly occurs. Therefore, it is easy to estimate the inter-block wiring delay at the early design stage, and to optimize the inter-block wiring delay such as wiring width, wiring layer, repeater insertion, etc. by changing the inter-block wiring area. It is possible to easily control the inter-block wiring structure.

In addition, since the design object is divided into small logical block sets and designed, a circuit having a scale that cannot be handled by flat design can be efficiently performed in a small memory and in a short time. Examples of conventional hierarchical design systems are described in Patent Documents 1 to 3.
JP 2004-192227 A JP 2004-302818 A JP 2006-338090 A

  In the conventional flat design method, as described above, since the arrangement area and the wiring area are mixed, it is difficult to predict which path the wiring between the logic gates becomes a failure because the logic gate becomes an obstacle. There are problems that it is difficult to control and that wiring bypass is a major factor that makes it difficult to design the timing of semiconductor circuits. In order to solve this problem, a flat design method in which arrangement and wiring are integrated has been proposed. However, in this case, there is a problem that the scale of a circuit that can be handled is limited.

  Although the divided design method can solve the problems of the flat design method described above, in order to divide and solve the problem, as shown in FIG. 14, there is a logic cone that spans a plurality of logic blocks. In this case, it is necessary to divide and set the original timing constraints for the partial logic circuits included in each block.

  For example, when the original restriction is 10 nanoseconds, it is necessary to perform processing such as dividing the value obtained by reducing the wiring delay between the logical blocks into four.

  Since it is difficult to set appropriate timing constraints for each block, the problem that the overall optimization of the result is lost by dividing the problem that should be optimized collectively, so-called division There is a problem of loss.

  Also, in the conventional hierarchical design, since logical blocks are generated based on the logical design hierarchy, the logical book size often varies and is not suitable for using a regular wiring structure between logical blocks.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit design method and design apparatus that facilitate the estimation and controllability of inter-gate wiring that is important in timing design without losing the overall optimization of logic circuit layout design. There is.

  In order to achieve the above object, a method for designing a semiconductor integrated circuit according to the present invention is based on component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed. A method for designing a semiconductor integrated circuit performed by a design apparatus for designing a circuit, the step of dividing a chip region in which a plurality of logic gates and a plurality of flip-flops are arranged based on the component information into a plurality of regions A logic circuit in which different flip-flops are used as an input unit and an output unit, and at least one of the logic gates is connected between the input unit and the output unit without a flip-flop being connected, Based on the information, the logic circuit that is extracted from the chip area and is entirely contained in one of the areas is a core logic block. A step of setting the logic circuit extending over two or more regions as an interface logic block, and a core logic block design step of performing a layout design of the core logic block based on the wiring connection information and the timing constraint And an inter-area wiring design step for designing a wiring layout between the areas based on the wiring connection information, and the interface based on the wiring connection information, the timing constraints, and the results of the wiring layout design. And an interface logic block design step for designing a layout of the logic block.

  According to another aspect of the invention, there is provided a semiconductor integrated circuit design apparatus for designing a semiconductor integrated circuit based on component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed. An apparatus for designing an integrated circuit, wherein the chip area in which a plurality of logic gates and a plurality of flip-flops are arranged based on the component information is divided into a plurality of areas, and is different as an input unit and an output unit Based on the wiring connection information, a logic circuit in which a flip-flop is used and no flip-flop is connected between the input unit and the output unit and at least one of the logic gates is connected from the chip region. Before extracting the logic circuit that is entirely contained in one area as a core logic block and spanning two or more areas Based on the setting means which sets the logic circuit as an interface logic block, the core logic block layout design means for designing the layout of the core logic block based on the wiring connection information and the timing constraint, and the wiring connection information. Wiring layout design means for designing the layout of the wiring between the regions, and an interface logic block for designing the layout of the interface logic block based on the wiring connection information, the timing constraint, and the result of the layout design of the wiring Layout design means.

  According to the above invention, the layout design of the core logic block, the interface logic block, and the wiring between the regions is performed individually. For this reason, at the time of wiring between regions, the logic gate arrangement does not become an obstacle, and it becomes easy to control the wiring structure for minimizing the wiring delay between regions, such as wiring width, wiring spacing, and repeater insertion. In addition, since the design object is divided and designed, a large-scale integrated circuit can be performed in a small memory and in a short time.

  Since all of the input / output units of the core logical block are FFs, it is possible to design each core logical block independently of other logical blocks without dividing timing constraints between FFs.

  For the design of interface logical blocks, for example, the entire set of interface logical blocks that span multiple areas can be optimized in consideration of the exact delay based on the actual inter-area wiring results. It is possible to solve the timing design convergence deterioration problem due to the division loss of the design.

  Therefore, it is possible to easily estimate and control the inter-gate wiring that is important in the timing design without losing the overall optimization of the logic circuit layout design.

  The design apparatus further includes region setting means for setting a core logical block layout region, an interface logical block layout region, and a wiring layout region between the regions in the chip region, and the core logical block layout The design means performs layout design of the core logic block in the core logic block layout area, the wiring layout design means performs layout design of wiring between the areas in the wiring layout area between the areas, and The interface logical block layout design means preferably designs the interface logical block in the interface logical block layout area.

  According to the above invention, the core logic block, the wiring between the areas, and the interface logic block are designed in the layout area corresponding to each. For this reason, at the time of wiring between regions, the logic gate arrangement does not become an obstacle, and it becomes easy to control the wiring structure for minimizing the wiring delay between regions, such as wiring width, wiring spacing, and repeater insertion.

  In addition, the dividing unit temporarily provisions the plurality of logic gates and the plurality of flip-flops in a chip arrangement region based on the component information to generate the chip region, and the chip region. Divided grid setting means for generating the plurality of areas by dividing into a grid, wherein the setting means extracts the logic circuit from the chip area based on the wiring connection information, and , The moving means for moving the logic circuit between the areas, and the moved logic that is entirely included in the one area, so that the proportion of the logic circuit that is entirely included in the area increases. A logic block decision in which the circuit is the core logic block and the moved logic circuit across the two or more areas is the interface logic block. It is desirable to include a means.

  According to the above invention, it is possible to reduce the size of the interface logical block. Therefore, it is possible to facilitate batch optimization of the entire interface logic block.

  The setting means may further include an overlapping logic gate of the moved logic circuit that is entirely included in the one area and the moved logic circuit that extends over the two or more areas. A logic block that duplicates the overlapping logic gates and separates the logic circuit that is entirely included in the one area and the logic circuit that extends over the two or more areas so as to be mutually exclusive. The logical block determination means includes a dividing unit, and the exclusive logic circuit that is entirely included in the one area is defined as the core logic block, and the exclusive logic circuit extending over the two or more areas is defined as the exclusive logic circuit. The interface logic block is desirable.

  According to the above invention, even if there are overlapping logic gates of the logic circuit, it becomes possible to appropriately separate the logic circuits without changing their logic functions, and without losing the overall optimization of the logic circuit layout design. This makes it possible to easily estimate and control the inter-gate wiring, which is important in timing design.

  Further, it is preferable that the interface logical block layout design means collectively perform layout design of all interface logical blocks in consideration of inter-block wiring delay obtained from the result of the wiring layout design.

  According to the above invention, in consideration of the accurate delay based on the actual inter-area wiring result, the entire interface logical block set extending over a plurality of areas is collectively optimized. It is possible to solve the timing design convergence deterioration problem due to loss.

  According to the present invention, it is possible to easily estimate and control the inter-gate wiring that is important in the timing design without losing the overall optimization of the logic circuit layout design.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a semiconductor integrated circuit design apparatus (hereinafter referred to as “design apparatus”) 1 according to an embodiment of the present invention.

  In FIG. 1, a design apparatus 1 includes a chip information input unit 1-01, a temporary gate arrangement unit 1-02, a division grid setting unit 1-03, a gate grouping unit based on an FF input logic cone and a division grid. 1-04 (hereinafter referred to as “grouping means”), core logical block and interface logical block dividing means (hereinafter referred to as “logical block dividing means”) 1-05, core logical block and interface logical block Layout area determination means (hereinafter referred to as “layout area determination means”) 1-06, core logical block layout design means 1-07, inter-block wiring layout design means 1-08, and interface logical block layout design Means 1-09 and layout design integration means 1-10 are included.

  The temporary gate placement means 1-02 and the divided grid setting means 1-03 constitute a dividing means 1-11, and the grouping means 1-44, logical block dividing means 1-05, and layout area determining means 1-06 The setting means 1-12 is configured, and the layout area determining means 1-06 and the inter-block wiring layout design means 1-08 constitute the area setting means 1-13.

  The design device 1 is configured by a general computer including a control device, a storage device, an input device, and a display device. These parts are not shown.

  Each of the above means is constructed and controlled on a storage device such as a ROM or a RAM by a control device that operates according to a program stored in the storage device.

  The chip information input unit 1-01 inputs information (chip data) related to the gate level netlist of the semiconductor integrated circuit chip to be designed to the storage device (specifically, the temporary gate arrangement unit 1-02). .

  The information about the netlist includes, for example, information on components in the integrated circuit chip (for example, information on a plurality of logic gates and a plurality of flip-flops), wiring connection information, and timing constraints (constraint values) between FFs. Including. The design apparatus 1 designs a semiconductor integrated circuit based on information on the netlist.

  Temporary gate placement means 1-02 temporarily places logic gates and FFs in the integrated circuit chip in the chip placement area based on chip data (specifically, component information) received from chip information input means 1-01. Then, a chip area is generated.

  The division grid setting means 1-03 sets a division line that divides the entire chip area where the logic gates and FFs are temporarily arranged into a plurality of grid areas (lattice).

  The grouping unit 1-44 is an example of a moving unit, which extracts all the logic cones included in the entire chip area based on information on the netlist (specifically, wiring connection information). It is determined whether it is included in one grid or spans multiple grids.

  The logic cone is an example of a logic circuit in which different FFs are used as the input unit and the output unit, and at least one of the logic gates is connected between the input unit and the output unit without connecting the FF.

  A logic cone included in one lattice (hereinafter referred to as “core logic cone”) is a candidate for an element constituting the core logic block, and a logic cone (hereinafter referred to as “interface logic cone”) across a plurality of lattices. ) Is a candidate for an element constituting the interface logical block.

  The grouping means 1-44 moves the logic cones between the lattices (regions) so that the ratio of the core logic cones in the lattice (regions) increases.

  When there is an overlapping partial circuit (overlapping logic gate) between the core logic cone and the interface logic cone, the logic block dividing means 1-05 doubles the overlapping partial circuit so that the core logic cone and the interface logic Separate cones into exclusive logic sets (logic circuits).

  The layout area determination unit 1-06 is an example of a logical block determination unit, and the entire area is included in one area, and the moved logical cone is a core logical block and is moved across two or more areas. The logic cone is an interface logic block.

  The layout area determining means 1-06 uses an exclusive logic cone that is entirely contained in one area as a core logic block, and an exclusive logic cone that spans two or more areas as an interface logic block. .

  The layout area determining unit 1-06 sets a core logical block layout area and an interface logical block layout area in the chip area based on the core logical block and the interface logical block.

  The core logical block layout design means 1-07 performs a core logical block layout design in the core logical block layout area based on information on the netlist (specifically, wiring connection information and timing constraints).

  The wiring layout design means 1-08 sets the wiring layout area between the areas in the entire integrated circuit area, and based on the netlist information (specifically, the wiring connection information), the layout of the wiring between the areas. Design is performed in the wiring layout area between the areas.

  The interface logical block layout design means 1-09 performs interface logical block layout design based on netlist information (specifically, wiring connection information and timing constraints) and the result of wiring layout design.

  The layout design integration means 1-10 integrates the core logical block layout, the interface logical block layout, and the inter-logical block layout, and completes the chip layout design.

  The dividing unit 1-11 divides a chip area where a plurality of logic gates and a plurality of flip-flops are arranged based on the component information into a plurality of areas.

  The setting means 1-12 extracts a logic cone from the chip area based on the wiring connection information, sets a logic cone that is entirely contained in one area as a core logic block, and sets a logic cone that spans two or more areas. Let it be an interface logic block.

  The area setting means 1-13 sets a core logical block layout area, an interface logical block layout area, and a wiring layout area between the areas in the chip area.

  Next, the operation will be described.

  Specifically, the operation of each of the above means will be described in detail with reference to FIGS. 2, 3, 4, 5, 6, 6, 7, 8, and 10. FIG.

  When the chip information input unit 1-01 receives chip data related to the gate level net list of the circuit chip to be designed, the chip information input unit 1-01 provides the chip data to the temporary gate arrangement unit 1-02.

  When the temporary gate placement means 1-02 receives the chip data from the chip information input means 1-01, the temporary gate placement means 1-02 performs the temporary placement of the logic gate and the FF in the circuit chip on the chip placement area based on the chip data, A chip region in which the gate and FF are provisionally arranged is generated.

  At this time, the temporary gate placement unit 1-02 collectively processes the temporary placement for all the logic gates and all the FFs included in the circuit. This process is a rough provisional arrangement for giving a circuit division guideline to the circuit division process performed by the following means, and does not require a detailed optimization process. Therefore, batch processing is possible even for a large-scale circuit.

  When the temporary placement is completed, the temporary gate placement unit 1-2 provides the chip area and the chip data with the divided grid setting unit 1-03.

  Upon receiving the chip area and the chip data, the divided grid setting unit 1-03 sets a dividing line that divides the entire chip area on which temporary placement has been performed into a plurality of grid-shaped areas. By changing the size of one grid here, it is possible to control the size of the logical block generated in the subsequent processing.

  FIG. 2 is a diagram for explaining the operation of the temporary gate placement means 1-02 and the divided grid setting means 1-03. In FIG. 2, the temporary gate placement means 1-02 places FFs and logic gates on the chip at once, and the divided grid setting means 1-03 sets a 2 × 2 grid over the entire chip area.

  When the divided grid setting means 1-03 sets a plurality of areas, the divided grid setting means 1-03 provides the plurality of areas and the chip data to the grouping means 1-44.

  When grouping means 1-44 receives a plurality of areas and chip data, it extracts all the logic cones from the chip area consisting of a plurality of areas based on the chip data, and each logic cone is included in one lattice ( Whether the core logic cone) or straddles multiple grids (interface logic cone).

  At this stage, there is usually a partial overlap between the core logic cone and the interface logic cone.

  In order to facilitate the timing design, it is desirable that the number of gates included in the core logic block is larger. Therefore, the grouping unit 1-44 is designed to increase the size of the logic cone serving as the core logic cone. The gate movement is performed in units of logical cones.

  3 and 4 are diagrams for explaining the operation of the grouping means 1-44.

  At this stage, as shown in FIG. 3, the core logic cone 3-01 and the interface logic cone 3-02 are overlapped. This duplication is removed in the subsequent logic duplexing process.

  FIG. 4 is a diagram for explaining the operation for increasing the size of the core logic cone, in other words, the operation for increasing the proportion of the core logic cone in the region.

  The grouping means 1-44 performs logical cone movement between lattices by executing the processing example 1 shown in FIG. 4A and the processing example 2 shown in FIG. 4B. For this reason, in FIG. 4, in the initial state, the logic cone that was the interface logic cone is changed to the core logic cone.

  In this process, there is also a logic cone that is changed from the core logic cone to the interface logic cone, but the grouping means 1-44 calculates the increase / decrease of the core logic cone size by this process, so that the core logic cone size increases. Move the gate.

  When the grouping unit 1-44 finishes moving the logical cone, the grouping unit 1-44 provides the movement result and chip data to the logical block dividing unit 1-05.

  When the logical block dividing means 1-05 accepts the movement result and the chip data, the core logic cone and the interface logic cone are exclusive by duplicating the overlapping partial circuit of the core logic cone and the interface logic cone. Separate into logical sets.

  FIG. 5 is a diagram for explaining the operation of the logical block dividing means 1-05.

  In FIG. 5A, the logic block dividing means 1-05 duplicates the logic duplication target circuit 5-01, thereby changing the core logic cone 5-02 without changing the operation of the logic circuit. Separate interface logic cone 5-03 into exclusive logic circuits.

  More specifically, as shown in FIG. 5 (b), the logic block dividing means 1-05 is an overlapping logic gate (duplication target gate) of the core logic cone 5-02 and the interface logic cone 5-03. By multiplexing 5-04, the core logic cone 5-02 and the interface logic cone 5-03 are separated without changing the logic function.

  If there is no logic duplexing target circuit 5-01, the logic block dividing means 1-05 does not perform the logic duplexing process.

  Thereafter, the logical block dividing unit 1-05 provides the processing result and the chip data to the layout area determining unit 1-06.

  Upon receiving the processing result and the chip data, the layout area determining unit 1-06 sets the layout areas of the core logical block and the interface logical block.

  Specifically, the layout area determining unit 1-06 first sets a logic circuit in which the core logic cone sets in each lattice are combined as one core logic block.

  Subsequently, the layout area determining unit 1-06 sets the core logical block layout area at the center of the lattice area based on the size of the generated core logical block.

  Subsequently, the layout area determining unit 1-06 converts the logic circuit included in the interface logic cone spanning the plurality of grid areas into a plurality of grid areas based on the arrangement positions obtained by the temporary gate arrangement unit 1-02. A logic circuit that is divided and put together a part of the interface logic cone in each lattice area is defined as an interface logic block.

  Subsequently, the layout area determining unit 1-06 sets the interface logical block layout area around the core logical block layout area based on the size of the interface logical block.

  Subsequently, the layout area determining unit 1-06 sets all the contacts of the generated core logic block and interface logic block to FF.

  FIG. 6 is a diagram for explaining the operation of the layout area determining means 1-06.

  The layout area determination means 1-06 creates a core logical block by collecting core logical cone sets in each lattice area, and sets the core logical block layout area 6-01 at the center of the lattice area.

  Subsequently, the layout area determination means 1-06 divides an interface logic cone that spans multiple grids between the grids (see the divided interface logic cone 6-03), and as an interface logic block within each grid area. In summary, a layout area 6-04 for an interface logical block is set around the core logical block layout area 6-01.

  The layout area determining unit 1-06 sets all the contacts of the core logical block and the interface logical block as FFs (for example, the core logical block boundary FF6-02). For this reason, there is no logical path between FFs that crosses the core logical block and the interface logical block.

  Thereafter, the layout area determining unit 1-06 provides its processing result and chip data to the core logical block layout design unit 1-07 and the inter-block wiring layout design unit 1-08.

  When the core logical block layout design means 1-07 receives the processing result and the chip data, the core logical block layout design means 1-07 performs a layout design in each core logical block based on the processing result and the chip data (wiring connection information and timing constraints).

  Since the boundaries of the core logical blocks are all FF, there is no logical path connected to other logical blocks such as the logical path 104-03 shown in FIG. Therefore, the core logical block layout design unit 1-07 does not need to divide the timing constraints included in the chip data, and can perform layout design independently of other blocks for all the core logical blocks.

  The layout design in each core logic block can be performed in a small memory and in a short time because the size is small compared to the entire integrated circuit.

  FIG. 7 is a diagram for explaining the operation of the core logical block layout design means 1-07.

  In FIG. 7, four small-scale core logic blocks having FF as input / output boundaries are generated from the entire logic circuit, and the core logic block layout design means 1-07 performs the original timing for the layout design of each core logic block. Do not split the constraints independently.

  On the other hand, when the inter-block wiring layout design unit 1-08 receives the processing result and the chip data from the layout area determination unit 1-06, the inter-block wiring layout design unit 1-08 determines the wiring between the logical blocks based on the processing result and the chip data (wiring connection information). Perform layout design.

  Specifically, the inter-block wiring layout design means 1-08 provides a dedicated inter-block wiring area (inter-wiring layout area) where there is no logical gate arrangement that becomes an obstacle in the conventional “flat design method”. Design wiring between areas. Therefore, the inter-block wiring layout design means 1-08 can easily control the wiring path and delay. For wiring path and delay control, for example, wiring path design with few detours for the purpose of wiring delay minimization, wiring width change, wiring interval change, repeater insertion, inter-block wiring required amount For example, adjustment of the block interval may be mentioned.

  FIG. 8 is a diagram for explaining the operation of the inter-block wiring layout design means 1-08.

  The inter-block wiring layout design means 1-08 converts the logical block into a black box (refer to the black block logical block 8-02), and a dedicated wiring area between the logical blocks (inter-wiring layout area between areas) 8-03 In the region 8-03, based on the wiring connection information, the inter-block wiring path is wired in the shortest time, and the repeater 102-01 is inserted in order to optimize the delay.

  Thereafter, the processing of the inter-block wiring layout design means 1-08 provides the wiring result and chip data to the interface logic block layout design means 1-09.

  When the interface logical block layout design means 1-09 accepts the wiring result and chip data, the interface logical block layout design means 1-09 fixes the inter-logical block wiring result generated by the inter-block wiring layout design means 1-08, and provides wiring connection information, timing constraints, In consideration of the inter-block wiring delay obtained from the block wiring result, the layout design of the entire interface logic block set is collectively performed.

  In other words, the interface logical block layout design means 1-09 uses the value obtained by subtracting the delay between the logical blocks calculated from the fixed inter-logical block wiring from the original timing constraint as the timing constraint, and performs the interface logic block layout design. Is performed in a lump without dividing.

  For example, when the original timing constraint is 10 nanoseconds and the inter-block wiring delay is 4 nanoseconds, the interface logical block layout design means 1-09 performs the interface logical block layout design using 6 nanoseconds as the timing constraint. At this time, each interface logical block is restricted to be placed and routed in an interface logical block layout area in the logical block to which the interface logical block belongs.

  FIG. 9 is a diagram for explaining the operation of the interface logical block layout design means 1-09.

  The interface logical block layout design means 1-09 fixes the layout (wiring) between blocks, and performs layout design of the entire interface logical block in consideration of the delay of that portion. At this stage, most of the logical blocks are black-boxed as core logical blocks, so the size of the interface logical block is reduced, and such batch processing is possible.

  When the processing of the interface logical block layout design means 1-09 is completed, the layout design integration means 1-10 integrates the core logical block layout, interface logical block layout, and inter-logical block layout obtained in the previous process. Then, the chip layout design is completed.

  FIG. 10 is a diagram for explaining the operation of the layout design integration means 1-10.

  The layout design integration means 1-10 integrates the core logical block layout, the interface logical block layout, and the layout between logical blocks, and completes the layout design of the entire chip.

  According to the present embodiment, the following effects can be obtained.

  The entire circuit is divided into a plurality of logic blocks (areas), and the layout is designed by setting the logic block layout area and the layout area between the logic blocks. It becomes easy to control the inter-logic-block wiring structure for minimizing the inter-block wiring delay, such as the width, the wiring interval, and the repeater insertion.

In the core logical block, the input / output section is all FF, and there is no logical path between the core logics as shown in FIG. Design can be done independently of other logic blocks.
As for the design of interface logical blocks, it is possible to optimize the entire set of interface logical blocks across multiple logical blocks in consideration of the exact delay based on the actual inter-block wiring results. Can solve the problem of deterioration of timing design convergence due to division loss.

  This collective optimization is possible because the logical block is divided into a core logical block and an interface logical block, and the size of the interface logical block is reduced.

  Moreover, according to the present Example, there exist the following effects.

  According to this embodiment, the layout design of the core logic block, the interface logic block, and the wiring between the regions is individually performed. For this reason, at the time of wiring between regions, the logic gate arrangement does not become an obstacle, and it becomes easy to control the wiring structure for minimizing the wiring delay between regions, such as wiring width, wiring spacing, and repeater insertion. In addition, since the design object is divided and designed, a large-scale integrated circuit can be performed in a small memory and in a short time.

  Since all of the input / output units of the core logical block are FFs, it is possible to design each core logical block independently of other logical blocks without dividing timing constraints between FFs.

  For the design of interface logical blocks, for example, the entire set of interface logical blocks that span multiple areas can be optimized in consideration of the exact delay based on the actual inter-area wiring results. It is possible to solve the timing design convergence deterioration problem due to the division loss of the design.

  Therefore, it is possible to easily estimate and control the inter-gate wiring that is important in the timing design without losing the overall optimization of the logic circuit layout design.

  In this embodiment, the core logic block, the wiring between the areas, and the interface logic block are designed in the layout areas corresponding to each of them.

  In this case, at the time of wiring between regions, the logic gate arrangement does not become an obstacle, and it becomes easy to control the wiring structure for minimizing the wiring delay between regions, such as wiring width, wiring spacing, and repeater insertion.

  Further, the grouping means 1-44 moves the logic cones between the regions so that the proportion of the logic cones that are entirely included in the regions becomes large.

  In this case, it is possible to reduce the size of the interface logical block. Therefore, it is possible to facilitate batch optimization of the entire interface logic block.

  Further, when there is an overlapping logic gate of a logic cone that is entirely contained in one area and a logic cone that extends over two or more areas, the logic block dividing means 1-05 doubles the overlapping logic gate. In other words, a logic cone that is entirely contained in one region and a logic cone that spans two or more regions are separated from each other so as to be mutually exclusive.

  In this case, even if there are overlapping logic gates, it is possible to properly separate the logic cones without changing their logic functions, which is important in timing design without losing the overall optimization of the logic circuit layout design. It becomes possible to easily estimate and control the wiring between the gates.

  In this embodiment, the interface logical block layout design means 1-09 collectively performs layout design of all interface logical blocks in consideration of inter-block wiring delay obtained from the result of wiring layout design. Do.

  In this case, in consideration of the accurate delay based on the actual inter-area wiring result, the entire interface logical block set across multiple areas is optimized in a batch. The timing design convergence problem can be solved.

  In the embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

It is a block diagram which shows the structure of one Example of the hierarchical design apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. FIG. 3 is a diagram illustrating operations of a temporary gate placement unit 1-02 and a divided grid setting unit 1-03 of the semiconductor integrated circuit design apparatus of FIG. 1; It is a figure which shows the operation | movement of the gate grouping means 1-44 on the basis of FF input logic cone and a division | segmentation grating | lattice of the design apparatus of the semiconductor integrated circuit of FIG. It is a figure which shows the operation | movement of the gate grouping means 1-44 on the basis of FF input logic cone and a division | segmentation grating | lattice of the design apparatus of the semiconductor integrated circuit of FIG. FIG. 5 is a diagram showing operations of a core logic block and interface logic block dividing means 1-05 of the semiconductor integrated circuit design apparatus of FIG. 1; FIG. 6 is a diagram showing an operation of a layout area determining unit 1-06 for a core logic block and an interface logic block of the semiconductor integrated circuit design apparatus of FIG. 1; It is a figure which shows operation | movement of the core logic block layout design means 1-07 of the design apparatus of the semiconductor integrated circuit of FIG. FIG. 8 is a diagram showing an operation of an inter-block wiring layout design means 1-08 of the semiconductor integrated circuit design apparatus of FIG. 1; It is a figure which shows operation | movement of the interface logic block layout design means 1-09 of the design apparatus of the semiconductor integrated circuit of FIG. It is a figure which shows operation | movement of the layout design integration means 1-10 of the design apparatus of the semiconductor integrated circuit of FIG. It is explanatory drawing regarding the terminology used in the timing design of LSI and this specification. It is a figure which shows the flat layout design method which is one of the conventional methods, and its subject. It is a figure which shows the division | segmentation design method which is one of the conventional methods. It is a figure which shows the subject of the division | segmentation design method which is one of the conventional methods.

Explanation of symbols

101-01 Flip-flop (FF)
101-02 logic gate
101-03 Signal line
101-04 Logical path
101-05 Timing constraints
101-06 Flip-flop (FF) input logic cone
102-01 repeater
102-02 Signal wiring
102-03 Detour wiring
103-01 Logical block layout area
103-02 Logical block wiring area
103-03 Signal wiring between logic blocks
104-01 Starting point FF
104-02 End FF
104-03 Path across multiple logical blocks
1 Semiconductor integrated circuit design equipment
1-01 Chip information input method
1-02 Temporary gate placement means
1-03 Split grid setting method
1-04 Gate grouping means based on FF input logic cone and split grid
1-05 Core logical block and interface logical block dividing means
1-06 Means for determining layout area of core logical block and interface logical block
1-07 Core logical block layout design method
1-08 Inter-block wiring layout design method
1-09 Interface Logic Block Layout Design Method
1-10 Layout design integration means
1-11 Division method
1-12 Setting method
1-13 Area setting method
2-01 Temporary Gate Placement Results
2-02 Split grid lines
3-01 Logic cone closed in lattice area (core logic cone)
3-02 Logic Cone over Grid Area (Interface Logic Cone)
4-01 Logic Logic Moving to Increase Core Logic Cone Size
4-02 Increasing the size of a closed logical cone in a lattice area by moving the logical cone
5-01 Logic Duplication Target Circuit
5-02 Core Logic Cone
5-03 Interface Logic Cone
5-04 Duplicated gates
6-01 Core logical block layout area
6-02 Core logic block boundary flip-flop
6-03 Divided Interface Logic Cone
6-04 Interface Logical Block Layout Area
6-05 Inter-block signal
7-01 Core Logical Block Layout Design
8-01 Inter-block wiring layout design
8-02 Black boxed logical block
9-01 Black Boxed Core Logic Block
9-02 Interface Logical Block Layout Design
9-03 Wiring layout between fixed blocks
9-04 Interface Logic Blocks for Simultaneous Optimization
10 Integrated layout design

Claims (10)

A design method of a semiconductor integrated circuit performed by a design apparatus that designs the semiconductor integrated circuit based on component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed,
A dividing step of dividing a chip area in which a plurality of logic gates and a plurality of flip-flops are arranged based on the component information into a plurality of areas;
The wiring connection information includes a logic circuit in which different flip-flops are used as an input unit and an output unit, and at least one of the logic gates is connected between the input unit and the output unit without a flip-flop being connected. And setting the logic circuit that is extracted from the chip area and is entirely contained in one area as a core logic block, and the logic circuit across two or more areas as an interface logic block When,
A core logic block design step for performing a layout design of the core logic block based on the wiring connection information and the timing constraint;
Based on the wiring connection information, an inter-area wiring design step for designing a layout of wiring between the areas,
A method for designing a semiconductor integrated circuit, comprising: an interface logic block design step for designing a layout of the interface logic block based on the wiring connection information, the timing constraint, and a result of the layout design of the wiring. The method for designing a semiconductor integrated circuit according to claim 1,
The chip region further includes a region setting step for setting a core logical block layout region, an interface logical block layout region, and a wiring layout region between the regions,
In the core logical block design step, layout design of the core logical block is performed in the core logical block layout area,
In the inter-region wiring design step, the layout design of the wiring between the regions is performed in the wiring layout region between the regions,
In the interface logic block design step, the interface logic block is designed in the interface logic block layout region. The method for designing a semiconductor integrated circuit according to claim 1,
In the dividing step, the plurality of logic gates and the plurality of flip-flops are provisionally arranged in a chip arrangement area based on the component information to generate the chip area, and the chip area is divided into a lattice shape to thereby generate the chip area. Generate multiple regions,
In the setting step, in the area, the logic circuit is moved between the areas so that a ratio occupied by the logic circuit that is entirely included in the area is increased, and the entire area is included in the one area. A method of designing a semiconductor integrated circuit, wherein the moved logic circuit is the core logic block, and the moved logic circuit across the two or more regions is the interface logic block. The method of designing a semiconductor integrated circuit according to claim 3,
In the setting step, if there is an overlapping logic gate between the moved logic circuit that is entirely included in the one area and the moved logic circuit that extends over the two or more areas, By duplicating overlapping logic gates, the logic circuit that is entirely included in the one region and the logic circuit that spans the two or more regions are separated from each other so as to be mutually exclusive, A method for designing a semiconductor integrated circuit, wherein the exclusive logic circuit entirely included in a region is the core logic block, and the exclusive logic circuit extending over the two or more regions is the interface logic block. The method for designing a semiconductor integrated circuit according to claim 1,
A method of designing a semiconductor integrated circuit, wherein, in the interface logic block design step, layout design of all interface logic blocks is collectively performed in consideration of inter-block wiring delay obtained from a result of layout design of the wiring. A design apparatus for a semiconductor integrated circuit, which designs the semiconductor integrated circuit based on component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed,
A dividing means for dividing a chip area in which a plurality of logic gates and a plurality of flip-flops are arranged based on the component information into a plurality of areas;
The wiring connection information includes a logic circuit in which different flip-flops are used as an input unit and an output unit, and at least one of the logic gates is connected between the input unit and the output unit without a flip-flop being connected. The logic circuit that is extracted from the chip area and is entirely included in one area is a core logic block, and the logic circuit that spans two or more areas is an interface logic block. When,
Core logical block layout design means for performing layout design of the core logical block based on the wiring connection information and the timing constraint;
A wiring layout design means for designing a layout of wiring between the regions based on the wiring connection information;
A semiconductor integrated circuit design apparatus comprising: an interface logic block layout design unit configured to perform a layout design of the interface logic block based on the wiring connection information, the timing constraint, and a result of the layout design of the wiring. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
The chip area further includes area setting means for setting a core logic block layout area, an interface logic block layout area, and a wiring layout area between the areas,
The core logical block layout design means performs layout design of the core logical block in the core logical block layout area,
The wiring layout design means performs wiring layout design between the regions in a wiring layout region between the regions,
The interface logical block layout design means is a semiconductor integrated circuit design apparatus for designing the interface logical block in the interface logical block layout region. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
The dividing means includes
Temporary gate arrangement means for generating the chip area by temporarily arranging the plurality of logic gates and the plurality of flip-flops in a chip arrangement area based on the component information;
Dividing grid setting means for generating the plurality of regions by dividing the chip region into a lattice shape,
The setting means includes
Based on the wiring connection information, the logic circuit is extracted from the chip area, and the logic circuit between the areas is increased in the area so that a ratio occupied by the logic circuit is entirely included in the area. Moving means for moving
A logic block determining unit that sets the moved logic circuit that is entirely contained in the one area as the core logic block, and sets the moved logic circuit across the two or more areas as the interface logic block; A device for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit according to claim 8,
The setting means further includes an overlapping logic gate of the moved logic circuit that is entirely included in the one area and the moved logic circuit that extends over the two or more areas. Logic block dividing means for duplicating overlapping logic gates and separating the logic circuit that is entirely included in the one area and the logic circuit that spans the two or more areas so as to be mutually exclusive Including
The logic block determination means uses the exclusive logic circuit that is entirely included in the one area as the core logic block, and sets the exclusive logic circuit across the two or more areas as the interface logic block. A semiconductor integrated circuit design apparatus. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
The interface logic block layout design means is a semiconductor integrated circuit design apparatus that collectively performs layout design of all interface logic blocks in consideration of inter-block wiring delay obtained from the result of the wiring layout design. .

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