JP4139236B2 - Timing analysis program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention , De The present invention relates to a timing analysis program that is loaded into a data processing device and causes the data processing device to perform the timing analysis.
[0002]
[Prior art]
As the circuit scale of a semiconductor integrated circuit increases, a design method for hierarchical layout processing that performs layout processing by dividing a chip of the semiconductor integrated circuit into a plurality of blocks has been adopted. Even in the timing analysis based on the actual wiring delay as a result of the layout by such a design method, it is difficult to handle the circuit in the entire chip at a time, and therefore the following hierarchical processing is performed. First, timing analysis is performed on each hierarchical block based on delay information of actual wiring. Next, each hierarchical block is modeled.
[0003]
FIG. 6 is a diagram showing how a hierarchical block is modeled.
[0004]
FIG. 6 shows a hierarchical block 100 expanded to the lowest layer circuit (gate level circuit such as AND, OR, and flip-flop). The hierarchical block 100 includes flip-flops 101, 102, and 103 that are sequential circuits, a buffer 104, and combinational circuits 105, 106, 107, 108, and 109 other than sequential circuits. A clock signal CLK is input to the buffer 104. Further, data signals A and B are input to the combinational circuits 105 and 106. In the hierarchical block 100, predetermined signals X and Y are output based on the input clock signal CLK and data signals A and B.
[0005]
Here, as shown in FIG. 6, the netlist in the hierarchical block (from the input port constituting the combinational circuit 106 to the first stage flip-flop 101, from the last stage flip-flop 103 to the output port constituting the combinational circuit 109, and The clock signal line netlist) and the actual wiring RC information (information in consideration of the electric resistance component and the electric capacity component in the actual wiring) are cut out and modeled (this model is referred to as a “boundary model” for convenience). Using such a “boundary model”, timing analysis is performed at the top level for the entire netlist of semiconductor chips.
[0006]
FIG. 7 is a diagram illustrating a state in which timing analysis is performed at the top level using a boundary model.
[0007]
In FIG. 7, two boundary models 210 and 220 are shown as boundary models of each hierarchical block constituting the block 200 of the entire semiconductor chip. Here, modeling is performed by cutting out (cutting out) the hierarchical blocks, so that the data to be handled is light, but since the boundary information of each hierarchical block 210 and 220 is held as it is, the boundary portion (input) The accuracy from the port to the first stage flip-flop and from the last stage flip-flop to the output port) is guaranteed. The delay information used when performing the timing analysis at the top level is calculated by reading the top level RC information and the RC information corresponding to the boundary models 210 and 220 that are omitted for the hierarchical block. Such a timing analysis method is proposed in Patent Document 1.
[0008]
[Patent Document 1]
JP 2000-76321 A
[0009]
[Problems to be solved by the invention]
When the timing analysis of the hierarchical block is performed, the timing constraint used there is generated by a process called timing budget from the timing constraint of the full chip that is the entire semiconductor chip. In general, there are a plurality of operation modes of a semiconductor circuit, and there are a plurality of timing constraints corresponding to the plurality of operation modes. For this reason, it is necessary to generate a timing constraint for each hierarchical block by performing a process called a timing budget for a plurality of timing constraints. Here, the timing constraint refers to the clock definition (definition of the location where the clock signal is generated, the waveform of the clock signal, etc.), the delay on the input side, and the delay on the output side. Restrictions are applied to the flip-flops, between internal flip-flops, and from the flip-flops at the final stage to the output, and subsequent timing analysis checks whether there are any violations of these restrictions. In addition, a path that should not be seen exceptionally as a timing constraint (a path that is not targeted) is designated as a false path, or a path that does not need to be operated in one cycle is defined as a multi-cycle path. Or specify.
[0010]
FIG. 8 is a diagram for explaining timing budget processing.
[0011]
FIG. 8 shows a block 300 of the entire semiconductor chip. This block 300 includes hierarchical blocks 310 and 320. As shown in FIG. 8, for each of the hierarchical blocks 310 and 320, how many ns is targeted as the delay time, that is, (one clock period−the top delay time) is assigned to both. Here, the top delay time means a delay time from the output port of the block 310 to the input port of the block 320. Also, the clock port of the hierarchical block is found and the clock definition is performed again.
[0012]
FIG. 9 is a diagram illustrating a certain hierarchical block.
[0013]
FIG. 9 shows a hierarchical block 330 including flip-flops 331, 332, 333, a buffer 334, and combinational circuits 335, 336, 337, 338. When calculating the delay time used in the timing analysis of each hierarchical block, it is necessary to correctly set, for example, the dullness of the input port signal at the boundary of the hierarchical block 330 and the load of the output port. In addition, if the input dullness of the clock signal CLK line is not set correctly, the dullness of the clock signal CLK related to the flip-flops 331, 332, and 333 in the blocks in the paths P1 and P2 that can be verified only by the timing analysis of the hierarchical block 330. And propagation delay becomes inaccurate. In order to correctly estimate the dullness of the clock port of the hierarchical block 330, the top-level wiring is determined first, and the calculation for calculating the dullness along the route from the top clock source to the hierarchical block 330 is performed. It is necessary to obtain the dullness and use this for the delay calculation in the hierarchical block 330. Such processing is complicated, and the clock port of the hierarchical block 330 is a point in the middle of wiring between primitive cells (cells whose wiring pattern is predetermined and whose characteristics are known). That is, there is a problem that the estimation accuracy of the delay time is also lowered.
[0014]
In view of the above circumstances, the present invention provides a timing solution that can perform timing analysis of the entire circuit in a short time while maintaining high estimation accuracy of delay information of actual wiring. Analysis The purpose is to provide a program.
[0015]
[Means for Solving the Problems]
The timing analysis method of the present invention that achieves the above object is a timing analysis method for performing timing analysis of a circuit in which a hierarchical layout in which layout processing is performed by dividing into a plurality of hierarchical blocks is performed.
A flat expansion is performed for expanding at least one of the plurality of hierarchical blocks into a lowermost circuit, and an input port of the hierarchical block for other hierarchical blocks excluding the at least one hierarchical block Create a boundary model consisting of a netlist of clock lines extending from the first stage flip-flop to the first stage flip-flop, from the last stage flip-flop to the output port of the hierarchical block, and within the hierarchical block. Timing analysis performed in a mode in which boundary models are combined with a hierarchical block is performed on a plurality of modes in which all of the plurality of hierarchical blocks are flat-developed as a whole.
[0016]
Here, flat development is performed for all of the plurality of hierarchical blocks to obtain delay information of the entire circuit, and unnecessary delay information for the boundary model is deleted from the delay information to obtain delay information used in the timing analysis. It is preferable to produce.
[0017]
Moreover, it is preferable to generate a timing constraint to be used in the timing analysis by deleting a timing constraint portion unnecessary for the boundary model from the timing constraint of the entire circuit.
[0018]
Further, it is also preferable that the timing analysis is sequentially performed for the plurality of aspects.
[0019]
Here, the lowermost circuit in the present invention will be described. The lowermost circuit in the present invention indicates not only a primitive cell (level of gate, flip-flop, etc.) whose wiring pattern is predetermined and whose characteristics are known, but also hardware whose characteristics are also predetermined and whose characteristics are known. Includes macros and the like. That is, for cells and macros that are registered in the cell library and whose characteristics are known, there is no need to perform timing analysis by expanding the cells and macros to a lower hierarchy.
[0020]
However, when a completely new large-scale chip is designed without using a hard macro or the like, all hierarchical blocks are designed with the primitive cell level as the lowest layer circuit.
[0021]
The estimation accuracy of the delay information of the actual wiring is highest at the stage where the flat development that develops to the lowermost circuit is performed. However, it is not practical to perform timing analysis by performing flat development on a large-scale circuit configuration, which is not practical. Therefore, it is divided into a plurality of hierarchical blocks, and among these hierarchical blocks, several hierarchical blocks are selected within the range where timing analysis is possible, and flat development is performed. Perform analysis. After this timing analysis, the hierarchical block to be flattened next is selected and the timing analysis is performed in the same manner. By repeating this, the entire circuit (full chip) as a whole is equivalent to performing flat development and timing analysis. In this case, the conventional method reads the top-level RC information, the flatly expanded hierarchical block reads the flat expanded RC information, and the boundary modeled hierarchical block reads the RC information corresponding to the outlined boundary block to calculate the delay. Need to do. Such a delay calculation requires a relatively long time. Further, when the combination of hierarchical blocks to be flattened is changed, it is necessary to change the RC information to be read and perform delay calculation again. Therefore, in the timing analysis method of the present invention, first, a full-chip delay calculation is performed based on RC information obtained by flattening all, and the delay information is stored. By deleting the delay information of the unnecessary part of the hierarchical block to be boundary modeled from the stored delay information, the delay calculation process itself that is necessary every time can be omitted. It takes much less time to delete the delay information than to calculate the delay. By doing in this way, it is possible to analyze the timing of the flatly developed hierarchical block with the same accuracy as the timing analysis of the entire chip. Further, since the timing analysis of the hierarchical block is not performed for the timing constraint used for the timing analysis, the timing budget itself becomes unnecessary. It is possible to use this timing constraint by deleting only the information of the part cut out in the modeled hierarchical block from the timing restriction for full chip (for example, the false path set between the flip-flops to be cut out) etc). This process itself is simple, and the timing constraint for each operation mode can be easily converted. As described above, the timing analysis in which only a part of the hierarchical blocks is flat-developed can also be executed separately and concurrently, so that the total analysis time can be shortened. Therefore, it is possible to perform timing analysis in a short time while maintaining high estimation accuracy of delay information of actual wiring.
[0022]
The timing analysis program of the present invention that achieves the above object is executed in a data processing apparatus that executes the program, and the data processing apparatus is subjected to a hierarchical layout in which layout processing is divided into a plurality of hierarchical blocks. In the timing analysis program that performs timing analysis of the circuit
In the data processing device, flat expansion is performed for expanding at least one hierarchical block of the plurality of hierarchical blocks into a circuit of the lowest layer, and other hierarchical blocks excluding the at least one hierarchical block Create a boundary model consisting of a netlist of clock lines extending from the input port of the hierarchical block to the flip-flop of the first stage, from the flip-flop of the final stage to the output port of the hierarchical block, and into the hierarchical block. The timing analysis performed in a mode in which the expanded hierarchical block and the boundary model-structured hierarchical block are mixed is performed on a plurality of modes in which all the plurality of hierarchical blocks are flatly developed as a whole.
[0023]
Here, the data processing apparatus performs flat development on all of the plurality of hierarchical blocks to obtain delay information of the entire circuit, deletes unnecessary delay information from the delay model in the boundary model, and performs the timing analysis. It is preferable to generate delay information used in the above.
[0024]
Further, it is preferable that the data processing apparatus deletes a timing constraint portion unnecessary for the boundary model from the timing constraint of the entire circuit, and generates a timing constraint used in the timing analysis.
[0025]
Further, it is preferable that the data processing apparatus sequentially execute the timing analysis for the plurality of aspects.
[0026]
The timing analysis program of the present invention is executed in a data processing apparatus that executes the program, and causes the data processing apparatus to perform the timing analysis of the present invention. Timing analysis can be performed in a short time while maintaining.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0028]
FIG. 1 is a perspective view of a data processing apparatus loaded with an embodiment of the timing analysis program of the present invention.
[0029]
Although the details will be described later, the timing analysis program stored in the CD-ROM 2 is loaded into the data processing apparatus 1 shown in FIG. 1 to realize an embodiment of the timing analysis method of the present invention. First, the configuration of the data processing apparatus 1 will be described.
[0030]
As the data processing apparatus 1, a computer generally called a workstation or a personal computer can be used. The communication line 4 connected to the data processing apparatus 1 is a communication line such as the Internet or a LAN (Local Area Network).
[0031]
The data processing device 1 displays an image and a character string on a display screen 1_2a according to an instruction from a main body 1_1 having a CPU (central processing unit), a RAM (random access memory), a hard disk, a communication board, and the like. By specifying an arbitrary position on the display unit 1_2, the keyboard 1_3 for inputting a user instruction to the data processing apparatus 1, and the display screen 1_2a, the icon or the like displayed at that position is specified. The mouse 1_4 for inputting the instruction is provided.
[0032]
The main body 1_1 further has a flexible disk (not shown), a flexible disk loading port 1_1a into which the CD-ROM 2 is loaded, and a CD-ROM loading port 1_1b in appearance.
[0033]
FIG. 2 is a hardware configuration diagram of the data processing apparatus having the appearance shown in FIG.
[0034]
The hardware configuration diagram of FIG. 2 shows CPU 1_11, RAM 1_12, hard disk controller 1_13, flexible disk drive 1_14, CD-ROM drive 1_15, mouse controller 1_16, keyboard controller 1_17, display controller 1_18, and communication board 1_19. They are connected to each other by a bus 5.
[0035]
FIG. 3 is a schematic diagram of a CD-ROM in which an embodiment of the timing analysis program of the present invention is incorporated.
[0036]
A CD-ROM 2 shown in FIG. 3 incorporates a timing analysis program 2_1 described below.
[0037]
The timing analysis program 2_1 is executed in the data processing apparatus 1 that executes the program, and the data processing apparatus 1 has a hierarchical layout in which layout processing is performed by dividing the data into a plurality of hierarchical blocks. This is a timing analysis program for performing the timing analysis.
[0038]
The timing analysis program 2_1 performs flat development on the data processing device 1 for developing at least one hierarchical block of a plurality of hierarchical blocks into a lowermost circuit and removing at least one hierarchical block. For other hierarchical blocks, create a boundary model consisting of a netlist of clock lines extending from the input port of the hierarchical block to the first flip-flop, from the final flip-flop to the output port of the hierarchical block, and within the hierarchical block. To do. Furthermore, the timing analysis performed in a mode in which these flatly developed hierarchical blocks and boundary modeled hierarchical blocks are mixed is executed for a plurality of modes in which all of the plurality of hierarchical blocks are flatly developed as a whole.
[0039]
The timing analysis program 2_1 also causes the data processing apparatus 1 to perform flat development on all of the plurality of hierarchical blocks to obtain delay information of the entire circuit, and deletes delay information unnecessary for the boundary model from the delay information. Thus, delay information used in the timing analysis is generated.
[0040]
Further, the timing analysis program 2_1 causes the data processing apparatus 1 to delete a timing constraint portion unnecessary for the boundary model from the timing constraint of the entire circuit, and generate a timing constraint used in the timing analysis.
[0041]
Further, the timing analysis program 2_1 causes the data processing apparatus 1 to sequentially execute the timing analysis for a plurality of modes. The following describes how the timing analysis method according to an embodiment of the present invention is realized by executing the timing analysis program 2_1.
[0042]
FIG. 4 is a diagram showing a flowchart of a processing routine of the timing analysis program loaded in the data processing apparatus shown in FIG.
[0043]
The processing routine of the timing analysis program shown in FIG. 4 is executed to realize the timing analysis method of one embodiment of the present invention.
[0044]
First, in step S11 shown in FIG. 4, RC information of each hierarchical block (information considering the electric resistance component and electric capacity component in the actual wiring) is extracted, and the process proceeds to step S12. In step S12, the top-level RC information for the portion excluding all hierarchical blocks from the entire chip is extracted, and the process proceeds to step S13. In step S13, the delay of the entire chip (semiconductor chip circuit) is calculated and stored in the disk 1_20 (see FIG. 2).
[0045]
Further, in step S14, for each hierarchical block, a boundary model including a netlist of clock lines extending from the hierarchical block input port to the first flip-flop, from the final flip-flop to the hierarchical block output port, and within the hierarchical block. Generate and save. At the same time, the information of the circuit portion deleted when the boundary model is generated is also saved. Next, in step S15, the delay information of a specific plurality of blocks is removed from the delay information of the entire chip. Specifically, the hierarchical block to be flat-developed and the hierarchical block to be boundary modeled are arbitrarily specified by the designer, or automatically set from the circuit scale, and the specified or set information and the boundary model saved in step S14 are generated. Based on the information of the circuit part deleted at the time, the delay information of the unnecessary part extracted in the boundary model hierarchical block is deleted and stored from the full-chip delay information stored in step S13.
[0046]
Next, in step S16, the timing constraints of a specific plurality of blocks are removed from the timing constraints of the entire chip. Specifically, based on the information set in step S15 and the information on the deleted circuit portion stored in step S14, the timing constraint information related to the unnecessary portion of the hierarchical block to be boundary modeled is deleted from the full chip timing constraint and stored. To do.
[0047]
Next, in step S17, based on the information set in step S15, the flat list is developed for hierarchical blocks that are not to be a boundary model, the net list of boundary models that is saved in step S14 is the hierarchical block that is to be a boundary model, The top lepel netlists excluding the hierarchical block portions are merged to generate a netlist of the entire chip in which only the hierarchical blocks of the boundary model are omitted.
[0048]
Next, in step S18, timing analysis is performed in a state where the specific plurality of blocks are omitted. Specifically, the timing analysis is performed using the net list obtained in step S17, the delay information generated in step S15, and the timing constraint generated in step S16.
[0049]
Further, in step S19, it is determined whether or not the total hierarchical blocks have been flatly developed and the timing analysis has been performed in total. If it is determined that all the hierarchical blocks are flatly developed and the timing analysis is not performed, the process returns to step S15, and the steps are repeated from step S15 to step S19. To be analyzed. If it is determined that all the hierarchical blocks have been flat developed and the timing analysis has been performed, this processing routine is terminated.
[0050]
FIG. 5 is a diagram for explaining in detail how it is executed in steps S15 to S19 of the processing routine of the timing analysis program shown in FIG.
[0051]
As will be described below, it is equivalent to performing a timing analysis with a full chip as a total by sequentially rotating the hierarchical blocks that are flatly developed and performing the timing analysis each time.
[0052]
FIG. 5 shows a semiconductor chip circuit 10 that is divided into four hierarchical blocks 11, 12, 13, and 14. Here, the timing analysis of the entire semiconductor chip circuit 10 is performed by performing the timing analysis four times.
[0053]
First, the first timing analysis is performed. In the first timing analysis, the flat expansion is performed on the hierarchical block 11 of the four hierarchical blocks 11, 12, 13, and 14, and the hierarchical block 11 is expanded to the lowest layer circuit, and the hierarchical block 11 is excluded. The hierarchical blocks 12, 13, and 14 from the input port of the hierarchical blocks 12, 13, and 14 to the first flip-flop, from the final flip-flop to the output port of the hierarchical blocks 12, 13, and 14, and the hierarchical blocks A boundary model consisting of a netlist of clock lines extending in 12, 13, and 14 is used. Further, the timing analysis is performed in a manner in which the flatly developed hierarchical block 11 and the boundary model hierarchical blocks 12, 13, and 14 are mixed.
[0054]
Next, a second timing analysis is performed. In the second timing analysis, for the hierarchical block 11, a boundary model is used in place of the flatly expanded netlist, the hierarchical block 12 is flatly expanded, and the flatly expanded hierarchical block 12 and the hierarchically modeled hierarchical block Timing analysis is performed in a form in which 11, 13, and 14 are mixed.
[0055]
Further, the third timing analysis is performed. In the third timing analysis, the hierarchical block 12 is replaced with a boundary model that replaces the flatly developed netlist, the hierarchical block 13 is flatly expanded, and the flatly expanded hierarchical block 13 and the boundary model of the hierarchical block 11 are converted. , 12 and 14 are mixed in a timing analysis.
[0056]
Finally, the fourth timing analysis is performed. Here, the hierarchical block 13 is replaced with a boundary model that replaces the flatly expanded netlist, and the hierarchical block 14 is flatly expanded, and the flatly expanded hierarchical block 14 and the boundary models of the hierarchical blocks 11, 12, and 13 are displayed. The timing analysis is performed in a mixed manner. In this way, the timing analysis is sequentially performed on the four modes in which all the four hierarchical blocks 11, 12, 13, and 14 are flat-developed as a whole.
[0057]
The timing analysis method of the present embodiment can perform timing analysis within a realistic time with a delay accuracy equivalent to that of a full-chip flat development for a large-scale circuit. In addition, since the timing analysis can be performed in parallel, the total analysis time can be shortened. Note that this embodiment is applicable not only when hierarchical layout is performed, but also when one chip can be flatly developed and laid out as the performance of the tool increases. That is, by making the block to be omitted not an hierarchical block but an arbitrary logical block (= module), the target of timing analysis can be suppressed.
[0058]
【The invention's effect】
As described above, according to the timing analysis method and the timing analysis program of the present invention, it is possible to perform timing analysis in a short time while maintaining high estimation accuracy of delay information of actual wiring.
[Brief description of the drawings]
FIG. 1 is a perspective view of a data processing apparatus loaded with an embodiment of a timing analysis program of the present invention.
FIG. 2 is a hardware configuration diagram of the data processing apparatus having the appearance shown in FIG. 1;
FIG. 3 is a schematic diagram of a CD-ROM in which an embodiment of the timing analysis program of the present invention is incorporated.
4 is a view showing a flowchart of a processing routine of a timing analysis program loaded in the data processing apparatus shown in FIG. 1. FIG.
FIG. 5 is a diagram for explaining in detail how it is executed in steps S15 to S19 of the processing routine of the timing analysis program shown in FIG. 4;
FIG. 6 is a diagram showing how a hierarchical block is modeled.
FIG. 7 is a diagram illustrating a state in which timing analysis is performed at the top level using a boundary model.
FIG. 8 is a diagram for explaining timing budget processing;
FIG. 9 is a diagram showing a certain hierarchical block.
[Explanation of symbols]
1 Data processing device
1_1 Main body
1_1a Flexible disk loading slot
1_1b CD-ROM loading slot
1_2 Display (CRT display)
1_2a Display screen
1_3 keyboard
1_4 mouse
1_11 CPU
1_12 RAM
1_13 Hard disk controller
1_14 Flexible disk drive
1_15 CD-ROM drive
1_16 Mouse controller
1_17 Keyboard controller
1_18 Display controller
1_19 Communication board
1_20 hard disk
2 CD-ROM
2_1 Timing analysis program
3 Flexible disk
4 communication lines
5 buses
10 Semiconductor chip circuit
11, 12, 13, 14 Hierarchical block

Claims (4)

In a timing analysis program that is executed in a data processing apparatus that executes a program and causes the data processing apparatus to perform timing analysis of a circuit in which a hierarchical layout is performed in which a layout process is performed by dividing the data into a plurality of hierarchical blocks.
In the data processing device, flat expansion is performed on the at least one hierarchical block of the plurality of hierarchical blocks, and the hierarchical block is expanded into a lowermost circuit, and other hierarchical blocks excluding the at least one hierarchical block Create a boundary model consisting of a netlist of clock lines extending from the input port of the hierarchical block to the flip-flop of the first stage, from the flip-flop of the final stage to the output port of the hierarchical block, and into the hierarchical block. timing a timing analysis performed in a manner that the expanded hierarchy block boundary modeled hierarchical blocks are mixed, the plurality of hierarchical blocks all as a whole, characterized in Rukoto is performed for a plurality of aspects to be flat expanded Analysis program. Claims wherein the data processing device, wherein all of the plurality of hierarchical blocks is determined delay information of the entire circuit by performing flat expansion, characterized in that makes deleting unnecessary delay information to said boundary model from the delay information 1. The timing analysis program according to 1 . Timing analysis program according to claim 1 or 2, characterized in Rukoto to delete unnecessary timing constraint information on the boundary model from the overall circuit timing constraints. Wherein the data processing device, timing analysis program according to claim 1, wherein the Rukoto are sequentially performed for the plurality of aspects of the timing analysis.

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