JP3055106B2 - Cell placement method and cell placement device for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The cell arrangement of a semiconductor device, more specifically, the cell arrangement of an LSI having a large-scale macrocell, the cell arrangement which can be connected in the shortest distance by considering a wiring path in a wiring process In order to improve the wiring ratio, a terminal extension area for extending the terminals of the small-scale macrocell around the large-scale macrocell is set, and the leading edge of the terminal extension area is extended to the terminal extension area. Set as the installation position,
After extending the terminal of the small-sized macrocell included in the terminal extension area to the extension position, the arrangement position of the small-scale macrocell having a connection relation with the small-scale macrocell is determined based on the terminal position after extension. I did it.

The present invention relates to a cell arrangement of a semiconductor device, and more particularly, to an LSI cell arrangement having a large-scale macro cell.

With the recent increase in scale and integration of LSIs, there has been an increasing demand for improved placement and wiring processing performance. For this reason, RAM (random access memory), ROM (read only memory), PLA
It is necessary to realize a cell arrangement that does not lower the wiring ratio even for an LSI chip including a large-scale macrocell such as a (programmable logic array).

[Prior Art] Conventionally, in a cell arrangement process of a semiconductor device, when arranging small-scale macrocells having a connection relationship, RAM, RO,
Regardless of the presence or absence of large-scale macrocells such as M, PLA, etc., other small-scale macrocells are arranged only based on the positional relationship with the small-scale macrocells whose arrangement has been determined. I didn't consider it at all.

That is, for example, in the LSI chip 21 shown in FIG. 5, when an attempt is made to arrange a logic cell having a connection relationship with the input / output buffer cell 26a formed around the memory 25 in the logic cell array 22, the buffer cell 26a And the logic cell 23b which is located at substantially the same position in the vertical direction. Therefore, when wiring the input / output buffer cell 26a and the logic cell 23b, the wiring route passes from the input / output buffer cell 26a to the two memories 24 and 25, and then passes through the bent portion 3 indicated by a dashed line.
It had three.

[Problems to be Solved by the Invention] However, the wiring from the wiring lead-out portion between the two memories 24 and 25 to the logic cell 23b becomes a bent portion 33, and the wiring length becomes longer, leading to a reduction in the wiring ratio. Had become.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a cell arrangement that can be connected with the shortest distance by considering a wiring path in a wiring process and improve a wiring rate.

[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention.

The first storage unit 1 stores terminal extension area data for extending a terminal of a small-scale macrocell around a large-scale macrocell and extension position data of a leading edge of the terminal extension area. The storage unit 2 stores terminal coordinate data of each small-scale macrocell.

The judging unit 3 includes the small-sized macro cell in the terminal extended area based on the terminal extended area data read from the first storage unit 1 and the terminal coordinate data of the small macro cell read from the second storage unit 2. Is determined.

When the determination unit 3 determines that the small-scale macrocell is included in the terminal extension area, the extension terminal position determination unit 4
The terminal of the small-scale macro cell is extended to the extended position based on the extended position data of the storage unit 1 of the above.

The cell arrangement position determining unit 5 is based on the terminal extension positions of the small-sized macro cells extended by the extended terminal position determining unit 4 and the terminal coordinate data of each small-sized macro cell stored in the second storage unit 2. Then, the arrangement position of the small-scale macrocell having a connection relationship with the small-scale macrocell having the extended terminals is determined.

[Operation] Therefore, the terminals of the small-scale macrocells around the large-scale macrocell are extended to the extended position where the large-scale macrocell does not hinder, and based on the extended position, the small-sized macrocell has a connection relation with the small-scale macrocell. Since the arrangement position of the scale macro cell is determined, the cell arrangement can be performed with the shortest distance in consideration of the wiring path in the wiring processing, and the wiring rate can be improved.

[Embodiment] An embodiment of a cell placement apparatus embodying the present invention will be described below with reference to FIGS.

Fig. 4 shows a gate array LSI with a large-scale macrocell.
A chip 21 is shown. In the center of the LSI chip 21, a logic cell array 22 having a large number of logic cells 23 as small-scale macro cells is formed, and memories 24 and 25 as large-scale macro cells are formed. A large number of input / output buffer cells 26 as small-scale macro cells are formed on the outer peripheral portion of the LSI chip 21, and pads 27 are provided corresponding to the respective input / output buffer cells 26.

FIG. 2 shows a cell arrangement device 10 for arranging cells in the LSI chip 21 configured as described above. The cell placement device 10 includes a library file 11 as a first storage unit, a design data file 12 as a second storage unit, first and second input units 13 and 14, a determination unit 15, and an extended terminal position determination unit. 16, an extended terminal data file 17, a cell arrangement position determining unit 18, and a layout data file 19.

The library file 11 has a memory as shown in FIG.
The data of the terminal extension area 31 for extending the terminal of each input / output buffer cell 26 around 24 and 25 is stored, and the extension positions 31a, 31b, and 31c of the leading edge of the terminal extension area 31 are stored. Data is stored. In the design data file 12, terminal coordinate data of each input / output buffer cell 26 is stored.

The determination unit 15 determines the data of the terminal extension area 31 input from the library file 11 via the first input unit 13 and the output buffer cells input from the design data file 12 via the second input unit 14. Based on the 26 terminal coordinate data,
It is determined whether or not each input / output buffer cell 26 is included in the terminal extension area. Therefore, it is determined that the input / output buffer cell 26a is included in the terminal extension region 31 in FIG.

When the determination unit 15 determines that each input / output buffer cell 26 is included in the terminal extension area, the terminal extension position determination unit 16 determines the The terminal of the input / output buffer cell 26 is extended to any extension position, the extension path is determined, and the result is sequentially stored in the extension terminal data file 17. Accordingly, in FIG. 5, the terminal of the input / output buffer cell 26a extends to the extension terminal 26a1 at the extension position 31b, and the extension path 32 is determined.

The cell arrangement position determining unit 18 determines whether or not a terminal is to be extended based on the extended terminal data stored in the extended terminal data file 17 and the terminal coordinate data of each input / output buffer cell 26 stored in the design data file 12. The layout positions of the logic cells 23 having a connection relationship with the input / output buffer cells 26 are determined, and the results are sequentially stored in the layout data file 19. Therefore, in FIG. 5, a logic cell 23a which is substantially at the same position in the vertical direction as the extension terminal 26a1 is arranged for the input / output buffer cell 26a.

Then, in the wiring step, the extension terminal 26a1 and the logic cell
23a is connected by the shortest distance wiring portion 34 as shown by the solid line.

As described above, in this embodiment, the terminal extension area for extending the terminal of the input / output buffer cell 26 around the memories 24 and 25 is provided.
31 and the terminals of the input / output buffer cells 26 around the memories 24 and 25 are extended to the extension positions 31a to 31c of the terminal extension area 31, and based on the extension positions, By determining the arrangement position of the logic cell 23 having a connection relationship with the cell 26, the cell arrangement can be performed with the shortest distance in consideration of the wiring route of the wraparound wiring, thereby improving the wiring ratio. can do.

In this embodiment, a library file 11 as a first storage unit and a design data file 12 as a second storage unit
However, the first and second storage units may be configured as one file to store terminal extension area data, extension position data, and coordinate data of each small-scale macrocell.

[Effects of the Invention] As described in detail above, according to the present invention, by considering the wiring route in the wiring processing, a cell arrangement that can be connected with the shortest distance can be performed, and the wiring ratio can be improved. In such a semiconductor device, it is possible to realize an optimal cell arrangement in consideration of the wraparound wiring.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a block diagram showing a cell arrangement apparatus of one embodiment, FIG. 3 is a flowchart showing an arrangement determination process in one embodiment, and FIG. FIG. 5 is a process diagram showing a cell arrangement process. In the figure, 1 is a first storage unit, 2 is a second storage unit, 3 is a determination unit, 4 is an extended terminal position determination unit, and 5 is a cell arrangement position determination unit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-58-11657 (JP, A) JP-A-57-117254 (JP, A) JP-A-57-111044 (JP, A) JP-A-2- 30164 (JP, A) JP-A-2-224371 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/82 H01L 21/822

Claims (2)

(57) [Claims] In a semiconductor device having various large-scale macro cells and various small-scale macro cells in which a predetermined function is defined, when determining an arrangement position of the small-scale macro cells having a connection relationship, the large-scale macro cells are determined in advance. A terminal extension area for extending a terminal of the small-scale macro cell around the terminal extension area is set, and a leading edge of the terminal extension area is set as an extension position of the terminal, and the small-scale macro cell included in the terminal extension area is set. The semiconductor device according to claim 1, wherein after the terminal is extended to the extension position, the arrangement position of the small macro cell having a connection relationship with the small macro cell is determined based on the terminal position after extension. Cell placement method of the device. 2. A semiconductor device comprising various large-scale macrocells and small-scale macrocells each having a predetermined function defined therein, wherein the arrangement position of the small-scale macrocells having a connection relation is determined. In the placement device, a first storage unit (1) storing terminal extension area data for extending a terminal of a small-scale macrocell around a large-scale macrocell and extension position data of a leading edge of the terminal extension area. ), A second storage section (2) storing terminal coordinate data of each small-scale macrocell, and terminal extension area data read from the first storage section (1) and the second storage section (2). A judging unit (3) for judging whether or not the terminal extension area includes the small-scale macrocell based on the read-out terminal coordinate data of the small-scale macrocell; When it is determined that the small macro cell is included in the child extension area, the extension terminal position determination unit () that extends the terminal of the small-scale macro cell to the extension position based on the extension position data in the first storage unit (1). 4), based on the terminal extension positions of the small-scale macrocells extended by the extension terminal position determination unit (4) and the terminal coordinate data of each small-scale macrocell stored in the second storage unit (2). hand,
A cell arrangement device for a semiconductor device, comprising: a cell arrangement position determining unit (5) for determining an arrangement position of a small macro cell having a connection relationship with a small macro cell having an extended terminal.