JP2001189386A - Method for laying out semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of hard macro hierarchic layout that causes the chip area to increase because of a dead space for ensuring the wiring area between macros and the problem of grooving layout that the period of development is prolonged, because auto placement and routing is performed over the entire chip and the machine processing time increase in CAD. SOLUTION: In hierarchic layout design, wiring is effected in macro, while limiting the wiring track to be used. For example, placement and routing is performed under the limitation that first and second layer wiring tracks 5, 6 be used freely but wiring inhibition tracks 9, 10 are set for one third of fourth and fifth wiring tracks 7, 8. The limited wiring tracks in the macro are released at the time of inter-macro wiring of the entire chip and wiring is effected principally using the limited tracks in macro.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit using a hierarchical layout method.

[0002]

2. Description of the Related Art ASIC (Application Specific Integ
In a custom IC such as a rated circuit, the degree of integration is increasing year by year and the required operating speed is also increasing, and accordingly, the degree of difficulty in designing the IC is also increasing.
Conventionally, a layout design method of a large-scale high-speed LSI has been to arrange and wire macros registered in advance as functional blocks on a chip.
As a specific method, two methods, a hierarchical layout method and a grouping layout method, are well known.

FIG. 5 is a layout diagram of a semiconductor integrated circuit laid out by a conventional hierarchical layout method. First, the function of the semiconductor integrated circuit to be designed is divided into a plurality of macros 2 (seven macros from macro A to macro G in the example shown) for each circuit function, and these are arranged on the chip 1 (this The process is called a floor plan). At this time, an inter-macro wiring channel 11 is provided between macros in advance. Then, the arrangement and wiring and timing adjustment are performed for each macro to convert each macro into a hard macro. Thereafter, the hard macros are arranged on the chip to perform wiring between the macros.

FIG. 6 is a layout diagram of a semiconductor integrated circuit laid out by a grouping layout method. In this method, first, an area for arranging and wiring the macros 2 for each circuit function is defined in the chip 1, and the setting of each macro is performed only in the defined area.
Then, placement and wiring are performed on the entire chip at once, and the timing is adjusted.

[0005]

In the conventional hierarchical layout method, the entire wiring area inside the macro is used in the macro. Therefore, in order to perform wiring of the entire chip, as shown in FIG. Inter-macro wiring channel 1 between macros
1 must be reserved in advance, and a dead space is generated, resulting in an increase in chip size and an increase in cost. Further, since the wiring between macros cannot pass through the inside of another macro, the wiring is routed so as to bypass the macro like the wiring 3 between macros in FIG. 5, so that the wiring length increases, and the wiring delay time between macros increases. It becomes a factor that hinders the high-speed operation of the chip. In addition, in the grouping layout method, since the placement and wiring is performed for the entire chip, there are problems such as an increase in machine resources such as memories due to an increase in data scale, an increase in layout processing time, and a prolonged development period. In addition, it is easy for the wiring inside the macro and the wiring between the macros to be partially concentrated and cannot be routed, and as in the case of the hierarchical layout method, the detour wiring is inevitable, which may cause a problem of deteriorating performance. There is.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to reduce the chip size and prevent local congestion and depopulation of wiring in the chip. The purpose of the present invention is to prevent the occurrence of detour wiring and increase the operation speed of the semiconductor integrated circuit.

[0007]

According to the present invention, in order to achieve the above object, (1) a semiconductor integrated circuit is provided with a plurality of circuit functions for each circuit function according to a plurality of circuit functions to be performed by the semiconductor integrated circuit. (2) determining the shape and size of each macro in accordance with the function and the circuit size of each macro and arranging each macro on a chip; and (3) separating each macro from the chip. A semiconductor integrated circuit comprising: a step of individually arranging and routing in each macro; (4) a step of rearranging each macro on a chip; and (5) a step of performing wiring between macros on the entire chip. In the layout method of (1), after the step (1), prior to the step (2), the usage rate of the wiring track existing in each macro is determined, and the step (2) is performed by the wiring step. Truck utilization Performed at under limited, the first (5)
Is performed with the restriction removed. This provides a layout method for a semiconductor integrated circuit.

Preferably, the usage rate of the wiring track is determined according to the size of the macro, the shape of the macro, the number of input / output terminals of the macro, the arrangement position of the macro, the number of wirings passing through the macro, or a combination thereof. .
Also preferably, the semiconductor integrated circuit has a multilayer wiring layer, and the usage rate of the wiring track is
Determined for each wiring layer. More preferably, the semiconductor integrated circuit has a lower wiring layer and an upper wiring layer, and the upper wiring layer is not provided on the lower wiring layer without limiting the usage rate of wiring tracks. Only the wiring track usage rate is limited.

According to the present invention, for example, in a macro of a relatively small size which is arranged at a corner of a chip and which is expected to have few wirings passing over the macro, the wiring in the macro is used. The track usage rate of the upper layer wiring used is set to a value close to, for example, 95% and 100%. On the other hand, if the macro is a relatively large-scale macro arranged in the center of the chip and it is expected that there are a large number of wirings passing over the macro, the wiring track usage rate of the upper layer used in the macro is set to, for example, Limit to about 50%. In this way, the track usage rate of the upper wiring track is set according to the expected number of wires passing on the macro, the size of the macro, the shape of the macro, and the number of input / output terminals from the macro, and then the Perform unique wiring. After a while
The wiring between the macros is performed after the restriction on the usage rate of the wiring track is released. By performing the hierarchical layout design in this manner, it is possible to avoid the local congestion of the wiring and to necessitate the detour wiring, and also to suppress the occurrence of a region where the wiring is sparse. According to the present invention, it is possible to develop a semiconductor integrated circuit that does not require an inter-macro wiring channel between macros using a small-scale machine resource in a short period of time. Therefore, according to the present invention, a semiconductor integrated circuit having a small chip area and capable of high-speed operation can be developed at low cost.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a processing flow of an embodiment of the present invention. FIG.
An overall view of a chip having a four-layer wiring structure of this embodiment, and FIGS. 3 and 4 are diagrams showing wiring tracks of macro E and macro F, respectively. The logic design of the semiconductor integrated circuit to be subjected to the layout design has already been completed, and the design data has been provided. First, the semiconductor integrated circuit is decomposed into a plurality of macros for each functional block (step S1). In the present embodiment, as shown in FIG. 2, macros A to G are decomposed into seven macros. Next, step S
In step 2, the size, shape, and location of the macro are determined in consideration of the circuit scale of each macro and the connection relationship with other macros, and each macro 2 is placed on the chip 1.

Next, in step S3, each macro
Determine the usage rate of the wiring track. Of this wiring track
The usage rate is based on the macro size, macro shape, and macro input.
Number of output terminals, macro placement position, and passing through macro
It is set for each macro according to the number of wiring lines. In this embodiment
In this case, since the four-layer wiring is used, the first and second layers are used.
Wiring shall be used exclusively for wiring within the macro (use rate
There is no restriction), and only the third and fourth layer wiring
Set rack utilization. For example, for macro E
Is located at the center of the chip, and the wiring 3
₁ ~ 3_Four Passes, and connects between macro E and macro F
Macro wiring 3 _Five Is expected to pass
And secure wiring tracks for these wirings.
50% of the third and fourth layer wiring tracks
Set. That is, as shown in FIG.
1st layer wiring track 5 which is a direction wiring track and vertical
Second-layer wiring track 6 which is a direction wiring track
Although the usage rate is not set (the usage rate is 100%), FIG.
As shown in (b), the horizontal wiring track
The third layer wiring track 7 and the vertical wiring track
For the four-layer wiring track 8, 50% is prohibited from using the third-layer wiring.
Stop track 9 and fourth layer wiring prohibited track 10
You.

[0012] For example, the macro F, located on the periphery of the chip, is expected wiring to pass over this, than macrocell routes 3 _1, 3 etc. _{4-3 6} and macro E Therefore, the usage rate of the third and fourth layer wiring tracks is set to 2/3. That is, as shown in FIG. 4A, the usage rate is not set for the first layer wiring track 5 and the second layer wiring track 6 (the usage rate is 100%), but is shown in FIG. 4B. As described above, with respect to the third-layer wiring track 7 and the fourth-layer wiring track 8, one-third thereof is set to the third-layer wiring prohibited track 9 and the fourth-layer wiring prohibited track 10. Also, for example, the macro B is a horizontal wiring track because relatively few wirings are expected to pass over the macro B, and more horizontal wirings are expected to pass therethrough. The usage rate of the third-layer wiring track is set to 80%, and the usage rate of the fourth-layer wiring track, which is a vertical wiring track, is set to 90%.

After the usage rate of the intra-macro wiring tracks is set for all the macros, each macro is separated from the chip in step S4, and the layout and wiring are performed independently for each macro. This placement and routing is performed, for example, by the standard cell method under the limitation of the wiring track usage rate set in step S3. That is, a plurality of standard cells, which are pre-registered functional blocks, are arranged in a macro, the first and second layer wiring tracks are used without restriction, and the third and fourth layer wiring tracks are used. Wiring within the macro is performed using a wiring track within the permitted range. An analysis of the delay characteristic is performed on the placed and routed macro, and if the delay characteristic satisfies the required performance, the placement and routing step is completed. Redo the placement and routing. If the size and shape of the macro change as a result of the placement and routing within the macro, the process returns to step S2 and starts over.

At step S5, the macro 2 which has been placed and routed is placed on the chip 1 again as shown in FIG. Thereafter, the restriction on the usage rate of the wiring track set for each macro is released, and wiring between the macros is performed. At this time, not only wiring tracks whose use has been prohibited,
Wiring is performed using wiring tracks that have not been used in step S4.

Although the preferred embodiment has been described above,
The present invention is not limited to the above-described embodiment, and can be appropriately modified without departing from the gist of the present invention. For example, in the embodiment, the case of four-layer wiring has been described, but the number of wiring layers is not limited to this. Further, in the embodiment, the use-prohibited tracks are specifically determined as shown in FIG. 3 and FIG. 4, but the layout is performed based on only the ratio of the available wiring tracks without setting the use-prohibited tracks. You may do so. In the embodiment, the macros are arranged and wired by the standard cell method, but the present invention is not limited to this.

[0016]

As described above, according to the present invention, the use rate of the wiring track that can be used when arranging and wiring in a macro is determined by the macro size, the macro shape, the number of input / output terminals from the macro, and the macro. It is set according to the number of wirings between macros passing above, etc., wiring within the macro is performed under the limitation of this usage rate, and wiring between macros is performed by removing the limitation of this usage rate. The following effects can be enjoyed. It is possible to prevent the wiring from being locally congested or depopulated on the chip, and the wiring can be accommodated in the chip in a well-balanced manner. Since it is not necessary to prepare an inter-macro wiring channel for performing inter-macro wiring between macros, it is possible to reduce the chip size, thereby improving the manufacturing yield and reducing the cost. By avoiding the necessity of having to perform detour wiring due to wiring congestion, the chip size is further reduced, so that the wiring length between macros can be reduced. Can be provided. The hardware resources required for the layout design can be reduced to a small scale, and the layout processing time can be reduced. Therefore, it is possible to reduce the design cost and the layout design TAT.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow of a layout according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of a chip according to one embodiment of the present invention.

FIG. 3 is an enlarged view of a macro E in FIG. 2;

FIG. 4 is an enlarged view of a macro F in FIG. 2;

FIG. 5 is a schematic plan view of a chip laid out by a conventional hierarchical layout method.

FIG. 6 is a schematic plan view of a chip laid out by a grouping layout method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 chip 2 macro 3, 3 _{1 to} 3 ₆ wiring between macros 5 first layer wiring track 6 second layer wiring track 7 third layer wiring track 8 fourth layer wiring track 9 third layer wiring prohibited track 10 fourth layer wiring Prohibited track 11 Inter-macro wiring channel

Claims (10)

[Claims] (1) dividing a semiconductor integrated circuit into a plurality of macros for each circuit function according to a plurality of circuit functions to be performed by the semiconductor integrated circuit; and (2) a function performed by each macro and its circuit. (3) a step of determining the shape and size of each macro according to the scale and arranging each macro on a chip; (3) a step of separating each macro from the chip and individually arranging and wiring in each macro; ) A method of laying out each macro on a chip; and (5) a step of performing inter-macro wiring on the entire chip. Prior to the step ()), the usage rate of the wiring track existing in each macro is set, and the step (2) is performed under the limitation of the usage rate of the wiring track. Remove this restriction from the process Layout method of a semiconductor integrated circuit, which comprises carrying out. 2. The semiconductor integrated circuit according to claim 1, wherein the setting of the usage rate of the wiring track is performed by setting a wiring track whose use is permitted and a wiring track whose use is prohibited. Layout method. 3. The layout method for a semiconductor integrated circuit according to claim 1, wherein the usage rate of the wiring track is individually determined for each macro. 4. The utilization rate of the wiring track is determined according to a macro size, a macro shape, the number of macro input / output terminals, a macro arrangement position, the number of wirings passing through the macro, or a combination thereof. 4. The layout method for a semiconductor integrated circuit according to claim 3, wherein 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a plurality of wiring layers, and the usage rate of the wiring tracks is determined for each wiring layer. Layout method of a semiconductor integrated circuit. 6. The semiconductor integrated circuit having a lower wiring layer and an upper wiring layer, wherein the lower wiring layer is not limited to a usage rate of wiring tracks and only the upper wiring layer is provided. 6. A layout method for a semiconductor integrated circuit according to claim 5, wherein a limitation is imposed on the usage rate of the wiring track. 7. The wiring according to claim 6, wherein the lower wiring layer is a first wiring layer and a second wiring layer, and the upper wiring layer is a third wiring layer and a fourth wiring layer. A layout method for a semiconductor integrated circuit. 8. The method according to claim 1, wherein the step (3) is performed so as to satisfy a predetermined operation speed condition.
The layout method of a semiconductor integrated circuit according to any one of the above. 9. When the size or shape of a macro is changed as a result of the step (3), the process returns to the step (2) and each macro is rearranged on a chip. The layout method for a semiconductor integrated circuit according to claim 1. 10. The method according to claim 1, wherein the step (3) is performed by a standard cell method.
The layout method of a semiconductor integrated circuit according to any one of the above.