JP3001416B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for laying out a semiconductor integrated circuit such as a gate array or a cell-based IC, and more particularly to a logic circuit using a cell laid out in advance such as a basic cell such as a composite gate or a flip-flop. The present invention relates to a layout method of a semiconductor integrated circuit when laying out a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, while the circuit scale of a semiconductor integrated circuit has rapidly increased, demands for cost reduction have become severe.
Therefore, there is a strong demand for reducing the chip area of a semiconductor integrated circuit. This means that ASICs (Applications) such as gate arrays and cell-based ICs
Specific Integrated Circuit
It is no exception in (it), and it is required to reduce the chip area, that is, to improve the degree of integration of the chip, while keeping the development period, which is an advantage of the ASIC, short.

As shown in FIG. 8, an ASIC chip has a mega block 200 composed of a memory block 210, a PLL 210, a multiplier 220, and the like, and a user logic 300 that can be freely laid out by a designer. And an I / O block 400 including an input / output buffer. The user logic 300
User logic 310, designed by the designer for special use,
320 made such, these circuits are further, NA N
Basic cells 311 for D , NOR, composite gate, adder, etc.
Consists of

Next, a conventional user logic design flow will be described with reference to FIG.
A desired circuit is designed using the basic cell 311 whose circuit characteristics and layout, such as D, NOR, and composite gate, have been verified, and a netlist is created in step S2 based on the circuit diagram created in step S1. Next, in step S3, a floor plan operation for determining an arrangement area of the user logic 300 on a chip is performed based on the total number of gates and the total number of wirings included in the circuit diagram. In step S4, automatic placement of basic cells in the placement area is performed using a computer, and then, in step S5, automatic wiring processing between the placed basic cells is performed.

Next, layout verification of placement and wiring is performed in step S6, and if there is no problem, the layout of the user logic is completed in step S7. On the other hand, step S
If an error occurs as a result of the layout verification in step 6, the circuit design is redone again, or the floor plan is corrected by manually performing forced placement in step S3.
The flow of FIG. 9 is repeated until no unwiring or short-circuit occurs in the layout verification, and the layout of the user logic is completed.

In FIG. 10, basic cells 1 having a relatively small number of input / output terminals are arranged in a horizontal direction, a cell row 2 composed of the basic cells 1 is arranged in a vertical direction, and The case where is wired is shown. Since the number of wirings connecting the input / output terminals of the basic cell is small, automatic layout can be performed without unwiring or short-circuiting. On the other hand, as shown in FIG. 11, when the basic cells having a large number of input / output terminals are densely arranged, the number of wirings between the basic cells increases, the wiring density partially increases extremely, Many unwired or short-circuited lines such as those indicated by dotted lines between the terminals t1 and t3 and between the terminals t2 and t4 occur.

[0007] As shown in FIG.
When a large number of vertical wirings pass through a region interposed between the vertical sides AA ′ and BB ′ of the terminal 29, a terminal t5
Unwiring occurs as shown by the dotted line between t8 and between the terminals t6 and t7.

In such a case, the number of circuit elements is reduced by correcting a circuit portion in which an unwiring or a wiring short is generated, or a region in which an unwiring or a wiring short is caused is manually arranged and wired. There is a problem that the design period is significantly increased.

[0009]

According to the conventional layout method for a semiconductor integrated circuit shown in FIG. 9, when basic cells having a large number of input / output terminals are densely arranged, the number of wirings between the basic cells increases. There is a problem that non-wiring and wiring short-circuit frequently occur in the wiring processing step of step S5. Similarly, when the wiring passing between cells in the vertical direction is partially concentrated, unwiring and short-circuiting frequently occur. And the operating speed becomes slow.

Further, when unwiring or short-circuiting occurs, the circuit design and the floor plan must be redone, and the design period is greatly lengthened.

[0011] Therefore, the object of the present invention is to provide a method for unwiring or wiring when basic cells having a large number of input / output terminals are densely arranged or when wiring passing between cells in the vertical direction is partially concentrated. An object of the present invention is to provide a semiconductor integrated circuit layout method that avoids short circuit and that is efficient.

[0012]

Therefore, a layout method of a semiconductor integrated circuit according to the present invention comprises the steps of vertically arranging a plurality of cell columns formed by arranging a plurality of basic cells in a horizontal direction; In the step, calculating the input / output terminal density of a basic cell group consisting of a plurality of the basic cells arranged continuously, and when the input / output terminal density of the basic cell group exceeds a specified value, The method includes a step of replacing the basic cells constituting the basic cell group with an enlarged cell having the same function as the basic cells provided with a wiring area outside the cell frame of the basic cells.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a layout method of a semiconductor integrated circuit according to the present invention. The steps from the circuit design of the user logic in step S1 to the arrangement of the basic cells in step S4 are the same as the conventional layout method of the semiconductor integrated circuit.

Next, in step S8, the input / output terminal density u of the basic cell group is calculated based on the following equation.

U = (Nl + Nc + Nr) / (Gl + Gc + Gr) (1) Here, Nl, Nc, and Nr are the inputs of the basic cells arranged at the left, center, and right at arbitrary positions in the cell row, respectively. Similarly, Gl, Gc, and Gr are the lengths of the grid-converted horizontal sides of the basic cells arranged on the left, center, and right sides, respectively.

The basic cell 11 adjacent to the left side of the basic cell 12 shown in FIG. 2 has a grid-converted horizontal side length of 4 and two input / output terminals, and the basic cell 12 has a grid-converted number. The length of the side in the horizontal direction is 5, the number of input / output terminals is 3, and the basic cell 13 adjacent to the right side of the basic cell 12 is:
Since the length of the horizontal side in the grid conversion is 2 and the number of input / output terminals is 1, from the equation (1), the input / output terminal density u is u
= (2 + 3 + 1) / (4 + 5 + 2 ) = 6/11 = 0.5
It becomes 5. Similarly, when attention is paid to the basic cell 13, the input / output terminal density u is considered in consideration of the basic cell 12 and the basic cell 14.
Is u = 7/12 = 0.58, and it can be seen that the input / output terminal density is extremely high in both the basic cell 12 and the basic cell 13.

Next, in step S9, the input / output terminal density u calculated in step S8 is compared with a specified value of the input / output terminal density u. A check is made to see if there is any vertical wiring that traverses the column. If there is no vertical wiring, normal wiring processing as shown in FIG. 10 is performed in step S5.

On the other hand, if there is a vertical wiring that traverses the basic cell row in step S10, the number of wirings that traverse the basic cells is calculated in step S11. FIG. 3 shows an example of the arrangement of the virtual basic cells and the virtual wiring in the vertical direction at this time.
Shown in In FIG. 3, vertical wiring exists between the terminals t9 and t12 and between the terminals t10 and t11. Therefore, as shown in FIG. 4, in step S12, the basic cell 14 to which the terminal t11 belongs and the basic cell 15 to which the terminal t12 belongs
Cells 14 'and 1 that can pass through the vertical wiring
Replace with 5 '. Here, the enlarged cell 14 'and the basic cell 14 and the enlarged cell 15' and the basic cell 15 have the same circuit characteristics, respectively.

In FIG. 4, the shaded area is a passage area for the vertical wiring, and the transistor for performing the circuit operation does not exist in this area. In addition, since the enlarged cell corresponding to the number of vertical passing wires is registered in advance as a cell library, in step S12, the enlarged cell corresponding to the number of vertical passing wires is called from the cell library, and the original basic cell is read. Is performed.

If the input / output terminal density of the basic cell is higher than the specified value at step S9, at step S13,
As in step S10, it is checked whether or not there is a vertical wiring that vertically crosses the cell row. If there is no vertical wiring that traverses the cell row, a basic cell replacement process is performed in step S16. Now, as shown in FIG.
If there is a high possibility that the wiring between the terminals t1 and t3 and between the terminals t2 and t4 will not be formed by the conventional layout method, a basic cell group having a high input / output terminal density u is formed in step S16 as shown in FIG. The basic cells are replaced with enlarged cells 16 to 20 having a wiring area on the side of the wiring channel area.
Here, the hatched portions are the wiring regions belonging to the enlarged cells 16 to 20, and do not include transistors that perform circuit operations.

In FIG. 5, step S1
6 shows an example in which, after the replacement processing of the basic cells is performed, the wiring processing is performed without changing the arrangement relationship between the basic cells and the enlarged cells. As can be seen from FIG. 5, although the non-wiring between the terminals t2 and t4 is eliminated and the wiring is correctly performed, the non-wiring remains between the terminals t1 and t3 as shown by a dotted line. The reason for this is that the input / output terminal density u is high near the terminal t3, and wiring cannot be pulled out from the terminal t3. Therefore, in step S16, the arrangement of the basic cell and the enlarged cell shown in FIG. 5 is regarded as an intermediate process of the present invention, and as shown in FIG. 6, the cell arrangement is continued not only for the cell column 2A but also for the cell column 2B. Perform replacement processing.

As can be seen from FIG. 6, the replacement process is performed on the basic cell including the terminal t3 and the replacement is performed with the enlarged cell 24, so that the wiring can be drawn from the terminal t3. Is eliminated.

On the other hand, if there is a vertical wiring that traverses the cell row in step S13, the number of vertical wirings that traverse the cell row is calculated in step S14. Then, step S
At 15, the replacement process of the basic cell is performed. As shown in FIG. 12, FIG. 7 shows an example in which, when four vertical wirings traverse the cell row, basic cell replacement processing and subsequent wiring processing are performed.

An enlarged cell 27 'in which a wiring area shown by oblique lines is secured on the upper side and the lower side with respect to the basic cell 27 of FIG.
12 is replaced with an enlarged cell 28 'in which a wiring area indicated by a hatched portion is secured on the upper side, the lower side, and the right side of the basic cell 28, and are automatically rearranged in step S5. Can be eliminated.

After executing the basic cell replacement processes (1) to (3) in steps S12, S15, and S16,
In this case, in addition to the wiring processing mode M0 in which the entire user logic is sequentially wired, a wiring processing mode M1 in which a region having a high input / output terminal density of the basic cell group is preferentially wired, and a cell processing mode M1. There is a processing mode M2 in which a region is traversed longitudinally and a region through which the vertical wiring passes is preferentially wired. If the mode M1 and the mode M2 are used, non-wiring or short-circuiting can be reliably avoided.

Next, layout verification is performed in step S6, and the layout of the user logic is completed in step S7. These steps are the same as those in the related art.

[0028]

As described above, the layout method of the semiconductor integrated circuit according to the present invention calculates the input / output terminal density of the basic cell group even if the basic cells having a large number of input / output terminals are concentrated. If the input / output terminal density obtained by this calculation exceeds the specified value, the basic cells constituting the basic cell group having a high input / output terminal density have the same circuit characteristics as the original basic cell in which the wiring area is previously secured. By replacing the cell with the enlarged cell having the above, it is possible to avoid a non-wiring or a wiring short.

Further, even when there are vertical wirings that traverse the cell row, the number of wirings in the vertical direction is calculated, an enlarged cell having a wiring area secured according to the number of passing wirings is called from the cell library, and the original cell library is called. By rearranging the cells in place of the basic cells, the problem that the vertical wiring cannot pass through the cell row can be improved.

Similarly, in the case where the input / output terminal density is high and there is a vertical wiring which traverses the cell row, the expanded cell having a wiring area secured on the upper and lower sides of the basic cell and also on the right or left side is similarly provided. By replacing and rearranging the cells, the wiring in the horizontal direction is congested and no unwiring occurs even when the wiring traverses the cell column.

By applying the expansion cell of the present invention,
The area of the enlarged cell itself may be partially larger because it is larger than the original basic cell. However, the wiring efficiency of the entire chip is improved, so that the chip area can be reduced.

Further, when performing the wiring processing, the priority of the wiring processing should be increased with respect to the area where the basic cells having a high terminal density are concentrated or the area where the passing wiring vertically traversing the cell row exists. Thus, more efficient wiring processing can be performed, so that not only the chip area can be reduced, but also the design period can be shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow of a layout method for a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a method for calculating an input / output terminal density u.

FIG. 3 is an example of the arrangement of basic cells in the case where there is a vertical wiring that traverses a cell row.

FIG. 4 is a layout diagram in which an enlarged cell of the present invention is applied to the arrangement of the basic cells shown in FIG.

5 is a layout diagram showing an intermediate processing stage of the layout processing of the present invention in which the enlarged cells of the present invention are partially applied to the arrangement of the basic cells shown in FIG. 11;

FIG. 6 is a layout diagram in which the enlarged cell of the present invention is applied to the arrangement of the basic cells shown in FIG.

FIG. 7 is a layout diagram in which the enlarged cell of the present invention is applied to the arrangement of the basic cells shown in FIG.

FIG. 8 is an explanatory diagram illustrating a hierarchical structure of a semiconductor integrated circuit.

FIG. 9 is a flowchart showing a processing flow of a conventional layout method for a semiconductor integrated circuit.

FIG. 10 is a first layout diagram showing an arrangement of basic cells and wiring between the basic cells according to a conventional layout method.

FIG. 11 is a second layout diagram showing an arrangement of basic cells and wiring between the basic cells according to a conventional layout method.

FIG. 12 is a third layout diagram showing an arrangement of basic cells and wiring between the basic cells according to a conventional layout method.

[Explanation of symbols]

1,11-15,27-29 Basic cell 2,2A, 2B Cell row 14 ', 15', 16-26,27 ', 28' Enlarged cell 100 Chip 200 Mega block 300,310,320 User logic 311 Basic cell 400 I / O block t1-t12 I / O terminal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-61350 (JP, A) JP-A-5-304209 (JP, A) JP-A-2-285656 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04

Claims (5)

(57) [Claims] 1. A step of vertically arranging a plurality of cell rows formed by arranging a plurality of basic cells in a horizontal direction, comprising: a plurality of the basic cells arranged continuously in the cell row. Calculating the input / output terminal density of the basic cell group, and when the input / output terminal density of the basic cell group exceeds a specified value, the basic cells constituting the basic cell group are divided into cell frames of the basic cell. A layout method for a semiconductor integrated circuit, comprising a step of replacing the base cell with an enlarged cell having the same function as that of the basic cell provided with a wiring region outside the semiconductor device. 2. The step of calculating the input / output terminal density of the basic cell group includes: determining a horizontal grid-converted side length of a first basic cell constituting the cell row; Adding the horizontal grid-converted side lengths of the second and third basic cells adjacent to the left and right sides, respectively, and adding the number of input / output terminals of the first to third basic cells 2. The layout of the semiconductor integrated circuit according to claim 1, further comprising: dividing the added number of horizontal input / output terminals by the added horizontal grid-converted side length. Method. 3. The layout method for a semiconductor integrated circuit according to claim 1, further comprising the step of giving priority to a region where the input / output terminal density of the basic cell group is high. 4. A step of vertically arranging a plurality of cell columns formed by arranging a plurality of basic cells in a horizontal direction, and a plurality of base cells arranged continuously in the cell columns.
Calculate the input / output terminal density of the basic cell group consisting of this cell
Process and the input / output terminal density of the basic cell group exceeds a specified value.
Determining whether or not there is a wiring that vertically traverses the cell column.
And if there is a wiring that vertically traverses the cell column,
Calculating the number of wires vertically traversing the cell row, and the input / output terminal density of the basic cell group exceeds a specified value, and
When there is a wiring vertically traversing the cell column,
The basic cells constituting the basic cell group are referred to as the basic cells.
Of the cell frame of the
A method of laying out a semiconductor integrated circuit, comprising a step of replacing the basic cell with an enlarged cell having the same function as that of the basic cell in which a wiring region is provided outside a side along a wiring to be vertically cut . 5. The layout method of a semiconductor integrated circuit according to claim 4, further comprising a step of traversing the cell column and preferentially arranging a region through which a vertical wiring passes.