JPH06349947A - Mask pattern designing method and device of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a length difference in actual wirings to a prescribed value or below so as to lessen a semiconductor integrated circuit in skew by a method wherein a wiring pattern is so converted by processing as to be replaced with another wiring pattern provided with a via-contact. CONSTITUTION:Logic data are inputted at a step S1, and cells are automatically laid out at a step S2. In succession, nets wherein a length difference in actual wirings is required to be reduced to a prescribed value or below are given a wiring starting point and a wiring terminating point, and the nets are made to converge to a wiring starting point taking advantage of a method which converges nets to a virtual point at a step S11. Next, a single broad wiring pattern, which is possessed of a wiring width and a wiring pattern determined basing on currents which flow through the actual wirings of the net between a wiring starting point and a wiring terminating point and a previously determined space between the wirings, is automatically laid. Then, the broad wiring pattern is converted into the wiring pattern of the net, and the wiring pattern of the net located at a corner is replaced with a wiring pattern provided with a via-contact to form a mask data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern designing method and a designing apparatus for a semiconductor integrated circuit device, and more particularly to a mask pattern designing method using a master slice method or a unit cell method (building block method). Is.

In recent years, semiconductor integrated circuit devices have been required to shorten the development period in accordance with the increase in scale and integration. Therefore, also in the mask pattern design, it is necessary to reduce the development period by reducing the design man-hours and simplifying each design process. Further, in the mask pattern design by the master slice method or the unit cell method, in order to prevent the skew, the wiring length difference of the actual wiring in each predetermined net may need to be set to a specified value or less. In that case,
The wiring width can be set appropriately according to the current flowing in each wiring, the wiring interval can be set appropriately so that the inter-wiring capacitance of the actual wiring in each predetermined net can be set appropriately, and the amount of data required for design can be set. There is a demand for simplifying the design tool (CAD system) by reducing the number.

[0003]

2. Description of the Related Art Normally, in differential wiring (wiring for handling differential complementary signals such as input / output wiring of a differential amplifier), clock distribution and latch, the delay time of the signal is set to a specified value or less and skewed. Need to prevent. For that purpose, the wiring length difference of the actual wiring in each predetermined net must be set to a specified value or less.

The wiring width of each wiring must correspond to the flowing current. Furthermore (especially in the case of differential wiring), if the inter-wiring capacitance of the actual wiring in each predetermined net is large, crosstalk between the wirings will deteriorate and cause malfunctions. Must be above a certain width.

FIG. 46 is a flow chart showing a processing procedure of a conventional mask pattern designing method by the master slice method or the unit cell method. First, in step (hereinafter referred to as S) 1, logical data is input.

This logical data is obtained by logical design. Logic design is to embody a logical configuration so as to meet a desired logical specification. Specifically, the logic specifications are realized by using cells (a group of basic circuits forming a logic circuit; a group of simple gates, flip-flops, registers, etc.) that are designed in advance and stored in a cell library. Is to create a logic circuit diagram for. That is, the logic data is the data of the logic circuit diagram, and is composed of the data of the cells to be used and the net data showing the connection relation of each cell.

Next, in S2, each cell is automatically arranged. Here, in the master slice method, in which the cell placeable area and the wiring area between cells are fixed, all cells are automatically placed after initial placement of specific cells due to electrical constraints. Evaluate. The placement evaluation should be performed together with the wiring that is subsequently performed, but since the problem becomes too complicated, it is common to set an approximate evaluation standard and process it separately from the wiring. As a specific evaluation condition, a virtual wiring route is defined to reduce the total wiring length of each wiring route, or a cut line is assumed in the semiconductor integrated circuit chip diagram and the number of wirings crossing it is reduced. Things are used.

Also, in the unit cell method in which the cell allocable area and the wiring area between cells are variable, the arrangement and the arrangement are evaluated by the same method as the master slice method. However, in the unit cell method, the evaluation conditions used in the master slice method are used to evaluate the layout (deciding a virtual wiring path to reduce the total wiring length of each wiring path, In addition to assuming a cut line and reducing the number of wirings crossing it, it is considered to reduce the wiring area.

Then, in S3, automatic wiring is performed between the cells. Here, in the master slice method, the wirable area and the forbidden area on the semiconductor integrated circuit chip are set based on the result of automatic placement of each cell. Then, a connection point pair having a short wiring length is created, and the wiring order is determined for the connection point pair. Next, automatic wiring is performed by the line search method, the maize method, the channel allocation method, and the heuristic method. At this time, the wiring width is set according to the current flowing in each wiring.

Further, in the unit cell method, a penetration position is determined for wiring extending between cell columns, a wiring constraint graph is created, and wiring is ordered. Then, automatic wiring is performed by the main line method while securing a necessary minimum wiring area, and at this time, the wiring width is set according to the current flowing through each wiring. .

Next, in S4, it is verified whether or not the wiring length difference of the actual wiring in each predetermined net is equal to or less than a specified value, and (in particular, in the case of differential wiring) the actual wiring in each predetermined net is checked. It also verifies whether the wiring interval is more than a certain width. If both are not violated, the process proceeds to S5, and if either one is violated, the process proceeds to S6.

In S5, mask data is created.
That is, a mask pattern figure is obtained from the result of automatic placement of each cell and the result of automatic wiring between each cell. Then, the obtained mask pattern figure is converted into mask data which is data suitable for input to the exposure apparatus. In particular,
After subjecting the mask pattern figure to rectangle decomposition processing or trapezoidal decomposition processing, correction for deflection distortion and proximity effect is performed.

On the other hand, in S6, the arrangement condition of a predetermined cell is changed. That is, the placement condition of the violating cell is changed corresponding to the content of the violation in S4, and the initial placement of the violating cell is performed with priority over the initial placement of the specific cell in S2.

Then, returning to S2, the respective cells are automatically arranged again, and then in S3, the automatic wiring between the respective cells is carried out again. This routine from S2 to S6 is repeated until no violation is detected in S4. This allows
It is possible to set the wiring length difference of the actual wiring in each predetermined net to a specified value or less, and to set the wiring interval in each predetermined net to a certain width or more.

FIG. 47 is a flow chart showing a processing procedure of another example of the conventional mask pattern designing method shown in FIG. In FIG. 47, the step numbers are the same for the same processes as in FIG.

Here, the difference between FIG. 47 and FIG. 46 is that S
4 only regarding the processing method when a violation is detected. That is, in FIG. 47, if a violation is detected in S4, the process proceeds to S7. Then, in S7, the placement of each cell and the wiring between each cell are manually (manually) corrected. The manual correction work is carried out interactively using a graphic system.

As a result, similarly to S46, the wiring length difference of the actual wiring in each predetermined net can be set to a specified value or less, and the wiring interval in each predetermined net can be set to a certain width or more.

[0018]

However, as shown in FIG.
In the design method shown in (1), since the routine from S2 to S6 is repeated until no violation is detected in S4,
The number of man-hours becomes very large. Further, in the design method shown in FIG. 46, the manual correction work is performed in S7,
This work is extremely complicated and takes a lot of time. That is, with the conventional design method shown in FIG. 46 or FIG. 47, it is difficult to shorten the time required for mask pattern design. As a result, there is a problem that the reduction of the development period of the semiconductor integrated circuit device is hindered.

Further, in the automatic wiring between the cells in S3, since the actual wiring is performed for each net, it is necessary to hold the wiring data for the number of nets. Therefore, there is a problem that the storage device of the design tool has to have a large capacity.

The present invention has been made in order to solve the above problems, and its purpose is to reduce the design man-hours of mask pattern design to simplify each designing process, and then to realize each predetermined net. A mask pattern designing method capable of setting the wiring length difference of the actual wiring to a specified value or less, appropriately setting the wiring interval of the actual wiring in each predetermined net, and reducing the data amount required for the design And to provide a design device.

[0021]

The first design step is to set a point at which wiring is to be started and a point at which wiring is to be ended for each predetermined net whose wiring length difference of the actual wiring is to be equal to or less than a specified value, and to set a virtual point. A method of pulling in a plurality of nets is used to converge each of the nets to a point where wiring is desired to start.

In the second design process, the wiring width and wiring pattern determined from the point where the wiring is to be started to the point where the wiring is to be ended are determined by the current flowing through the actual wiring in each of the nets and the predetermined wiring interval of each wiring. Wiring is automatically performed with the one wide width wiring.

The third design process and the automatic wide wiring are converted into a wiring pattern for each net. Fourth
In the designing process, the wiring pattern for each net in the corner portion of the thick wiring is replaced with a wiring pattern including a predetermined via contact.

[0024]

Therefore, according to the present invention, the wiring pattern conversion processing in the third designing step and the wiring pattern replacement including the via contact in the fourth designing step replace the actual wiring in each predetermined net. The wiring length difference can be set to a specified value or less. As a result, the deviation of the delay time of the signal of the actual wiring in each net can be set to the specified value or less, and thus the skew can be prevented.

Further, since the wiring width of the thick wiring is determined by the wiring spacing of each wiring determined in advance in the second design process, the wiring spacing of the actual wiring in each predetermined net can be set appropriately.

Further, in the second to fourth design steps,
Only the wiring data of one thick wiring needs to be held.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flow chart showing the processing procedure of the mask pattern designing method according to the present embodiment by the master slice method or the unit cell method. Incidentally, FIG.
In FIG. 46, the step numbers are the same for the same processing as the conventional example shown in FIGS.

First, in S1, logical data is input. This logical data is obtained by logical design. Logic design is to embody a logical configuration so as to meet a desired logical specification. Specifically, the logic specifications are realized by using cells (a group of basic circuits forming a logic circuit; a group of simple gates, flip-flops, registers, etc.) that are designed in advance and stored in a cell library. Is to create a logic circuit diagram for. That is, the logic data is the data of the logic circuit diagram, and is composed of the data of the cells to be used and the net data showing the connection relation of each cell.

Next, in S2, each cell is automatically arranged. Here, in the master slice method, in which the cell placeable area and the wiring area between cells are fixed, all cells are automatically placed after initial placement of specific cells due to electrical constraints. Evaluate. The placement evaluation should be performed together with the wiring that is subsequently performed, but since the problem becomes too complicated, it is common to set an approximate evaluation standard and process it separately from the wiring. As a specific evaluation condition, a virtual wiring route is defined to reduce the total wiring length of each wiring route, or a cut line is assumed in the semiconductor integrated circuit chip diagram and the number of wirings crossing it is reduced. Things are used.

Also in the unit cell method in which the cell allocable area and the wiring area between cells are variable, the placement and the placement are evaluated by the same method as the master slice method. However, in the unit cell method, the evaluation conditions used in the master slice method are used to evaluate the layout (deciding a virtual wiring path to reduce the total wiring length of each wiring path, In addition to assuming a cut line and reducing the number of wirings crossing it, it is considered to reduce the wiring area.

Then, in S11, one thick wiring is automatically provided between the cells. The procedure will be described below. S11-1] Setting a point at which wiring is to be started (hereinafter referred to as a wiring start point) and a point at which wiring is to be ended (hereinafter referred to as a wiring end point) for each predetermined net whose wiring length difference of the actual wiring is desired to be equal to or less than a specified value To do. still,
There may be a plurality of wiring start points and plural wiring end points.

S11-2] Using the technique of pulling in a plurality of nets to the virtual point, each predetermined net whose actual wiring length difference should be equal to or less than the specified value is converged to the wiring start point. The method of pulling in a plurality of nets to this virtual point has been conventionally performed by the master slice method. For example, in S3, it is used when setting the prohibited area on the semiconductor integrated circuit chip based on the result of automatic placement of each cell.

S11-3] The wiring from the wiring start point to the wiring end point is automatically performed by one thick wiring. Here, in the master slice method, the wirable area and the forbidden area on the semiconductor integrated circuit chip are set based on the result of automatic placement of each cell. Then, the wide wiring is automatically wired by the line search method, the maize method, the channel allocation method, and the heuristic method.

Further, in the unit cell method, the penetration position is determined for the wiring extending between the cell columns, the wiring constraint graph is prepared, and the wiring is ordered. Then, the thick wiring is automatically wired by the main line method while ensuring the minimum required wiring area.

However, the wiring width and the wiring pattern of the thick wiring are determined by the current flowing in the actual wiring in each net and the predetermined wiring interval of each wiring. For example, in order to improve the crosstalk between the wirings, it is necessary to set the wiring interval to a certain width or more so that the capacitance between the wirings is reduced.

Next, in S12, mask data is created. The procedure will be described below. S12-1] The automatically routed wide wiring is converted into a predetermined wiring pattern for each net in which the wiring length difference of the actual wiring is desired to be a specified value or less.

S12-2] The wiring pattern for each net in the corner portion of the thick wiring is replaced with a wiring pattern including a predetermined via contact. That is, the wiring pattern including the via contact is predetermined and tabulated based on the classification of the type of the corner portion of the thick wiring. Then, the type of the corner portion of the actual thick wiring is determined, and the wiring pattern including the via contact corresponding to the type is searched from the table and replaced.

S12-3] A mask pattern figure is obtained from the result of the automatic arrangement of the cells in S2 and the result of the wiring in which the wiring pattern is replaced in S12-2]. Then, the obtained mask pattern figure is converted into mask data which is data suitable for input to the exposure apparatus. Specifically, the mask pattern figure is subjected to rectangle decomposition processing or trapezoidal decomposition processing, and then correction for deflection distortion and proximity effect is performed.

As a result, the wiring length difference of the actual wiring in each predetermined net can be set to a specified value or less, and the wiring interval in each predetermined net can be set to a certain width or more.
Next, by taking differential wiring as an example, the actual mask pattern design will be described with reference to FIGS.

In this example, 2 which transmits a differential complementary signal is used.
It is assumed that the difference in wiring length between the actual wirings 21 and 22 in one net must be zero, and the wiring width of each actual wiring 21 and 22 is set to 1 grid and the wiring interval is set to 1 grid. . In the wiring layout diagram, only the intersections of the vertical grid and the horizontal grid are represented by ".g".

FIG. 2 is a wiring layout diagram showing the result of automatic wiring of the wide wiring 23 (see S11). Set the wiring start point α and the wiring end point β one by one,
Using the technique of pulling a plurality of nets to the virtual point, the two nets that transmit differential complementary signals are converged to the wiring start point α. Then, the wiring from the wiring start point α to the wiring end point β is automatically wired as one thick wiring 23.

Here, the wiring width and the wiring pattern of the thick wiring 23 are determined by the current flowing through the actual wirings 21 and 22 in each net and the predetermined wiring interval between the wirings 21 and 22. In this example, the wiring width of each of the actual wirings 21 and 22 is set to 1 grid, and the wiring interval is set to 1 grid. Therefore, the wiring width of the thick wiring 23 is 3 grids. In addition, the wiring pattern of the thick wiring 23 is such that one side of the center line segment 24 that divides the thick wiring 23 into two is
Except for each side, both sides should be 4 grids or more.

That is, as shown in FIG. 3, the central line segment 2
If one side of 4 is 2 grids, there will be a portion where the actual wirings 21 and 22 overlap. Further, as shown in FIG. 4, if one side of the center line segment 24 is set to 3 grids, the actual wirings 21 and 22 are adjacent to each other, and the wiring interval cannot be set to 1 grid. In the differential wiring, if the inter-wiring capacitance between the actual wirings 21 and 22 is large, the crosstalk between the wirings 21 and 22 is deteriorated to cause a malfunction. You have to do more than that. Therefore, in this example, the wiring interval is set to one grid.

FIG. 5 is a wiring layout diagram showing the result of converting the wide wiring 23 into a wiring pattern for each of two nets for transmitting differential complementary signals (see S12-1).
In this example, a wiring pattern of two actual wirings (wiring width is 1 grid) with a wiring interval of 1 grid is arranged along the center line segment 24.

FIG. 6 is an explanatory diagram for explaining the type classification of the corner portion of the thick wiring 23. The corner portion of the thick wiring 23 of this example is always one grid around the point where the central line segment 24 in the X direction and the central line segment 24 in the Y direction intersect (that is, the point where the central line segment 24 bends). Each becomes a square (3 grids on a side).

Therefore, as shown in the position determination diagram of FIG. 6A, the point where the center line segment 24 in the X direction (horizontal direction) and the center line segment 24 in the Y direction (vertical direction) intersect is located at position "E". As
The positions "A" to "I" are assigned to the surrounding grid.

Next, with respect to the wiring layout diagram of the corner portion of the thick wiring 23 shown in FIG. 6B, a grid having a single layer wiring is coded as "1", as shown in FIG. 6C.
A grid with two-layer wiring is code "2", one-layer wiring and two
The code is set by setting the grid having both layer wirings as the code “3” and the grid having no wiring at all as the code “0”.

Then, the position where the code "3" is "A"-
The type of the corner portion of the thick wiring 23 is classified by determining whether it is set to "I". In the example of the corner portion of the thick wiring 23 shown in FIG. 6B, the code "3" is set at the position "G".

Similar to FIG. 6B, when the positions "A" to "I" where the code "3" is set are classified, the type of the corner portion of the thick wiring 23 of this example is shown in FIG. Type 1
Are classified into 9 patterns of type 9 in FIG.

That is, the positions where the code "3" is set are: type 1; position "G", type 2; position "A", type 3; position "I", type 4; position "C", type 5; positions "G" and "I", type 6; positions "C" and "I", type 7; positions "A" and "C", type 7; positions "A" and "G", type 7; The positions are "A", "C", "G", and "I".

Next, as shown in FIGS.
For each of Type 1 to Type 8 in FIG. 14,
Delete part of the wiring pattern. That is, the positions for deleting the wiring patterns are type 1; positions "A-B" and "F".
-I ", type 2; positions" GH "and" CF ", type 3; positions" BC "and" DG ", type 4; positions" A-D "and" HI " , Type 5; position "FI",
Type 6; position "BC", type 7; position "A-
D ”, type 8; position“ GH ”, type 9; wiring pattern is not deleted.

Subsequently, as shown in FIGS. 24 to 31, wiring patterns are added to each of the type 1 of FIG. 16 to the type 8 of FIG. That is, the positions where wiring patterns are added are type 1; positions "A-D" and "H-
I ", type 2; positions" DG "and" BC ", type 3; positions" CF "and" GH ", type 4; position" A "
-B "and" FI ", type 5; position" A-D ", type 6; position" GH ", type 7; position" FI ", type 8; position" BC ", Type 9: No wiring pattern is added.

Then, as shown in FIGS. 32 to 39, via contact patterns are generated for each of the type 1 of FIG. 24 to the type 8 of FIG. That is,
The positions for generating the via contact pattern are: type 1; positions "A" and "I"; type 2; positions "C" and "G"; type 3; positions "C" and "G"; type 4; position "A" and "I", type 5; positions "A" and "I", type 6; positions "C" and "G", type 7; positions "I" and "A", type 8; position "C" And “G”. For type 9, as shown in FIG. 40 or FIG. 41, two positions on the diagonal line of type 9 in FIG. 15 (that is, FIG. 40; positions “A” and “I” or FIG. 41; position “C”). , And “G”) to generate a via contact pattern.

As described above, according to FIGS. 7 to 15, the types of the corner portions of the thick wirings 23 in the wiring layout diagram shown in FIG. 5 are classified, as shown in FIG. When the via contact pattern is generated in FIG. 42 according to FIGS. 24 to 39, the wiring layout diagram in FIG. 43 is obtained.

That is, based on the classification of the types of the corner portions of the wide wiring 23 (FIGS. 7 to 15), the wiring patterns of the actual wirings 21 and 22 including via contacts (FIGS. 24 to 25).
39) is made into a table in advance. Then, the actual wiring 2 for each net in the corner portion of the wide wiring 23
The wiring patterns 1 and 22 can be replaced with a wiring pattern including a predetermined via contact (see S12-2).

As a result, in this example in which differential wiring is performed, the wiring length difference between the actual wirings 21 and 22 in the two nets that transmit differential complementary signals is set to zero, and the actual wirings 21 and 22 are reduced. The wiring interval can be one grid.

As described above, in the present embodiment, the wiring length difference of the actual wiring in each predetermined net can be set to the specified value or less. Therefore, it is possible to prevent the skew by setting the deviation of the delay time of the signal to a specified value or less.

Further, in the present embodiment, the wiring interval of the actual wiring in each predetermined net can be set appropriately. Therefore, particularly in the differential wiring, malfunction can be prevented by reducing the inter-wiring capacitance of the actual wiring in each predetermined net to improve crosstalk between the wirings.

Further, in this embodiment, FIG. 46 and FIG.
The actual wiring for each net as in S3 of the conventional example shown in FIG. 7 is not performed, and only one thick wiring is automatically wired between cells in S11. Therefore, in the present embodiment, it is not necessary to hold the wiring data for the number of nets,
Since only the wiring data for one thick wiring needs to be held, the storage capacity of the design tool need not be large.

Then, in this embodiment, FIG. 46 and FIG.
The verification processing as in S4 of the conventional example shown in FIG. 7 is not performed, and the automatic placement and the automatic wiring are not repeated or the correction work is not manually performed. Therefore, in this embodiment, it is possible to reduce the design man-hours for mask pattern design and simplify each design process.

The present invention is not limited to the above embodiments and practical examples, but may be carried out as follows. 1) As described in S11-1], there may be a plurality of wiring start points and plural wiring end points. For example, as shown in FIG. 44, two wiring end points δ and σ may be set for one wiring start point γ. In this case, two sets of real wirings (4
Although the wiring lengths of 1, 43 and 31, 33) are equal, the wiring lengths of the two sets of real wirings (41, 42 and 31, 32) connecting the wiring start point γ to the wiring end point δ are not equal. However, if the wiring length difference between the two sets of real wirings (41, 42 and 31, 32) is not more than the specified value, skew can be prevented. From a different point of view, if it is desired to make the wiring lengths equal, it is not necessary to provide T-shaped intersections in the wiring pattern as shown in FIG.

2) In the above example of the differential wiring, the differential wiring of 2 nets is taken as an example, but if the wiring is such that the deviation of the delay time of the signal is set to the specified value or less to prevent the skew, it is set to 3 nets or more. It may be used for designing any wiring pattern such as clock distribution or latch.

3) In the above example of the differential wiring, the two-layer wiring is taken as an example, but the same can be applied to the multi-layer wiring having three or more layers. 4) In the example of the differential wiring, each process of the mask pattern designing method has been described as being performed by the software of the computer in the design tool, but it may be embodied by a hardware configuration and used as a mask pattern designing device. That is, as shown in FIG. 45, the logical data input processing circuit unit 5
1, automatic placement processing circuit section 52, and automatic wiring processing circuit section 53
In the mask pattern designing device composed of the above and the mask data creation processing circuit section 54, the same processing as in the above embodiment may be performed. Each processing circuit unit 51-5
Since the processing operation of No. 4 corresponds to S1, S2, S11, and S12 of the flowchart shown in FIG. 1, description thereof will be omitted here.

[0064]

As described in detail above, according to the present invention, the design man-hours for mask pattern design are reduced to simplify each design process, and the wiring length difference of the actual wiring in each predetermined net is defined. There are excellent effects that the values can be set to be equal to or less than the values, the wiring interval of the actual wiring in each predetermined net can be appropriately set, and the data amount required for the design can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of a mask pattern designing method according to an embodiment of the present invention.

FIG. 2 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 3 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 4 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 5 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 6 is an explanatory diagram for explaining the type classification of the corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 7 is a wiring layout diagram showing types of corner portions of a wide wiring 23 as an example of differential wiring.

FIG. 8 is a wiring layout diagram showing types of corner portions of a wide wiring 23 as an example of differential wiring.

FIG. 9 is a wiring layout diagram showing types of corner portions of a wide wiring 23 as an example of differential wiring.

FIG. 10 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of the differential wiring.

FIG. 11 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of the differential wiring.

FIG. 12 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of differential wiring.

FIG. 13 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of the differential wiring.

FIG. 14 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of the differential wiring.

FIG. 15 is a wiring layout diagram showing types of corner portions of the wide wiring 23 as an example of the differential wiring.

FIG. 16 is a wiring layout diagram showing a partial deletion of the wiring pattern at the corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 17 is a wiring layout diagram showing a partial deletion of the wiring pattern at the corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 18 is a wiring layout diagram showing a partial deletion of the wiring pattern at the corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 19 is a wiring layout diagram showing partial deletion of a wiring pattern at a corner portion of a wide wiring 23 as an example of differential wiring.

FIG. 20 is a wiring layout diagram showing partial deletion of a wiring pattern at a corner portion of a wide wiring 23 as an example of differential wiring.

FIG. 21 is a wiring layout diagram showing partial deletion of a wiring pattern at a corner portion of a wide wiring 23 as an example of differential wiring.

FIG. 22 is a wiring layout diagram showing a partial deletion of the wiring pattern at the corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 23 is a wiring layout diagram showing partial deletion of a wiring pattern at a corner portion of a wide wiring 23 as an example of differential wiring.

FIG. 24 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 25 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 26 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 27 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 28 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 29 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 30 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 31 is a wiring layout diagram showing addition of a wiring pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 32 is a wiring layout diagram showing via contact patterns at the corners of the wide wiring 23 as an example of the differential wiring.

FIG. 33 is a wiring layout diagram showing a via contact pattern at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 34 is a wiring layout diagram showing a via contact pattern in a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 35 is a wiring layout diagram showing a via contact pattern at a corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 36 is a wiring layout diagram showing a via contact pattern at a corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 37 is a wiring layout diagram showing a via contact pattern at a corner portion of the thick wiring 23 as an example of the differential wiring.

FIG. 38 is a wiring layout diagram showing a pattern of a via contact at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 39 is a wiring layout diagram showing a via contact pattern in a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 40 is a wiring layout diagram showing via contact patterns at the corners of the wide wiring 23 as an example of the differential wiring.

FIG. 41 is a wiring layout diagram showing a pattern of a via contact at a corner portion of the wide wiring 23 as an example of the differential wiring.

FIG. 42 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 43 is a wiring layout diagram for explaining a mask pattern designing method as an example of differential wiring.

FIG. 44 is a wiring layout diagram for explaining a wiring pattern having T-shaped intersections.

FIG. 45 is a block circuit diagram of a mask pattern design device.

FIG. 46 is a flowchart showing a processing procedure of a conventional mask pattern designing method.

FIG. 47 is a flowchart showing a processing procedure of a conventional mask pattern designing method.

[Explanation of symbols]

 51 logic data input processing circuit section 52 automatic placement processing circuit section 53 automatic wiring processing circuit section 54 mask data creation processing circuit section 54

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazunori Kawazoe 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture, Fujitsu Viel SAI Co., Ltd. (72) Inventor Yukumi Nishiwaki 2-1844, Kozoji-cho, Kasugai-shi, Aichi Fujitsu Viel SII Co., Ltd.

Claims (2)

[Claims] 1. A method for drawing a plurality of nets into virtual points by setting a point at which wiring is to be started and a point at which wiring is to be ended for each predetermined net whose actual wiring length difference is to be equal to or less than a specified value , A first design step of converging each net to a point where wiring is to be started, and a current flowing in the actual wiring in each net and a predetermined wiring interval between the point where the wiring is to be started and the point where the wiring is to be ended The second design step of automatically wiring with one thick wiring having the wiring width and wiring pattern determined by and the third design step of converting the automatically wide wiring to the wiring pattern for each net. The fourth step of designing and replacing the wiring pattern for each net in the corner portion of the thick wiring with a wiring pattern including a predetermined via contact A method of designing a mask pattern for a semiconductor integrated circuit device, comprising: a design step. 2. A logical data input processing circuit section (51) for inputting logical data, an automatic layout processing circuit section (52) for arranging each cell based on the logical data, and a wiring length difference between actual wirings are defined. Set the point at which you want to start wiring and the point at which you want to end it for each given net that you want to keep below the value, and use the technique of pulling in multiple nets to virtual points to converge each net to the point where you want to start wiring , From the point where the wiring is desired to be started to the point where it is desired to be terminated automatically with one thick wide wiring having a wiring width and a wiring pattern determined by the current flowing in the actual wiring in each net and the predetermined wiring spacing of each wiring. The automatic wiring processing circuit section (53) for wiring and the automatically routed wide wiring are converted into a wiring pattern for each net, and the thick wiring corner is formed. And a mask data generation processing circuit section (54) for generating mask data by replacing a wiring pattern for each net in the portion with a wiring pattern including a predetermined via contact. Mask pattern design device.