JP2933605B1 - How to create layout data - Google Patents

Abstract

Conventionally, unwiring and detour wiring occur in a wiring congestion part. Insertion of a feedthrough cell increases the amount of data, and an increase in the size of an LSI chip causes a reduction in the degree of integration. SOLUTION: An automatic placement and routing cell is placed (Step 21), schematic wiring is performed (Step 22), and detailed wiring is performed (Step 24). After performing the schematic wiring and the detailed wiring, it is determined whether or not there is a place where the wiring can pass in the automatic placement and routing cell in response to the connection request of the through wiring (steps 23 and 25). And
If the through wiring cannot be realized, the cell size is changed (step 20), and then the automatic placement and wiring LSI chip design (step 13) is again automatically placed (step 21). The cell size is changed by adding a virtual GRID frame to the automatic placement and routing cell of the actual cell size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating layout data, and more particularly, to automatic layout wiring in a semiconductor integrated circuit design, sometimes using layout cells having terminals inside the cells. How to create.

[0002]

2. Description of the Related Art At present, a semiconductor integrated circuit, for example, a large scale integrated circuit (LSI) is known.
In t) and the like, layout design is performed by automatic placement and routing using an electronic computer as an LSI chip design technique. There are various LSI chip design methods, and a specific application IC (ASIC: Application Spec) is used.
In the field of integrated circuits (LIFs), a method of combining layouts of units called cells is used.
We are doing SI design. Therefore, in the ASIC, the net list (circuit connection information) and the layout (graphic information)
Are prepared in cell unit data, and automatic placement and routing using them is performed .

Conventionally, in an LSI chip design, in the layout design by automatic placement and routing, after the automatic placement and routing cells are designed, the automatic placement and routing cells used in the LSI chip design are collected as a library unit. Input to the wiring tool, create layout data and perform automatic placement and routing.

FIG. 6 is a schematic flowchart showing an example of a conventional layout data creating method. In the figure, first, for layout design of an LSI chip, a cell for automatic placement and routing is designed (step 11), a plurality of automatic placement and routing cells for each function are created, and these cells are collectively collected for automatic placement and routing. A cell library is obtained (step 12).

Subsequently, in the automatic placement and routing LSI chip design (step 13), the automatic placement and routing cells required by the circuit are called from the automatic placement and routing cell library and registered as LSI chip data. Thereafter, the automatic placement and routing cells are placed in the automatic placement processing step (step 21), and schematic routing is performed (step 2).
2).

Next, in a determination step (step 23), it is determined whether or not there is a passable part in the automatic placement and routing cell in response to a request for connection of a through wiring. If it is impossible to realize the through wiring, the processing step (step 17) avoids this by increasing the chip size and widening the gap between the automatically arranged and wiring cells to realize the through wiring (step 1).
8) Alternatively, a cell (feed-through cell) dedicated to the passing wiring is generated and inserted between the adjacent automatic placement and wiring cells to avoid this by realizing the through wiring (step 1).
9). Then, the automatic placement (Step 21) of the automatic placement and wiring LSI chip design (Step 13) is performed again.

On the other hand, if it is determined in step 23 that the passable portion in the automatic placement and routing cell is satisfied, detailed wiring is performed (step 24), and then a request for connection of through wiring is again made. It is determined whether or not there is a route-passable part in the automatic placement and routing cell (step 2).
5). If it is determined that there are not enough wiring-passable parts and it is impossible to realize through wiring, in the processing step (step 17), the chip size is increased and the gap between the automatically arranged wiring cells is increased. Avoidance by realizing through wiring (step 18) or avoiding by generating and inserting a cell (feedthrough cell) dedicated to passing wiring between adjacent automatic arrangement wiring cells (realizing through wiring) (step 18). Step 19). Then, the automatic placement (Step 21) of the automatic placement and wiring LSI chip design (Step 13) is performed again.

On the other hand, if it is determined in step 25 that the place where the wiring can be passed in the automatic placement and routing cell is satisfied, automatic placement and routing verification is performed (step 26).
If the error generated in the automatic placement and routing verification is irreparable, and in the determination step (step 27), there is a shortage of possible wiring locations in the automatic placement and routing cell in response to the through wiring connection request. If it is determined that the through wiring cannot be realized, it is avoided in the processing step (step 17) by realizing the through wiring by increasing the chip size and widening the gap between the automatically arranged and wiring cells. (Step 18) or avoidance by generating and inserting a cell (feedthrough cell) dedicated to the passing wiring between adjacent automatic placement and wiring cells to realize the through wiring (Step 19). And again,
Automatic placement and wiring (Step 21) of LSI chip design (Step 13) is performed.

If it is determined that through wiring can be realized in all of the determination steps in steps 23, 25 and 27, LSI chip data is created (step 14), and layout verification of the LSI chip data is performed. (Step 15), and the LSI chip design layout is completed (Step 16).

On the other hand, the above steps 23, 25 and 27
If it is determined in any of the determination steps that the placement of the through wiring is impossible, the processing step (step 1)
7) In order to avoid this by realizing through wiring by increasing the chip size and widening the gap between the automatic placement and routing cells (step 18), or a cell dedicated to passing wiring between adjacent automatic placement and routing cells (step 18). Feed-through cell)
Is generated and inserted to realize and avoid through wiring (step 19), thereby realizing through wiring and leading to convergence. However, there are cases where convergence does not occur due to input data, the performance of the automatic placement and routing tool, and the like, and the automatic placement and routing tool loops (re-executes automatic routing) many times, which not only increases the execution time but also does not converge. .

Here, the automatic placement and routing will be briefly described with reference to FIG. The automatic placement and routing cell 41 shown in FIG.
42, 43, 44, 45, 46, 47, 48, 49, 5
Reference numerals 1, 52, and 53 denote GRID frames (generally referred to as SITEs) that are divided in units for forming an automatic placement and routing cell called a grid (hereinafter referred to as GRID) existing in the automatic placement and routing cell. The number determines the size of each automatic placement and routing cell.

The automatic placement and routing cell is an automatic placement and routing cell 4
A GRID frame such as 1, 43, 44, 45, 48, 49, 51, 52, in which all terminals are present or a large number of terminals are present for each GRID frame in the automatic placement and routing cell. And a cell having a high terminal density (hereinafter, referred to as a high terminal density cell) with respect to
6, 47, 53, each GR in the automatic placement and routing cell
A cell having a low terminal density for a GRID frame having only a small number of terminals relative to the number of ID frames (hereinafter, referred to as a low terminal density cell) is classified.

When wiring is performed on these automatic placement and routing cells, two or more layers of wiring are usually used for wiring, and different layers are allocated in the horizontal direction (horizontal direction) and the vertical direction (vertical direction). . In general, there are places in the automatic placement and routing cells such as the automatic placement and routing cells 42, 46, 47, and 53 shown in FIG. , 40, 50) (such wires are referred to as through wires) are realized by using locations in the cell where the pass-through wiring is possible.

In the automatic placement and routing, there may be a case where a portion where the passing wiring in the cell is possible is insufficient for the connection request of the through wiring. In such a case, the high terminal density cells are adjacent or densely arranged. This requires wiring to be connected to the terminal, so that the number of places through which the through wiring can pass is reduced. In such a case, there will be a shortage of places that can pass through in response to the through wiring connection request.Therefore, there will be no wiring next to the high terminal density cell or a dense area, and the automatic placement and routing tool will not It converges.

In addition, a detour wiring 60 shown in FIG. 7 is generated to make a detour to another passable part and to enable a through wiring, and the wiring length becomes longer even when the wiring is converged, resulting in deterioration of circuit characteristics. I will. Conventionally, in such a case, as described with reference to the flowchart of FIG. 6, in the processing step (step 17), it is necessary to increase the chip size and widen the gap between the automatically arranged and wired cells to realize the through wiring. (Step 18), or by generating and inserting a cell dedicated to passing wiring (feedthrough cell) between adjacent automatic placement and wiring cells to realize through wiring (step 1).
9).

[0016]

By the way, at present, LS
As the integration of I-chips is increasingly strictly demanded,
The cell size mounted on SI is becoming smaller and smaller. Under such circumstances, the layout design of the LSI chip is mainly designed using the automatic placement and routing, and naturally, the improvement of the wiring property for the automatic placement and routing is also required. Also, L
In the design process of the SI chip, a large number of automatic placement and routing cells are required due to the complexity of the circuit and the improvement of the integration degree.
The increase in SI chip data cannot be ignored.

When designing an LSI chip, the degree of integration varies depending on the circuit to be designed, such as the total number of automatically arranged and wired cells used in the LSI chip, the number of automatically arranged and wired cells used for each function, the number of circuit pin pairs, and the like. However, in the above-described conventional layout data creation method, a plurality of automatic placement and routing cells are prepared for each function in order to correspond to any circuit, and the cell size of each automatic placement and routing cell is fixed. Therefore, when a very large number of high terminal density cells are used in a circuit, etc., there may be a shortage of passing points in response to the connection request for through wiring, and unwiring and detour wiring may occur. However, the degree of integration and circuit characteristics are degraded.

Conventionally, in order to realize through wiring,
Insertion of feedthrough cells, which has been generally performed, has a problem that the data amount of LSI chip data after design increases. Furthermore, regarding the realization of through wiring by enlarging the size of the LSI chip, a low terminal density cell in which there are many places through which the through wiring can pass and a high terminal density in which there are no places through which the through wiring can pass, or where only a very few exist. Regardless of the frequency of use of the cell, if there is a portion that does not converge locally, the size of the LSI chip is uniformly increased, so that there is a problem that a useless area increases and the degree of integration decreases.

The present invention has been made in view of the above points.
An object of the present invention is to provide a method of creating layout data for a semiconductor integrated circuit chip design that can reduce the size of an LSI chip and reduce the amount of LSI chip data by reducing unwiring and detour wiring in automatic wiring. I do.

It is another object of the present invention to provide a method of creating layout data that can realize through wiring without significantly increasing the data amount or lowering the degree of integration.

[0021]

In order to achieve the above object, the present invention provides a first step of creating an automatic placement and routing cell and a second step of registering the created automatic placement and routing cell in a library. A step, a third step of automatically arranging the cells for automatic placement and routing called from the library, a fourth step of performing schematic routing on the automatically placed cells for automatic placement and routing, and a fourth step A fifth step of performing detailed wiring based on a result of the schematic wiring according to the above, a sixth step of performing verification after the detailed wiring of the fifth step, and a detail after the general wiring of the fourth step and the fifth step A step of changing the cell size when the connection of the through wiring is impossible after the wiring, and again performing the automatic placement in the third step. That.

According to the present invention, after the general wiring and after the detailed wiring, if the wiring in the direction orthogonal to the longitudinal direction of the cell column (cell row direction), that is, the connection of the through wiring is impossible, the cells with the same function are used. Based on the automatic placement and routing cell whose size has been changed only, the through wiring is placed in the changed cell part, so only the high terminal density cell appears adjacent to the high terminal density cell existing in the wiring congestion area, the apparent cell By changing the size, even if the high terminal density cells are adjacent to each other, through wiring can be connected in addition to the wiring connected to the terminal. Further, in the present invention, there is no need to redesign the automatic placement and routing cells, insert a feedthrough, and possibly enlarge the size of the LSI chip.

In the seventh step, the cell size may be changed by changing the length of one set of parallel sides of the cell for automatic placement and routing. Also, the present invention
It is characterized in that cells for automatic placement and routing corresponding to several cell sizes are generated in advance and registered in a library.

The seventh step of the present invention is as follows:
It is characterized in that some generated cell size information is stored in a table, and the cell size is changed by referring to the table. Further, the present invention is characterized in that the cell size of the automatic placement and routing cell is changed by automatically processing the automatic placement and routing cell itself in the automatic placement and routing tool or by a device other than the automatic placement and routing tool.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a flowchart of an embodiment of a method for creating layout data for designing a semiconductor integrated circuit chip according to the present invention. 6, the same processing steps as those in FIG. 6 are denoted by the same reference numerals. In FIG. 1, first, a cell for automatic placement and routing is designed for the layout design of an LSI chip (step 11), a plurality of automatic placement and routing cells for each function are created, and these are grouped together for automatic placement and routing. A cell library is obtained (step 12).

Subsequently, in the automatic placement and routing LSI chip design (step 13), the automatic placement and routing cells required by the circuit are called from the automatic placement and routing cell library and registered as LSI chip data. Thereafter, the automatic placement and routing cells are placed in the automatic placement processing step (step 21), and schematic routing is performed (step 2).
2).

Next, in response to the request for connection of the through wiring, it is determined whether or not there is a place that can pass through the wiring in the automatic placement and routing cell (step 23). If this is not possible, the cell size is changed (step 20), and the automatic placement and routing LS is performed again.
Automatic placement of I chip design (step 13) (step 2)
Perform 1).

On the other hand, if it is determined in step 23 that the portion of the automatic placement and routing cell that can pass through the wiring is satisfied, detailed wiring is performed (step 24). After performing the detailed wiring, it is again determined whether or not there is a place where the wiring can pass in the automatic placement and routing cell in response to the through wiring connection request (step 25), and the automatic placement and routing is performed in response to the through wiring connection request. If it is determined that there is not enough wiring-passable part in the cell and it is impossible to realize through wiring, the cell size is changed (step 20), and then the automatic placement and wiring LSI chip design is performed again. The automatic arrangement (step 21) of (step 13) is performed.

On the other hand, if it is determined in step 25 that the place where the wiring can pass in the automatic placement and routing cell is satisfied, the automatic placement and routing verification is performed (step 26). If the error occurred in the automatic placement and routing verification is irreparable, and the following determination processing (step 27)
In the case where it is determined that there is a shortage of places that can pass through the wiring in the automatic placement and routing cell in response to the connection request of the through wiring and that it is impossible to realize the through wiring, after changing the cell size, (Step 20) Automatic placement (Step 21) of automatic placement and wiring LSI chip design (Step 13) is performed again.

If it is determined in all of the determination steps of steps 23, 25, and 27 that through wiring can be realized, LSI chip layout data is created (step 14), and the layout of the LSI chip data is determined. Verification is performed (step 15), and the LSI chip design layout is completed (step 16). On the other hand, if it is determined in any of the determination steps of steps 23, 25, and 27 that realization of through wiring is impossible, the cell size of the automatic placement and routing cell is changed (step 2).
0) realizes through wiring.

In this embodiment, a virtual GRI is applied to the automatic placement and routing cell 31 of the actual cell size shown in FIG.
By adding the D frame, the cell size is changed like the automatic placement and routing cell 32, the automatic placement and routing cell 33, the automatic placement and routing cell 34, the automatic placement and routing cell 35, and the automatic placement and routing cell 36, and the inside of the automatic placement and routing cell is changed. Is provided with a portion through which wiring can pass.

The process of changing the cell size in step 20 of FIG. 1 will be described in more detail with reference to FIG. In the cell size change processing unit 70, in addition to the automatic placement and routing cell A of the actual cell size at the stage of designing the cell for automatic placement and routing,
The cell size changed version 7 of the automatic placement and routing cell A in which the cell size has been changed in the automatic placement and routing cell library 12 in advance.
1 is registered, and an automatic placement and routing cell having a cell size to be used is extracted from the registered cells (step 72).

The cell size data is added to the automatic placement and routing cell A as a table (step 73), a cell size table 74 for the automatic placement and routing cell is created, and the cell size is extracted from the table 74 (step 73).
75 ). The steps 73 and 75 and the cell size table 74 constitute a second cell extracting unit 92. Furthermore,
The cell size of the automatic placement and routing cell A is changed by processing such as a program (step 76).
A processing unit 93 to be a cell size change plate 77 is provided in the cell size change processing unit 70.

For example, as shown in FIG. 4, a table 37 in which setting numbers, actual cell sizes, number of terminals in a cell, cell size change values, left side cell size increase, right side cell size increase are associated as data and automatically arranged and wired cells. Give it to A. The table 37 is used by selecting each setting number when changing the size. The setting numbers in this table 37 correspond to FIG.

After the cell size is changed, as described with reference to FIG. 1, at the time of execution of the automatic placement and routing, the automatic placement and routing LSI chip of FIG. 1 is directly designed together with the netlist (step 13). The automatic placement and routing is performed again for all the cells having the same function as the cell size change version 77 of the automatic placement and routing cell A among the used automatic placement and routing cells (steps 94 and 21).

In this automatic placement and routing, the cell name of the size-changed version 77 of the automatic placement and routing cell A is changed (step 78), and the changed cell name or the cell extracted in step 72 is automatically placed and routed in the cell AX. (Step 7
9) Extraction of the instance name in the netlist of the automatic placement and routing cell A existing in the portion where the automatic routing is not routed and the bypass route exists (step 80), and the extracted instance name and the cell in the netlist are extracted. If the instance names of A match (step 81), the netlist 83
The cell name in the middle is set as the cell name after the cell size is changed (step 82), and the cell name changed version 84 of the netlist is set. Then, along with the netlist cell name change version 84 and the automatic placement and routing cell AX, the automatic placement and routing LSI chip design of FIG. 1 (step 13) is performed to partially change the cell size (step 95).

Next, an example in which the layout data creating method according to the flowcharts of FIGS. 1 and 3 is applied will be described. The automatic placement and routing cells 41, 42, 4 shown in FIG.
Automatic placement and routing cell row 4 adjacent to 3, 44, 45, 46
0, automatic placement and routing cells 47, 48, 49, 51, 5
2 and 53 are adjacent to each other, and there is a shortage of one place where a wiring can be passed in response to a request for connection of a through wiring passing therethrough. Occurs. In addition, if there is a further shortage of the connection request for the through wiring passing over the automatic placement and routing cell row 40 and the automatic placement and routing cell row 50, and if the detour routing to another is not possible, the wiring will be unrouted. .

On the other hand, in this embodiment, when step 95 is applied, it is necessary to change the cell size of the automatic placement and routing cell 48 which causes the detour wiring 60 to occur and the unplaced wiring to be the through wiring. Automatic placement and routing cell 4
The automatic placement and routing cells 61 and 62 are obtained by extracting the instance names 5 and 52 and changing the cell names in the netlist for the extracted instance names only. , 63, and in the LSI chip data, the cell size of the automatic placement and routing cell 45 in FIG.
The automatic placement and routing cell whose cell size has been changed by D enlargement is referred to as a cell 61, and the cell size of the automatic placement and routing cells 48 and 52 in FIG. As 63, the arrangement is performed again.

As a result, the number of places on the automatic arrangement / wiring cell row 40 and the automatic arrangement / wiring cell row 50 that can pass through the wiring is increased by two, so that the wiring which has not been wired or bypassed becomes the through wiring, and the wiring shown in FIG. As shown in FIG. 5, the wiring 60 becomes the through wiring 64, and the non-wiring becomes the through wiring 65 as shown in FIG.

When step 95 is applied, unlike step 94, the automatic placement and routing cell 48 that causes the detour wiring 60 is generated, and the cell size needs to be changed to make the unrouted wiring a through wiring. The cell names of the cells of the same function in the netlist that match the automatic placement and routing cells 45 and 52 of FIG.
The cell names are changed to 62 and 63, and the arrangement is performed again to lead to convergence. Therefore, all the automatic placement and routing cells having the same function as the automatic placement and routing cells 45, 48, and 52 in the LSI chip data are replaced with the automatic placement and routing cells 61, 62, and 63 whose cell sizes have been changed.

As described above, according to this embodiment, the high terminal density cells 45, 48 and 5 are adjacent to the high terminal density cells.
Only 2 can change the apparent cell size,
Even when the high terminal density cells are adjacent to each other, the through wiring 64 can be connected in addition to the wiring connected to the terminal, and the unwiring and the bypass wiring 60 can be eliminated.

Conventionally, in order to improve the wiring performance by increasing the chip size, regardless of the density of the terminals with respect to the grid frame, the wiring performance is improved by increasing the chip size, dispersing the arrangement, and increasing the wiring tracks. Detour wiring and the like have been avoided. However, in this case, even low terminal density cells capable of sufficient through wiring are unnecessarily arranged and dispersed, and wasteful areas increase. According to this embodiment, since the cell size can be changed for an arbitrary cell, the cell size is not changed for a low terminal density cell, and the cell size is changed only for a high terminal density cell. This can reduce wasteful area and minimize the increase in chip size.

[0043]

As described above, according to the present invention,
By changing the apparent cell size of only the high terminal density cells when adjacent to the high terminal density cells, even if the high terminal density cells are adjacent to each other, it is possible to connect through wiring other than wiring connected to terminals , Wiring properties can be improved,
Accordingly, unwiring and bypass wiring can be eliminated, so that the number of design steps can be reduced, the degree of integration can be improved, and circuit characteristics can be improved.

Further, according to the present invention, since the cell size can be changed for an arbitrary cell, the cell size is not changed for a low terminal density cell, and only for a high terminal density cell. It is possible to resize,
Useless areas can be reduced, and enlargement of the chip size can be minimized.

According to the present invention, unlike the method of inserting a feed-through cell, the feed-through cell is not required, and only the cell size of the automatic placement and routing cell itself is changed. It can be kept small.

Further, according to the present invention, since only the cell size as input data of the automatic placement and routing tool is changed, a program other than the automatic placement and routing tool can be used without modifying the automatic placement and routing tool. Cell size can be changed automatically.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of the method of the present invention.

FIG. 2 is a diagram showing each example of a size change cell of an automatic placement and routing cell in one embodiment of the method of the present invention.

FIG. 3 is a flowchart illustrating firing of size change of an automatic placement and routing cell of a main part in FIG. 1;

FIG. 4 is a diagram showing an example of a size change table of an automatic placement and routing cell in FIG. 3;

FIG. 5 is a layout diagram of automatic placement and routing according to an embodiment of the present invention.

FIG. 6 is a flowchart of an example of a conventional method.

FIG. 7 is a layout diagram of automatic placement and routing according to a conventional method.

[Explanation of symbols]

12 Cell Library for Automatic Placement and Routing 13 LSI Placement and Routing LSI Chip Design Step 14 LSI Chip Layout Data 20 Cell Size Change Processing Step 31, 32, 33, 34, 35, 36, 41, 42, 4
3, 44, 45, 46, 47, 48, 49, 51, 5,
2, 53, 61, 62, 63 Layout of automatic placement and routing cell 37 Size change table 40, 50 Automatic placement and routing cell row 60 Detour routing 64, 65 Through routing 94, 95 Size change flowchart

Continued on the front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G06F 17/50 H01L 21/82 JICST file (JOIS) Patent file (PATOLIS)

Claims (6)

(57) [Claims] A first step of creating a cell for automatic placement and routing; a second step of registering the created cell for automatic placement and routing in a library; and a step of creating a cell for automatic placement and routing called from the library. A third step of automatically arranging cells, a fourth step of performing global routing on the automatically-placed cells for automatic placement and routing, and a detailed routing based on a global routing result of the fourth step A fifth step of performing verification after detailed wiring by the fifth step.
And if the through wiring cannot be connected after the schematic wiring in the fourth step and the detailed wiring in the fifth step, the cell size is changed, and the automatic placement in the third step is performed again. And a seventh step of redoing the process. 2. The method according to claim 1, wherein, in the seventh step, the cell size is changed by changing a length of a set of parallel sides of the cell for automatic placement and routing. How to create layout data. 3. The method according to claim 2, wherein cells for automatic placement and routing corresponding to some cell sizes are generated in advance and registered in the library. 4. The layout according to claim 1, wherein in the seventh step, information of some generated cell sizes is stored in a table, and the cell size is changed by referring to the table. How to create data. 5. The automatic placement and routing cell itself is automatically processed in an automatic placement and routing tool or by a device other than the automatic placement and routing tool to change the cell size of the automatic placement and routing cell. Item 9. The layout data creation method according to Item 1. 6. The automatic placement and distribution process according to claim 7, wherein
Line cells are added to each grid frame in the automatic placement and routing cell.
Terminal density with all or many terminals
A higher terminal density cell and a higher terminal density than the high terminal density cell.
Low terminal density cell with a small number of terminals in the cell for dynamic placement and routing
2. The method according to claim 1, wherein the apparent cell size of only the high terminal density cells is changed when the cells are classified into .