JPH02121349A - Semiconductor integrated circuit device and its design - Google Patents

Semiconductor integrated circuit device and its design

Info

Publication number
JPH02121349A
JPH02121349A JP27297088A JP27297088A JPH02121349A JP H02121349 A JPH02121349 A JP H02121349A JP 27297088 A JP27297088 A JP 27297088A JP 27297088 A JP27297088 A JP 27297088A JP H02121349 A JPH02121349 A JP H02121349A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
cell
wiring
layer
arrangement
nodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27297088A
Other versions
JP2834156B2 (en )
Inventor
Mitsuo Asai
Toshio Doi
Takehisa Hayashi
Kenichi Ishibashi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

PURPOSE: To make it possible to design a high-speed LSI in a short time by a method wherein a potential is fixed in the upper layer of a wiring layer and moreover, there is at least one layer of a shielding layer to cover nodes in a cell and at the same time, at least one layer of a wiring layer to make an intercell connection is arranged on the upper layer of the shielding layer.
CONSTITUTION: In a three-input AND cell 101 using a precharge circuit, specifications on the layout of the arrangement of a power wiring and a grounding wiring, the external shape and height of the cell, the positions of input/ output terminals and the like are set in specifications identical with those of a standard cell (an inverter cell) 102 of a CMOS static circuit. Therefore, the arrangement of the cell can be conducted using a DA technique identical with that used for the arrangement of the standard cell. Moreover, as the space over dynamic nodes 9 to 11 in the cell is covered with the power wiring VDD and the grounding wiring GND, whose potentials are fixed, an electrostatic capacity between a signal wiring i101 passing through the space over the cell and the nodes is inhibited sufficiently small. Accordingly, there is no limit to a wiring in the space over the cell. Thereby, an intercell connecting wiring can be automatized like that in the standard cell.
COPYRIGHT: (C)1990,JPO&Japio
JP27297088A 1988-10-31 1988-10-31 The semiconductor integrated circuit device Expired - Fee Related JP2834156B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27297088A JP2834156B2 (en) 1988-10-31 1988-10-31 The semiconductor integrated circuit device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27297088A JP2834156B2 (en) 1988-10-31 1988-10-31 The semiconductor integrated circuit device
KR890015696A KR0150778B1 (en) 1988-10-31 1989-10-31 Semiconductor vlsi apparatus and its design method
US07793296 US5223733A (en) 1988-10-31 1991-11-14 Semiconductor integrated circuit apparatus and method for designing the same

Publications (2)

Publication Number Publication Date
JPH02121349A true true JPH02121349A (en) 1990-05-09
JP2834156B2 JP2834156B2 (en) 1998-12-09

Family

ID=17521331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27297088A Expired - Fee Related JP2834156B2 (en) 1988-10-31 1988-10-31 The semiconductor integrated circuit device

Country Status (2)

Country Link
JP (1) JP2834156B2 (en)
KR (1) KR0150778B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513732A (en) * 1990-09-13 1993-01-22 Nec Corp Composite type semiconductor integrated circuit device
US6278148B1 (en) 1997-03-19 2001-08-21 Hitachi, Ltd. Semiconductor device having a shielding conductor
JP2005347591A (en) * 2004-06-04 2005-12-15 Matsushita Electric Ind Co Ltd Standard cell, semiconductor integrated circuit device in standard cell system and layout design method for semiconductor integrated circuit device
US7334210B2 (en) 2003-11-04 2008-02-19 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and method of designing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513732A (en) * 1990-09-13 1993-01-22 Nec Corp Composite type semiconductor integrated circuit device
US6278148B1 (en) 1997-03-19 2001-08-21 Hitachi, Ltd. Semiconductor device having a shielding conductor
US7334210B2 (en) 2003-11-04 2008-02-19 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and method of designing the same
JP2005347591A (en) * 2004-06-04 2005-12-15 Matsushita Electric Ind Co Ltd Standard cell, semiconductor integrated circuit device in standard cell system and layout design method for semiconductor integrated circuit device
US7309908B2 (en) 2004-06-04 2007-12-18 Matsushita Electric Industrial Co., Ltd. Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device

Also Published As

Publication number Publication date Type
JP2834156B2 (en) 1998-12-09 grant
KR0150778B1 (en) 1998-12-01 grant

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees