JP2980316B1 - Hierarchy layout method - Google Patents

Abstract

An object of the present invention is to provide a hierarchical layout method for embedding a pass-through wiring on a macro cell while retaining a result of performing a repeater insertion process in a state where a wiring is expanded and not divided in an upper hierarchy in a hierarchical layout. And SOLUTION: In a hierarchical layout, there is provided a method of embedding a layout result passing on a macro (lower hierarchy) cell in a lower hierarchy while keeping a wiring path and a repeater arrangement position. Further, in the hierarchical layout method of a semiconductor integrated circuit, timing between terminals in an upper hierarchy is
It is characterized by embedding wiring in the lower hierarchy to guarantee. A wiring passing on the lower hierarchical macro is connected by arranging at least one of a repeater, a buffer, and an inverter, and embedding at least one of the repeater, the buffer, and the inverter in the lower hierarchical macro. I do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate array and an A
SIC (Application Specific integrated Circuit:
The present invention relates to a hierarchical layout method for embedding a pass-through wiring on a macro cell of a semiconductor integrated circuit such as an LSI of an application specific IC.

[0002]

2. Description of the Related Art Hierarchical layouts have become indispensable today as the development scale of LSIs increases. When the hierarchical layout method is used, the lower layer portion is treated as one macro when viewed from the upper layer, and the wiring in the upper layer may be laid out by bypassing the macro. In this case, due to the detour of the wiring, the wiring length increases, and the chip area also increases.

As a method of avoiding the macro detour of the wiring, as shown in FIG. 13, a passage area is previously secured in a portion expected to pass on a macro in a layout of a higher hierarchy, and FIG. There is a method in which a terminal is formed at the boundary of the macro cell for passing through the inside of the macro cell and wiring is performed, and the macro cell passes through this terminal.

FIGS. 13 and 1 show these conventional methods.
This will be briefly described with reference to FIG. 13 and 14, the upper layer is denoted by 101 and the lower layer macrocell is denoted by 102. The wiring that passes over the macro cell 102 in the lower hierarchy is connected to the terminals 103 and 104 in the upper hierarchy. First, in the first method, before the layout shown in FIG. 13A, the area 171 where the wiring prohibited area (OBS) indicated by 105 and 106 does not exist on the lower-layer macrocell 102 is set to the OB.
After the layout is created between S105 and OBS 106 and after the layout shown in FIG. 13B, the region 171 is made to pass through the wiring 107 to prevent the macro cell 102 from being bypassed.

In the second method, before the layout shown in FIG. 14A, external terminals 108 and 109 connected to the outside of the cell are provided in the lower hierarchy 102 in order to allow the wiring to pass through the macro cell 102 in the lower hierarchy. Created beforehand, as shown in FIG.
After the layout shown in FIG.
03 and the external terminal 108, and the upper layer terminal 104 and the external terminal 109 are respectively wired. After the layout shown in FIG.
By wiring 08 and 109, macro bypass of the wiring is avoided.

On the other hand, a method of manufacturing a semiconductor integrated circuit using a hierarchical design method based on the standard cell method is disclosed in Japanese Patent Application Laid-Open No. Hei 5-347354. And designing a module combining a basic cell and a macro cell, including a placement and routing step of automatically placing and routing the macro cell in the same manner as the basic cell, thereby providing a cell data of a conventional macro cell. It is said that the number of processes that were stored in the cell library together with the characteristic parameters was reduced, thereby achieving a reduction in man-hours. However, it does not address the problem of wiring between the upper layer and the lower layer, and does not particularly mention the delay time.

[0007] An automatic wiring design method for a master slice type semiconductor integrated circuit is disclosed in Japanese Patent Application Laid-Open No. H08-63493, in which a cell in a mask cell of a semiconductor chip having a plurality of memory cells such as a RAM is automatically determined. It is arranged and automatically wired in a hierarchy higher than the macro cell. A first prohibited area is set in the macro cell area, and automatic wiring is performed between cells in the macro cell so as not to violate the wiring area in the cell and the first prohibited area. However, inside the macro cell, a region other than the first prohibited region is set as a second prohibited region, and automatic wiring is performed in the upper hierarchy so as not to violate the second prohibited region. However, even in this conventional example, there is no description about a delay time or a bypass circuit due to wiring between a lower layer and an upper layer of a macro cell, and the problem of the above conventional example still remains.

[0008]

However, today, with the miniaturization of the process, the delay caused by the increase in the wiring length has become a serious problem. As a method of suppressing this delay, a method of inserting a repeater is used.
The effect of the repeater will be described in detail with reference to FIG. Reference numerals 301 and 302 shown in FIG. 15A indicate terminals having a terminal distance ta. In FIG. 15A, an example without a repeater is shown by a wiring 303, and on the other hand, an example with a repeater 306 shown in FIG. 15B is shown by wirings 304 and 305.
The terminal 30 with and without the repeater 306
As shown in FIG. 15C, a delay time between the terminals 1 and 302 is represented by ta and tb, respectively, and the horizontal axis represents a distance between terminals and the vertical axis represents a time. In FIG. 15C, tb
Is composed of a delay time t1 between the wirings 304, a delay time t2 in the repeater 306, and a delay time t3 between the wirings 305. In the graph, with the terminal 301 as a starting point, ta is denoted by 31, and tb is denoted by 32. Here, there are two types of delay times between the terminals 301 and 302, one is the delay time of the wiring portion, and the other is the delay time inside the repeater 306.

Here, the relationship between the delay time (t) of the wiring portion and the wiring length (l) is represented by t = xl ² where x is a coefficient.

On the other hand, the delay time t2 inside the repeater 306 has a constant value. Therefore, the delay time ta without the repeater 306 is only the wiring delay time as shown by the quadratic curve 31 shown in FIG. 15, and the delay time tb with the repeater 306 is shown by the curve 32, and the wiring delay Is divided, the total delay time becomes small.

In the repeater insertion process, a necessary number of repeaters of a required type are inserted between necessary terminals at necessary positions so that the delay time between the terminals at the start and end points is within the constraint time. Therefore, in the hierarchical layout, when the wiring in which the repeater is inserted is passed to the lower hierarchical macro,
It is necessary to embed in the lower layer macro while keeping the position of the repeater. However, in the conventional macro passing wiring embedding method described above, it is difficult to embed the repeater in a lower hierarchy while maintaining the arrangement position of the repeater on the macro cell.

First, in the method described with reference to FIG. 13, the wiring passing over the macro cell 102 is a wiring of the upper hierarchy, and there is no particular problem in the upper hierarchy, but in the lower hierarchy, the position where the repeater is arranged in the upper hierarchy Must not allow other blocks to be placed. In the case where only the wiring information is passed, the area that passes through the wiring in the upper hierarchy is merely set as the wiring prohibited area (OBS). However, when the repeater is embedded in the lower hierarchy, the placement prohibition is created in the lower hierarchy. The need arises. However, if all the wiring-passable areas are prohibited from being arranged in the lower hierarchy, the wiring property in the lower hierarchy will be deteriorated. Therefore, if only the position where the repeater is placed is prohibited, it is necessary to match the cell columns of the upper layer and the lower layer, and it is necessary to reflect the result of the upper layer layout in the lower layer. Only layout can be done.

In the method described with reference to FIG. 14, since the wiring in the lower hierarchy macro is the wiring of the lower hierarchy, it is not particularly problematic to insert a repeater in the lower hierarchy, but there is a problem in its arrangement position. I do. Problems with this method will be described with reference to FIG. 11 shows an example of repeater insertion in the upper hierarchy, and 12 shows an example of repeater insertion in the conventional method described with reference to FIG. In the state diagram before the repeater insertion and after the repeater insertion in FIG. 16, reference numeral 11 denotes an example in which the repeater is inserted at a position satisfying the delay constraint in the wiring 153 between the start point 151 and the end point 152 in the upper hierarchy 101 having the lower hierarchy 102. FIG. Example of FIG. 16 In the example of FIG. 7, the repeater 155 is inserted, and the wiring 153 is connected to the wirings 153 and 1
It is divided into 54. On the other hand, 12 shown in FIG.
4 shows an example in which a repeater is inserted into the conventional example in which a terminal is provided in the macro cell shown in FIG.
Are divided at the terminals 159 and 160 at the boundary of the lower layer macro cell in the state of
It is divided into 6 to 158 wirings. Next, the upper hierarchy 101 and the lower hierarchy 102 after the repeater insertion according to the conventional method.
In the state shown in FIG. 16, in FIG.
62 is added, and the wiring 157 is divided into 157 and 161. In this method, the repeater insertion processing is
Since the wiring is performed between the wirings 156, 157, and 158, the result is different from the repeater insertion result executed in a state where the wiring is developed without being divided. For this reason, redesign on the wiring is required, which causes a problem in the process.

The present invention solves such a problem, and embeds the pass-through wiring on the macro cell while retaining the result of the repeater insertion process in the hierarchical layout in which the wiring is expanded without being divided in the upper hierarchy. It is an object to provide a method.

[0015]

SUMMARY OF THE INVENTION The present invention provides a method of embedding a layout result passing over a macro (lower hierarchy) in a lower hierarchy while maintaining the layout positions of wiring routes and repeaters in a hierarchical layout. The greatest feature of the present invention is that the repeater insertion process in the upper layer is
This can be performed without dividing the wiring.

Further, the present invention is characterized in that in a hierarchical layout method of a semiconductor integrated circuit, timing between terminals in an upper hierarchy is guaranteed by embedding wiring in a lower hierarchy.

According to the present invention, there is provided a hierarchical layout method for a semiconductor integrated circuit, wherein a wiring passing on a lower hierarchical macro is connected by arranging at least one of a repeater, a buffer and an inverter, and connecting the repeater and the buffer. , One or more of the inverters are embedded in the lower layer macro.

According to the present invention, in a hierarchical layout method for a semiconductor integrated circuit having a plurality of layers, when embedding wiring information in a macro cell of a lower layer, an arrangement path and an arrangement position of at least one of a repeater, a buffer, and an inverter. Is held.

Further, according to the present invention, in a hierarchical layout method of a semiconductor integrated circuit having a plurality of layers, when embedding a wiring in a macro cell of a lower hierarchy, an existing external terminal of the macro cell is moved and redundant wiring is deleted. It is characterized by.

Further, the present invention is characterized in that in a hierarchical layout method for a semiconductor integrated circuit having a plurality of layers, when a repeater is embedded in a macro cell of a lower layer, unnecessary repeaters that are virtually disposed are deleted.

According to the present invention, there is provided a hierarchical layout method for a semiconductor integrated circuit having a plurality of hierarchies, wherein a placement and routing process for executing an initial layout including a lower hierarchy as an upper hierarchy process; Virtual terminal creation processing for creating a virtual terminal with respect to a boundary, wiring division processing for dividing wiring at the position of the virtual terminal, layout change processing for deleting the divided wiring and repeater, and again after the layout change A rearrangement and wiring process for arranging and routing, wherein the lower hierarchy process includes, after the wiring division process in the upper hierarchy, a wire divided and embedded in the lower hierarchy, and a repeater arranged in the lower hierarchy. And a rearrangement and wiring process for rearranging and wiring after the layout change. And butterflies.

In the above-described hierarchical layout method,
The virtual terminal creation processing determines whether or not the wiring of the lower-level macro cell is a target, determines whether or not there are three or more points on the boundary, If the distance is less than or equal to the predetermined distance, it is excluded from the target.
It is determined whether or not it is necessary to connect to the external terminal to move the position of the external terminal. If the passing distance of the wiring passing through the lower hierarchy is shorter than a predetermined distance, the wiring is changed and the wiring is changed. Is within the target, a virtual terminal is created at the intersection of the upper layer and the lower layer.

[0023]

Embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment (Configuration of the Present Embodiment) FIG. 1 is a flowchart of a method of embedding a pass-through wiring on a macro in a hierarchical layout in a plurality of hierarchical design methods of a semiconductor integrated circuit according to the present embodiment.

Referring to FIG. 1, the present embodiment includes a process 21 in an upper hierarchy and a process 22 in a lower hierarchy in a hierarchical layout.

The upper layer process 21 is a process in the upper layer, which is a placement and routing process 201, a virtual terminal creation process 202 for a boundary, and a wiring division process 203 at a virtual terminal position.
And layout change processing 204 for deleting the divided wiring and repeater, and rearrangement wiring processing 205 after the layout change.

The lower hierarchy processing 22 is a processing in the lower hierarchy, in which after the wiring division processing 203 in the upper hierarchy, the wiring to be divided and embedded in the lower hierarchy and the repeater arranged in the lower hierarchy are added. Change processing 20
6 and a rearrangement and wiring process 207 after layout change.

(Operation of the Present Embodiment) The operation of the present embodiment will be described in detail with reference to the flowchart of FIG. Examples of each operation will be described with reference to FIGS. 2 to 8 along the flowchart of FIG. 2 to 8, the upper layer is denoted by 101 and the lower layer is denoted by 102. The terminals at the start and end points by the position wiring on the upper hierarchy 101 are denoted by 103 and 104, the inserted repeater is denoted by 113, and the wiring is denoted by 114 and 115.
Indicated by

First, the placement and routing processing 2 in the upper hierarchy of FIG.
FIG. 2 shows an example of a schematic layout result after the placement and routing of No. 01. FIG. 2 shows a state diagram of a state diagram after the initial layout. As a result of the layout on the upper hierarchy 101, the wirings 114 and 115 pass on the lower hierarchy 102, and the repeater 113 is operated to reduce the delay time of the wiring. Are located.
Next, FIG. 3 shows an example after the virtual terminal creation processing of the virtual terminal creation processing 202 of FIG. Lower layer 102 and wiring 114,
115 and virtual terminals 116 and 117 are created. Next, FIG.
FIG. 4 shows an example after the wiring division processing of the wiring division processing 203 of FIG. FIG. 4 shows the upper hierarchy 101 and the lower hierarchy 10 after wiring division.
2 is a plan view of FIG. Wiring 1 with virtual terminal 116 created
14 is divided into a wiring 114 on the upper hierarchy 101 side and a wiring 118 on the lower hierarchy side. Similarly, the wiring 115 is divided into the wiring 115 and the wiring 119 at the virtual terminal 117.

Next, the layout change processing (deletion) shown in FIG.
204, and the layout change processing (addition) 206 will be described. FIG. 5 shows a layout change process (deletion) 2
It is a layout diagram after 04. As shown in FIG. 5, the upper layer 101 after the layout change processing has the virtual terminals 1 and 117 with respect to the virtual terminals 116 and 117 of the lower layer macrocell 102.
16, the wiring between the wiring 114 and the terminal 103, and the virtual terminal 11
7, the wiring 116 and the wiring of the terminal 104 are shown. FIG.
In the lower hierarchy 102 shown in FIG. 7, a wiring 118 is provided between the virtual terminal 116 and the repeater 113, and a wiring 119 is provided between the repeater 113 and the virtual terminal 117. FIG.
In the upper hierarchy side, the wirings 114 and 115 are changed, and the repeater 113 is deleted. In the lower hierarchy side of FIG.
18, 119 and a repeater 113 are added.

Finally, the rearrangement and wiring process (upper) 2 in FIG.
05, an example of the rearrangement and wiring process (lower) 207 after the rearrangement and wiring is shown in FIG. 7 on the upper layer side and in FIG. 8 on the lower layer side. In this case, since there is a layout change in both the upper and lower layers, the arrangement and wiring are performed again. In particular, in the lower hierarchy shown in FIG. 8, since the wirings 118 and 119 and the repeater 113 are added, there is a possibility that the wirings overlap the existing arrangement and wiring information. Therefore, the placement and routing process is performed again in the lower hierarchy. According to the figure, the positions of the virtual terminals 116 and 117 are the same as the imaginary points, and the wirings 118 and 119 are curved straight lines with corners.

Next, in order to show the operation of the present invention, a part of the process of setting and creating a virtual terminal in the virtual terminal creation process 202 of FIG. 1 will be described in detail with reference to FIGS. 9 and 10. . FIG. 10A shows a state diagram before embedding a virtual terminal or a repeater, and FIG. 10B shows a state diagram after embedding.

FIG. 9 is a flowchart illustrating the virtual terminal creation processing 202 in detail. It is not necessary to create virtual terminals at all boundary points of the lower-layer macrocells from the schematic layout results in the upper layer. The virtual terminal creation processing 202
Check whether to create a virtual terminal.

First, when the wiring embedding processing is excluded from the target by the designation from outside (20 in FIG. 9).
9).

Next, in the arrangement diagram before embedding in FIG. 10A, when passing over the boundary of the macrocell 102 many times as shown by the wiring 136, the distance between the intersections of the boundary is checked. If the distance is within the predetermined distance α, no virtual terminal is created.
This distance α is a distance for excluding a short passage wiring from the embedding process, and can be freely set from outside. This processing is described with reference to the wiring 136 in FIG.
A specific example will be described. The wiring 136 has four intersections with the boundary at four points. Since two of these are shorter than the predetermined distance α, virtual terminals are not created, and virtual terminals are created only at the two intersections 140 and 141 (FIG. 9). 210, 211).

Next, when the wiring is connected to the external terminal of the macro cell, the external terminal may be moved to eliminate the necessity of performing the wiring embedding process. A specific example will be described with reference to the wirings 132 and 133 in FIG. These wirings are connected to the external terminals 127. However, if the positions of the external terminals are moved to the intersections between the wirings 132 and the boundaries, there is no need to embed the wirings in the lower hierarchical macro. At this time, the wiring 133 and the repeater 129 which have become redundant by moving the external terminal are deleted. Whether to move the external terminal is determined based on whether the side of the intersection with the external terminal is the same.

However, when the external terminal passes through the wiring at two or more locations, the external terminal is not moved. FIG.
A specific example will be described with reference to the 0 wirings 134 and 135. The wiring 135 is connected to the external terminal 128.
24 is also connected. In this case, the position of the external terminal does not move, the virtual terminal 137 is created, and
4, 138, and the wiring 135 is an external terminal 128,
It is divided into 135 and 139 (212 and 213 in FIG. 9).

Next, when the distance passing on the lower layer macro is short, no virtual terminal is created. A specific example will be described with reference to the wiring 131 of FIG. Although the wiring 131 passes over the macro cell, the passing distance is short, so that the passing wiring embedding process is not performed. This distance β serves as a criterion for excluding from the process of embedding the short passage wiring, and can be designated from outside. The distance β is measured by measuring the distance between two points on the boundary along the boundary (214 in FIG. 9).

A virtual terminal is created only at a wiring boundary position that satisfies all of these conditions (215 in FIG. 9).

Lastly, if there is an existing external terminal or a created virtual terminal at the position of the created virtual terminal, it is shifted so as not to overlap (216 in FIG. 9).

FIG. 11 shows an example of embedding another passing wiring as an application example. FIG. 11 shows an example in which two or more repeaters are connected in series, an example in which two or more repeaters are connected in parallel, and an example in which two or more repeaters are connected in parallel. 145, the passing wiring can be embedded in any of the examples.

In the above-described embodiment, an example in which the number of lower layers is one is shown, but the number of lower layers is not limited. Further, in the above embodiment, an example in which the number of wirings passing through the lower hierarchy is one is shown. However, the number of wirings passing therethrough is not limited. Depending on the function, the size of the macro cell, the distance between external terminals, and the like, appropriate passing wiring may be performed according to various modes.

In the above embodiment, an example is shown in which a repeater is embedded in a lower hierarchy, but it is not necessary that the repeater be used. For example, an inverter, a clock buffer, ordinary block information, or a buffer as a delay element may be embedded.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to FIG.
The present embodiment is different in that the layout performed in the upper hierarchy is not a repeater insertion but a clock buffer insertion. Referring to FIG. 12, an upper layer is denoted by 401, and a lower layer macro cell is denoted by 402. When a clock buffer insertion process is performed in order to reduce the clock skew in the upper layer 401, a clock buffer is inserted in several stages from the root buffer to the external terminal at the terminal or an FF (Flip Flop). . FIG. 12 shows the root buffer 403, the inserted clock buffer 404-406, and the terminal FFs 407-412. At this time, an example in which the clock buffer 404 is arranged on the lower layer macro 402 is shown. Further, without providing a virtual terminal, wiring is performed from the route buffer 403 to the clock buffer 404, and the terminal 409,
An example of distribution to 410 is shown. The clock of the clock buffer 405 is supplied to the terminals 411 and 412.
And is distributed to.

In the hierarchical layout design, even when a clock buffer is inserted in the upper hierarchy, the following wiring embedding process can be performed on the macro cell 402 according to the flowchart of FIG.

Clock buffer 40 in upper layer 401
4 to 406, the clock buffer 40
When 4 to 406 cannot be arranged on the lower layer macro cell 402, the clock buffer is arranged so as to avoid the macro cell 402, and the wiring length also increases. Since the clock skew is wired in accordance with the skew to the slowest FF, the total clock wiring increases unless the present invention is used. For this reason, in the present embodiment, an example in which the entire wiring is performed using a repeater, a buffer, an inverter, or the like in consideration of the wiring and the delay time due to the wiring in consideration of the location of the lower hierarchy as well as the upper hierarchy. Is shown.

[0047]

According to the present invention, since the arrangement position of the repeater arranged on the macro cell can be held, even if the wiring passing over the macro cell is embedded in the lower layer macro in the hierarchical layout, the wiring delay in the upper layer is reduced. Timing can be guaranteed. The position of the repeater arrangement is a result of the repeater insertion processing executed in a state where the wiring is expanded in the upper hierarchy. Referring to FIG. 16, the delay timing between the terminals 151 and 152 is guaranteed by holding the arrangement position of the inserted repeater 155 in consideration of the delay time between the terminals 151 and 152 at the start and end points of the upper hierarchy. . Further, according to the present invention, redundant wiring in hierarchical layout design can be reduced. As described with reference to the wiring 132 in FIG. 10, when the wiring connected to the external terminal of the lower hierarchy is embedded in the macro of the lower hierarchy, the redundant external wiring is moved by moving the existing external terminal position to the optimum position. Can be reduced, and the wiring property in the lower hierarchy can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart of a hierarchical layout process according to the present invention.

FIG. 2 is a state diagram after an initial layout process of a hierarchical layout according to the present invention.

FIG. 3 is a state diagram after virtual terminal creation processing of a hierarchical layout according to the present invention.

FIG. 4 is a state diagram after a wiring division process of a hierarchical layout according to the present invention.

FIG. 5 is a state diagram after a layout change process of a hierarchical layout according to the present invention.

FIG. 6 is a state diagram after a layout change process of a hierarchical layout according to the present invention.

FIG. 7 is a diagram showing a state after rearrangement and routing processing of a hierarchical layout according to the present invention.

FIG. 8 is a diagram showing a state after rearrangement and wiring processing of a hierarchical layout according to the present invention.

FIG. 9 is a flowchart of a virtual layout virtual terminal creation process according to the present invention.

FIG. 10 is a state diagram of a virtual layout virtual terminal creation process according to the present invention.

FIG. 11 is a state diagram of another wiring arrangement of a hierarchical layout according to the present invention.

FIG. 12 is a state diagram of another wiring arrangement of a hierarchical layout according to the present invention.

FIG. 13 is a state diagram before and after a conventional hierarchical layout.

FIG. 14 is a state diagram before and after a conventional hierarchical layout.

FIG. 15 is a view for explaining a principle of delay time of a hierarchical layout;

FIG. 16 is a state diagram before and after insertion of a repeater in a conventional hierarchical layout.

[Explanation of symbols]

21 upper layer processing 22 lower layer processing 101 upper layer 102 lower layer 103, 104 external terminal 105, 106 OBS (wiring prohibited area) 108, 109, 116, 117 virtual terminal 110, 111, 112 wiring 113 repeater 118, 119 wiring 120 , 122, 123, 125, 124, 126 external terminal 130 repeater 151, 152 external terminal 153, 154 wiring 155, 162 repeater 201 placement and wiring processing 202 virtual terminal creation processing 203 wiring division processing 204 layout change processing 205 relocation wiring processing 206 Layout change processing 207 Relocation wiring processing 215 Virtual terminal creation processing 301, 302 Terminals 303, 304, 305 Wiring 306 Repeater 401 Upper layer 402 Lower layer 403 Route buffer 404-4 06 Clock buffer 407-412 External terminal (FF)

Claims (7)

(57) [Claims] In a hierarchical layout method of a semiconductor integrated circuit, timing between terminals in an upper hierarchy is guaranteed.
In order to pass through the macro (lower level),
The layout result is transferred to the lower-level wiring route and the repeater.
And embedding it in the lower hierarchy while maintaining the arrangement position of the hierarchy. 2. In a hierarchical layout method of a semiconductor integrated circuit, a wiring between terminals of an upper layer passing on a lower layer macro is connected to one of a repeater, a buffer, and an inverter.
A hierarchical layout method comprising arranging and connecting the above, and embedding at least one of the repeater, buffer, and inverter in the lower hierarchical macro. 3. A hierarchical layout method for a semiconductor integrated circuit having a plurality of hierarchies .
The wiring information of the terminal wiring of the upper layer
When embedding in a cross cell , the placement path and the placement position of one or more of repeaters, buffers, and inverters are virtual terminals.
And a virtual layout. 4. A hierarchical layout method for a semiconductor integrated circuit having a plurality of layers, wherein the method passes over a macro of a lower layer .
When embedding an inter-terminal wiring of an upper hierarchy in a macro cell of the lower hierarchy, an existing external terminal of the macro cell is moved and redundant wiring is deleted. 5. A hierarchical layout method for a semiconductor integrated circuit having a plurality of layers, wherein the method passes over a macro of a lower layer .
Said the repeater of the inter-terminal wiring of the upper layer lower layer of Ma that
A hierarchical layout method comprising deleting unnecessary virtual repeaters when embedding in a cross cell . 6. A hierarchical layout method for a semiconductor integrated circuit having a plurality of hierarchies, a placement and routing process for executing an initial layout including a lower hierarchy as an upper hierarchy process, and a virtual terminal for a boundary between the upper hierarchy and the lower hierarchy. A virtual terminal creating process, a wiring dividing process of dividing the wiring at the position of the virtual terminal, a layout changing process of deleting the divided wiring and the repeater, and a re-arranging process after the layout changing. It consists of a placement and routing process, further, as the lower layer processing, after the wiring division processing in the upper layer, a repeater placed on the wiring and the lower layer is divided the wiring is embedded in the lower layer It is characterized by comprising a layout change process to be added, and a rearrangement and wiring process for rearranging and wiring after the layout change. Hierarchy layout method to. 7. The hierarchical layout method according to claim 6, wherein the virtual terminal creation processing determines whether or not wiring of the lower hierarchical macro cell is a target, and three or more points on the boundary are determined. It is determined whether or not there is, and if the distance between consecutive points on the boundary is less than a predetermined distance, it is excluded from the target, and then it is necessary to connect to the external terminal and move the position of the external terminal? It is determined whether or not the wiring that passes through the lower hierarchy has a passing distance of less than or equal to a predetermined distance. If the wiring is within a target, the wiring is changed. A hierarchical layout method characterized by creating terminals.