JPH11177029A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design wiring layout automatically while inhibiting concentration of wiring density by forming a wiring layer for an external circuit, in which wirings used for a circuit excepting a specific layout region in the direction forming an angle to the direction of regular-interval arrayed wirings are arrayed at regular intervals, to the specific layout region. SOLUTION: Specific macro-wirings in a specific layout region are wired in the direction forming an angle to the direction of regular-interval arrayed wirings, and are right-downward oblique wirings laid at regular intervals. The wirings are used for a CPU 20, a data processing section 30 and control circuit sections 40 and 50 excepting the specific layout region. In wirings utilizing the specific macro-wirings, the overall length is shortened, and the length laid in the peripheral region of a storage circuit 10 is shortened. The wirings laid in the peripheral region of the storage circuit 10 are reduced as a whole. Accordingly, layout of the wirings, in which mutual effects between the wirings are inhibited, can be designed automatically be the automatic wiring function of a CAD while suppressing the concentration of wiring density.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a specific layout region in which, in addition to a base such as a diffusion layer, a wiring layer of a wiring pattern of a fixed direction arranged at equal intervals is formed. In particular, a wiring laying design that suppresses the mutual influence between wirings can be performed while suppressing the concentration of wiring density.
The present invention relates to a semiconductor integrated circuit that can be automatically controlled by an automatic placement and routing function of AD (computer aided design). In the following, the automatic placement and routing function includes those having only the automatic routing function.

[0002]

2. Description of the Related Art In order to reduce the size of an electronic device, a device which has conventionally been constituted by a plurality of chips is often made into a single chip. For example, in the integrated circuit layout diagram of FIG.
, CPU 20, data processing unit 30, control circuit unit 4
0 and 50. That is, the CPU 20
In FIG. 1, the semiconductor integrated circuit 1 is configured as a single chip, which is conventionally configured as an independent chip such as the memory circuit unit 10 and the like.

Further, such a semiconductor integrated circuit 1 is provided with a CA
It is designed using a macro circuit registered in the library of the D device and its layout. For example, since the storage circuit unit 10 is registered in advance as a memory macro,
The semiconductor integrated circuit 1 is designed using this.

FIG. 2 is an integrated circuit layout diagram of the storage circuit section 10. In the storage circuit section 10, a large number of memory cells (not shown) are arranged vertically and horizontally at equal intervals. The word lines and bit lines for these memory cells are wirings in a certain direction, and are densely laid at equal intervals. In the figure, the word lines indicated by broken lines are all in the horizontal direction, and the bit lines indicated by dashed lines are all in the vertical direction. Note that wirings in a fixed direction arranged at equal intervals, such as the word lines and the bit lines, are hereinafter referred to as equal-interval arrangement wirings.

In FIG. 1, the following three wirings are considered as examples. That is, first, from position P1 to position P2
Wiring L1. Second, the wiring L2 from the position P3 to the position P4. Third, the wiring L from the position P5 to the position P6
3.

The lines L1 to L3 are connected to the storage circuit unit 10
3 through the shortest distance or a short distance as shown in FIG. In this figure and FIGS. 4 and 6 described later, the wiring L1 is a broken line, the wiring L2 is a dashed line, and the wiring L
3 is a two-dot chain line.

[0007]

In FIG. 3, first,
The wiring L1 has a large coupling capacitance to word lines in the same direction in the horizontal direction. In addition, the wiring L2 has a large coupling capacitance with respect to the bit line in the same direction in the vertical direction. As described above, the coupling capacitance between the parallel wirings becomes large and affects each other. In particular, the signal on the bit line may be weak, and the memory performance may be degraded due to such mutual influence, for example, an error may occur in the read bit data. CAD
In the automatic placement and routing function, if wiring is performed so as not to be parallel to the bit line, a large limitation occurs.
Problems such as a decrease in the number of routable wires occur.

Next, since the wiring L3 is an oblique wiring,
The problem of the coupling capacitance with respect to the word line and the bit line as described above hardly occurs. However, such an oblique wiring cannot usually be handled by the automatic placement and routing function of CAD. Or it is very difficult. Therefore, a manual integrated circuit layout design is required, and work efficiency is greatly reduced.

In order to solve the problems of the wirings L1 to L3 in FIG. 3, it is conceivable that the wirings L1 to L3 are routed around the storage circuit section 10 as shown in FIG. However, in this case, restrictions on the automatic placement and routing function of the CAD become large, and the above-described wiring L
It may be larger than the limit of 1 or L2 in FIG.
When the wiring is performed as shown in FIG. 4, the number of wirings arranged in the area around the storage circuit unit 10 indicated by a broken line in FIG. is there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a wiring laying design which suppresses mutual influence between wirings by using a CAD automatic placement and routing function while suppressing concentration of wiring density. It is an object to provide a semiconductor integrated circuit that can be automated.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a specific layout region in which a wiring layer of a wiring pattern in a fixed direction arranged at equal intervals is formed in addition to a base such as a diffusion layer. In the specific layout region, wiring used for circuits other than the specific layout region in a direction forming an angle with respect to the direction of the equidistant arrangement wiring includes an external circuit wiring layer arranged at equal intervals. This feature solves the above problem.

In the semiconductor integrated circuit, a circuit formed in the specific layout area includes a plurality of memory cells arranged at equal intervals vertically and horizontally, and word lines and word lines corresponding to these memory cells are arranged at equal intervals. As the storage circuit in which the bit lines are laid, the specific layout area has been clarified as a target to which the present invention can be effectively applied.

Hereinafter, the operation of the present invention will be briefly described.

In the present invention, in addition to a base such as a diffusion layer,
The specific layout region in which the wiring layers of the wiring patterns in the fixed direction arranged at equal intervals are formed is, for example, the storage circuit unit 10 in the above-described semiconductor integrated circuit 1 of FIG. Note that the specific layout area is not limited to a storage circuit.

In such a specific layout area,
According to the present invention, for an external circuit, wirings used for circuits other than the specific layout area (hereinafter, referred to as specific macro wirings) are arranged at equal intervals in a direction at an angle to the direction of the equally-spaced wiring. A wiring layer is provided in advance. For example, if the storage circuit section 10 is a memory macro, the memory macro itself is provided with the external circuit wiring layer in advance.

The direction of the specific macro wiring as described above forms an angle with the direction of the equally-spaced wiring in the specific layout area, and is not parallel to the direction of the equally-spaced wiring. Therefore, the coupling capacitance between the specific macro wiring and the equally-spaced wiring can be suppressed, and the mutual influence between the wirings can be suppressed. Further, since the specific macro wiring is laid in advance, it is not necessary to perform wiring again by the automatic placement and wiring function of CAD. Even if the specific macro wiring is oblique wiring, there is no problem in the automatic placement and routing function, and in this case, the automatic placement and routing function of CAD is easy to use. When a specific macro wiring is used, usually, only the wiring is selected by the automatic placement and routing function of CAD. In this case, the wiring in the automatic placement and routing is usually performed on both ends of the selected wiring of the specific macro wiring.

As described above, according to the present invention, it is possible to automatically perform the wiring laying design which suppresses the mutual influence between the wirings by the automatic placement and routing function of the CAD while suppressing the concentration of the wiring density. Efficiency can be improved.

The present invention does not particularly limit the handling of unused specific macro wiring. The unused specific macro wiring may be left as a wiring that is not connected to anywhere. Alternatively, when using CAD, unused specific macro wiring may be automatically removed.

The present invention does not limit the wiring interval between specific macro wirings in a specific layout area. The wiring interval may be determined according to a circuit formed in a specific layout area. For example, when a storage circuit is formed in a specific layout area, the wiring interval of the specific macro wiring may be determined according to the type of the storage circuit, the arrangement interval of the memory cells, and the installation interval of the word lines and the bit lines. Good.

Note that the angle between the direction of the specific macro wiring and the direction of the equally-spaced wiring in the specific layout area need not be zero degrees, that is, the same direction (parallel), and the present invention particularly limits the angle. Not something. As the angle approaches 90 degrees and the specific macro wiring and the equidistantly arranged wiring approach the orthogonal state, the coupling capacitance can be suppressed and the mutual influence between the wirings can be suppressed. What is necessary is just to determine the utilization form and convenience of macro wiring comprehensively. Alternatively, for example, when a storage circuit is formed in a specific layout area, the type of storage circuit, the arrangement interval of memory cells, the laying interval of word lines and bit lines, etc. You may decide.

The present invention does not limit the number of wiring layers in a specific layout area. Further, there is no limitation on which wiring layer among the plurality of wiring layers is used as the wiring layer for the external circuit. Note that the wiring layer used for the external circuit wiring layer may be used other than the external circuit wiring layer, and it is particularly effective to use the wiring layer other than the external circuit wiring layer outside the specific layout region.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

In the following embodiments, the present invention is applied to the semiconductor integrated circuit 1 described above with reference to FIGS. That is, in addition to the base such as the diffusion layer, the storage circuit unit 10 in which the wiring layer of the pattern of the equally-spaced wiring is formed.
The present invention is applied to the semiconductor integrated circuit 1 having the above-described region.

Here, in the following embodiment, the area of the storage circuit section 10 is applied as a specific layout area of the present invention. Further, in the storage circuit section 10, the word lines and the bit lines are arranged at equal intervals. In addition, by using a specific macro wiring provided in a specific layout area by applying the present invention, a wiring laying design that suppresses mutual influence between wirings can be automatically arranged while suppressing concentration of wiring density. It can be done automatically with the wiring function.

First, in the first embodiment to which the present invention is applied, the specific macro wiring in the specific layout area is as shown in FIG. 5, and is a wiring in a direction at an angle to the direction of the equally-spaced array wiring. , Diagonally lower right wirings laid at equal intervals. The wiring is located outside the specific layout area.
It is used for the wiring of the PU 20, the data processing unit 30, and the control circuit units 40 and 50.

In the present embodiment, the above-mentioned wirings L1 to L3 utilizing the specific macro wiring are as shown in FIG. 6, for example. Compared with the wiring L1 of FIG. 3 described above, the wiring L1 of FIG. 6 has a shorter overall length and a shorter length laid in the peripheral region of the storage circuit unit 10. Compared with the wiring L2 in FIG. 3, the wiring L2 in FIG. 6 has a shorter length laid in the area around the storage circuit unit 10. Compared with the wiring L3 in FIG. 3, the wiring L3 in FIG. 6 has a shorter overall length and a shorter length laid in the area around the storage circuit unit 10. Further, as a whole, the number of wirings laid in the area around the storage circuit unit 10 is reduced.

Next, a second embodiment to which the present invention is applied
In the fourth embodiment, the specific macro wirings are shown in FIGS.
As shown in FIG. In any of the embodiments, the specific macro wiring is a wiring in a direction at an angle to the direction of the equally-spaced wiring. The wiring is used for wiring of the CPU 20, the data processing unit 30, and the control circuit units 40 and 50 other than the specific layout area.

First, in the second embodiment, the specific macro wiring is located at the upper left and lower right portions of the specific layout area.
This is an oblique wiring that is laid at equal intervals and rises to the right. The lower left part and the upper right part are diagonally lower right wirings laid at equal intervals. In the third embodiment, the specific macro wiring is a slightly oblique vertical wiring. In the fourth embodiment, the specific macro wiring is a wiring in a substantially horizontal direction including a wiring part descending to the right.

Next, in the fifth embodiment to which the present invention is applied, the specific macro wiring is as shown in FIG. In the present embodiment, the specific macro wiring is formed in a certain wiring layer, that is, the specific macro wiring of the first embodiment itself and the specific macro wiring of the first embodiment that is formed in a different wiring layer. And a specific macro wiring rotated by 90 degrees. These specific macro wirings are directions that form an angle with respect to the direction of the equally spaced wirings. The wiring is provided in the CPU 20, the data processing unit 30, the control circuit unit 4,
Used for 0 and 50 wiring.

Next, in the sixth embodiment to which the present invention is applied, the specific macro wiring is as shown in FIG. In the present embodiment, the specific macro wiring is formed in a certain wiring layer, the specific macro wiring of the third embodiment itself, and the specific macro wiring of the third embodiment formed in a different wiring layer. And a specific macro wiring rotated by 90 degrees. These specific macro wirings are directions that form an angle with respect to the direction of the equally spaced wirings. The wiring is provided in the CPU 20, the data processing unit 30, the control circuit unit 4,
Used for 0 and 50 wiring.

Also in the second to sixth embodiments, the present invention is applied similarly to the above-described first embodiment, so that the wiring laying design in which the mutual influence between the wirings is suppressed can be reduced. The concentration can be suppressed and the automatic placement and routing function of the CAD can be used for the automatic operation.

[0032]

According to the present invention, a wiring laying design which suppresses mutual influence between wirings can be performed while suppressing concentration of wiring density.
This can be done automatically by the CAD automatic placement and routing function.

[Brief description of the drawings]

FIG. 1 is an integrated circuit layout diagram of an example of a semiconductor integrated circuit.

FIG. 2 is an integrated circuit layout diagram of an example of a storage circuit unit built in the semiconductor integrated circuit.

FIG. 3 is an integrated circuit layout diagram of a first conventional example of wiring passing through the storage circuit section.

FIG. 4 is an integrated circuit layout diagram of a second conventional example of wiring passing through the storage circuit section.

FIG. 5 is an integrated circuit layout diagram showing a specific macro wiring according to the first embodiment to which the present invention is applied;

FIG. 6 is an integrated circuit layout diagram showing an example of a wiring using the specific macro wiring of the first embodiment.

FIG. 7 is an integrated circuit layout diagram showing a specific macro wiring according to a second embodiment to which the present invention is applied;

FIG. 8 is an integrated circuit layout diagram showing a specific macro wiring according to a third embodiment to which the present invention is applied;

FIG. 9 is an integrated circuit layout diagram showing a specific macro wiring according to a fourth embodiment to which the present invention is applied;

FIG. 10 is an integrated circuit layout diagram showing a specific macro wiring according to a fifth embodiment to which the present invention is applied;

FIG. 11 is an integrated circuit layout diagram showing a specific macro wiring according to a sixth embodiment to which the present invention is applied;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 10 ... Storage circuit part 20 ... CPU 30 ... Data processing part 40, 50 ... Control circuit parts P1-P6 ... Position

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a specific layout region in which a wiring layer of a wiring pattern of a fixed direction arranged at equal intervals is formed in addition to a base such as a diffusion layer. Of the direction at an angle to the direction,
A semiconductor integrated circuit, wherein a wiring used for a circuit other than the specific layout area includes an external circuit wiring layer arranged at equal intervals in the specific layout area. 2. The circuit according to claim 1, wherein the circuit formed in the specific layout area includes a plurality of memory cells arranged at equal intervals vertically and horizontally, and the word lines and bit lines for these memory cells are arranged as the equal-interval wiring. A semiconductor integrated circuit, which is a storage circuit for laying wires.