JP2947219B2 - Wiring structure of standard cell type semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a wiring structure of a standard cell type semiconductor integrated circuit device.

[0001]

2. Description of the Related Art In a conventional standard cell type multilayer wiring structure, wiring is performed at one kind of wiring pitch for one wiring layer (the wiring pitch is the sum of the wiring width and the distance between wirings). I was Since this wiring pitch is determined by limitations in the manufacturing technology, it is usually small (thin thickness) for lower-layer wiring with excellent flatness during manufacturing.
In the upper layer wiring, the pitch was wide (thick).
Also, the pitch of the basic cell is designed to match the pitch of either wiring layer (usually the lower wiring layer) (usually, the cell size is larger than the wiring pitch, so it is an integral multiple of the lower wiring pitch). I was

[0002]

The first problem is that, in the above-mentioned prior art, wiring is performed at one kind of wiring pitch for one wiring layer. Is that they appear only once in a range equal to the least common multiple of each wiring pitch. Further, since the pitch of the basic cell is set in accordance with the pitch of one of the wiring layers, the point where the terminal of the basic cell and the grid of the wiring are at the same relative position is repeated only in a range equal to the least common multiple thereof. That is the point. Standard cell type LS having such a structure
In I (large-scale integrated circuits), after placing and wiring cells for a part of the circuit, the results are subject to restrictions when trying to transfer the results to the whole chip or to the placement and wiring for a wider circuit range. become. In other words, in the standard LSI, the cell arrangement position can be moved in units of cell pitch, but if the wiring pitch is not equal to a divisor (of the moving distance), the moved wiring will be in the correct grid. It means that you can not move because you can not get on.

[0003] The second problem is that in the conventional technique, when wiring is performed using a CAD tool, there are many routes that can be wired, so that it takes time to process.

[0004] The third problem is that the pitch is small (usually,
The lower layer wiring has a lower EM resistance than the upper layer wiring, and the EM resistance of the entire signal is determined here.

[0005] The fourth problem is that the R
Since C is determined by the pitch, if a low-capacity, low-resistance wiring is required for a specific signal to increase the speed, it is necessary to pass one wiring at a plurality of pitches.
That is, the wiring property is deteriorated.

An object of the present invention is to improve the degree of integration of an integrated circuit,
An object of the present invention is to provide a wiring structure capable of improving EM resistance, achieving high speed, and improving design efficiency.

[0007]

According to the present invention, a first wiring layer which is wired at a first wiring pitch to make the main axes equal, a second wiring layer,
In the semiconductor integrated circuit of the static <br/> Ndadoseru scheme and a second wiring layer to be wired in the wiring pitch of the first distribution
A portion where the relative positional relationship between the wiring of the wiring layer and the wiring of the second wiring layer is equal is determined by the first wiring layer and the second wiring layer.
The first arrangement has a smaller number of repetitions than the case where only one kind of pitch exists in each of the line layers.
The wiring at the third wiring pitch is formed on the wiring layer or the second wiring layer.
Has been inserted .

The above means can be repeated so that the relative positions of the lower and upper wiring layer grids are the same within a pitch range in which cells can be moved equal to an integral multiple of the basic cell pitch. After arranging and wiring the cells, the result can be freely moved when the result is to be taken over by arranging and wiring for the entire chip or a wider circuit range.

Further, since the point where the relative positions of the lower and upper wiring layer grids coincide with each other is repeated in a small range as compared with the prior art, the number of routes that can be routed when wiring is performed using a CAD tool is reduced. Processing is completed in a short time.

When it is necessary to use a lower layer wiring for a wiring with severe EM, it is possible to relax the restriction on the EM by using a wide wiring passing through a wide pitch portion. it can.

A signal having a wide width (low resistance) or a wide wiring interval (low capacitance) for a signal requiring a high speed operation
With the use of, a wiring with a small delay can be realized without deteriorating the wiring property.

[0012]

FIG. 1 is a diagram showing the arrangement of standard cells and the state of their wiring when the present invention is implemented.

FIG. 2 is a diagram showing the operation of the present invention.

A part of the circuit 10 of the LSI is a function block of standard cells (having a height of 8 microns).
2, 3, and 4, and wirings 5, 6, 7, 8,
9 and 10, and the arrangement and wiring are performed as shown in FIG. The line shown on the left of the drawing shows the wiring pitch of the first layer (equal spacing, for example, 1 micron), and the line shown on the right of the drawing is the wiring pitch of the third layer (wiring having the same principal axis as the first layer). (There is a location with an interval of x (1.48 microns) and a location of y (2.08 microns)).
Dotted lines indicate locations where the first layer wiring and the third layer wiring match, and the first layer wiring is one in eight.
For the third and third layer wirings, one out of five wirings exists. In addition, since the height of one cell and the pitch at which the five third-layer wirings are repeated coincide with the vertical pitch of the basic cell, the positions of the terminals 1a, 1b, 2a, 2b, 3a, 3b, and 4a of the cell are different from those of the cell. The wiring positions also match.

Therefore, as shown in FIG. 2, when the area 10 which has been arranged and wired in the LSI 11 is moved to 10 ', the area can be freely moved in the vertical direction in units of 8 microns.

Also, the number of gratings existing in the 8 micron repetition range is 8 for the first layer + 5 for the third layer-1 (coincidence) = 1.
2, which is smaller than 13 or 14 wirings when the wiring pitch of the third layer is uniform and 1.48 microns.

FIG. 3 is a plan view showing another embodiment of the present invention. For a plurality of wiring pitches x and y, the wiring width l and the wiring spacing w are x = 11 + w1, y = 12 + w
If it is set to 1, the resistance Rb of the wiring b becomes Rb = (11/12) · Ra with respect to the resistance Ra of the wiring a. Further, the EM resistance is improved in accordance with the ratio between l1 and l2, so that a high-speed operation can be achieved by using a wide wiring for a wiring having a high current density. As shown in FIG. 4, x = l1 + w
If 1, y = l1 + w2, the capacitance between the adjacent wirings of the wiring b becomes cy = (w1 / w2) · cx, and the load decreases, so that the speed of a signal using the wiring can be increased.

[0018]

The first effect is that, as shown in FIGS. 1 and 2, the result of arranging and wiring a part of the circuit according to the present invention can be used as it is in a wider range of designs.

The reason is that the relative positions of the terminals of the arranged cells and the upper and lower wiring layers connected thereto are not changed even when the cells are moved.

The second effect is that the wiring processing can be speeded up.

The reason is that the number of virtual wiring grids is reduced in the example shown in FIG.

A third effect is that a wiring with high EM resistance and low resistance can be obtained without sacrificing the wiring properties.

The reason is that as shown in FIG. 3, the width of the wiring can be increased where the wiring pitch is widened.

A fourth effect is that a low-capacity wiring can be obtained without sacrificing the wiring properties.

The reason is that, as shown in FIG. 4, the wiring interval can be increased where the wiring pitch becomes wide.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing the operation of the present invention.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a conventional example.

[Explanation of symbols]

1-4 Standard cell function blocks (cells) 5,7 First layer wiring 6,9 Third layer wiring 8,10 Second layer wiring 1a, 1b, 2a, 2b, 3a, 3b, 4a Cell input / output terminals 11 Part of LSI circuit 12 LSI (semiconductor integrated circuit)

Claims (1)

(57) [Claims] A first wiring pitch for equalizing the main axes;
A first wiring layer to be wired and a second wiring pitch
That in the semiconductor integrated circuit of the second standard cell system having a wiring layer, the relative positional relationship is equal portion of the wiring of the first wiring layer and the second wiring layer, the first wiring Layer
And the second wiring layer has a smaller number of repetitions as compared with the case where only one kind of pitch exists ,
A third wiring pin is provided on the first wiring layer or the second wiring layer.
A wiring structure for a semiconductor integrated circuit, wherein wiring is inserted in the switch.