JPH08236633A - Placement of logic cell - Google Patents

Abstract

PURPOSE: To realize high speed placement of logic cell by placing imaginary cells except an objective module at the time of layout thereof and determining the placement of each terminal being connected with a nonobjective module while taking account of the positional relationship of a module being connected with the objective module. CONSTITUTION: A module region 11a represents an objective module region for placement and routing whereas module regions 11b, 11c, 11d represent nonobjective module regions. Imaginary cells 13b, 13c, 13d are placed, respectively, in the center of the nonobjective module regions 11b, 11c, 11d and each terminal of the objective module is placed in the objective module region 11a based on the length of a line 15 connecting each terminal of the objective region 11a with the terminal 14b, 14c, 14d of the imaginary cell. Furthermore, a plurality of logic cells constituting the objective module are placed and routed in the objective module region 11a. With such method, the logic cells can be placed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a plurality of logic cells forming a semiconductor integrated circuit on a semiconductor substrate.

[0002]

2. Description of the Related Art Recently, as semiconductor integrated circuits have become larger and larger in scale, the time required to place and route logic cells using an automatic layout tool is gradually increasing at the design stage. Therefore, increasing the speed of automatic layout and shortening the required time has become a major issue. Among semiconductor integrated circuits, ASIC (Appl
ication Specific Integrate
In the case of ed circuit), there are many opportunities to perform automatic layout, so there is a particularly strong demand for higher speed.

Generally, in order to increase the speed of the automatic layout, there are a method of improving the speed of the automatic layout tool by improving the algorithm, a method of increasing the execution speed of the automatic layout tool by using a computer having a high calculation speed, and the like. However, these methods are expensive and have economic limitations, so we cannot rely on them alone. Therefore, the parallel layout method is attracting attention as one solution for increasing the layout speed.

There are the following two conventional parallel layout methods. A first method is to divide a plurality of logic cells forming a semiconductor integrated circuit into a plurality of modules, determine a position of a terminal for connecting to another module for each module, and This is a method of laying out the layout and wiring of the logic cells inside and the wiring to the terminals of other modules in parallel.

FIG. 4 is an example of the flow of such a parallel layout method. First, in step S1, the semiconductor integrated circuit is divided into a plurality of modules for each function,
The entire netlist describing the connection information of all the logic cells constituting the semiconductor integrated circuit is divided into the module-specific netlists. Next, in step S2, each module area for arranging and wiring the logic cells belonging to each module is allocated.

Next, in step S3, the position of the terminal for connecting each module to another module is determined. Next, in step S4, the netlist for each module is assigned to each of the plurality of calculation means. Next, in step S5, the placement and wiring in each module are performed in parallel using the above-described plurality of calculation means based on the position of the terminal determined in step S3.

Next, in step S6, wiring between the modules is performed. FIG. 5 is a schematic diagram showing a state after the terminal positions of the module are determined in step S3 of FIG. In step S1 and step S2, a plurality of logic cells forming the semiconductor integrated circuit are divided into functional modules, and each module area 11 is provided in the module placement area 10 on the circuit board of the semiconductor integrated circuit.
After a, 11b, 11c, and 11d are assigned, terminals 12a, 12b from each module to another module,
The positions of 12c and 12d are determined.

However, at the stage where step S2 ends, each module area 11a, 11b, 11c, 11d
It is very difficult to determine the position of the terminal because each logic cell is not placed inside the module.Also, even if the position of the terminal can be determined, the wiring between modules does not intersect. In many cases, satisfactory results cannot be obtained because the wiring length becomes too long. Therefore, trial and error is often repeated many times, and there is a problem in that the layout takes a long time.

Therefore, as a second method, an automatic layout method has been proposed in which the terminal positions are not determined in advance. That is, an overlapping area in which cells that connect between both modules are collected is provided between adjacent module areas, the layout is determined for each module and the overlapping area, and then the cells in the overlapping area are allocated to the corresponding adjacent modules. Is the way. However, with this method, the method of allocating cells in the overlapping area must rely on trial and error,
In many cases, the overhead becomes large, and it is not possible to achieve much speedup. Further, this method has a problem that connection information with other modules than the adjacent module is not taken into consideration.

[0010]

In view of the above circumstances, the present invention does not predetermine the position of the terminal for each module, and also takes into account the connection information with other modules than the adjacent module. Therefore, it is an object of the present invention to provide a method of arranging logic cells, which can arrange logic cells at high speed.

[0011]

According to a method of arranging logic cells of the present invention which achieves the above-mentioned object, a plurality of logic cells constituting each of a plurality of modules in which one semiconductor integrated circuit is divided according to functions are provided. In a method of arranging logic cells, which are allocated on a semiconductor substrate and simulated in respective module areas corresponding to the respective modules, a predetermined target module of a plurality of modules constituting one semiconductor integrated circuit is provided. When arranging the logic cell in the module area corresponding to the target module, all the non-target modules in each module area corresponding to each non-target module except the target module among the plurality of modules Each virtual cell that collects logical cells for each non-target module is arranged, and each virtual cell and the target module are arranged. , Based on the distance between the plurality of terminals connected to each virtual cell, the target module, and wherein the determining the arrangement positions of the terminals connected to the non-target module.

Here, when arranging each virtual cell in each module area corresponding to each non-target module described above, it is preferable to arrange each virtual cell at the center of gravity of each module area.

[0013]

In the method of arranging logic cells of the present invention, since non-target modules other than the target module are considered as virtual cells, it is possible to perform a parallel layout in which a plurality of modules are respectively target modules. Since it is not necessary to determine the positions of the terminals in advance, the time required for layout can be significantly reduced.

According to the logic cell placement method of the present invention, the placement position of each terminal connected to the non-target module is determined in consideration of the positional relationship between the target module and all modules having a connection relationship. Therefore, it is possible to reduce the possibility that the wirings between the modules intersect and the wiring length becomes too long, and it is possible to obtain a placement and wiring that is almost optimal as a whole.

Further, by arranging each virtual cell at the center of gravity of each non-target module area, each logic cell is prevented from being unevenly arranged in the target module area, and the wiring length as a whole can be further shortened. it can.

[0016]

Embodiments of the present invention will be described below. FIG. 1 is a flow of an embodiment of a method of arranging logic cells of the present invention. First, in step S1, all logic cells of the semiconductor integrated circuit are divided into modules for each function.
That is, the entire netlist describing the connection information of all the logic cells forming the semiconductor integrated circuit is divided into the functional module netlists.

Next, in step S2, a virtual cell, which is a collection of all logic cells in the module, is set for each module. Next, in step S3, each module region corresponding to each module for arranging and wiring the logic cells belonging to each module is simulatedly allocated on the semiconductor integrated circuit substrate.

FIG. 2 is a schematic diagram showing how each module area is assigned. That is, FIG. 2 shows a state in which the module areas 11a, 11b, 11c, and 11d for arranging a plurality of logic cells forming each module are allocated in the module arrangement area 10 of the semiconductor integrated circuit board. Has been done. Next, in step S4 shown in FIG. 1, a certain module is set as a target module, and the center of gravity position of each module region corresponding to all other non-target modules other than the target module is set to
Each virtual cell in which all the logic cells of each non-target module are collected for each non-target module is arranged. In this step S4, each virtual cell is arranged with all modules as target modules.

Next, in step S5, the netlist for each module, the placement information of the virtual cells, etc. when all the modules are the target modules are assigned to each of the plurality of calculation means. Next, step S6
In the above, using the above-mentioned plurality of calculation means, the placement and wiring for each target module assigned to each calculation means are performed in parallel.

FIG. 3 is a schematic diagram showing a state of placement and wiring of the target module in a certain calculation means. FIG.
, The module area 11a is a module area (target module area) corresponding to the target module for placement and routing, and the other module areas 11b, 1
1c and 11d are module areas (non-target module areas) corresponding to non-target modules.

As shown in FIG. 3, the target module area 1
Each non-target module area 11b, 11c, 1 except 1a
At each barycentric position within 1d, each virtual cell 13b, 13c,
13d is arranged. And the target module area 1
Based on the lengths of a plurality of connection lines 15 that connect the terminals of 1a and the terminals 14b, 14c, and 14d of the virtual cells provided at the centers of these virtual cells, each terminal of the target module has a target module area 11a. Further, a plurality of logic cells constituting the target module are arranged and wired in the target module area 11a.

In this embodiment, each virtual cell 13b, 1 in each non-target module area 11b, 11c, 11d is
3c and 13d are non-target module areas 11b and 11
Although they are arranged at the respective centroid positions of c and 11d, by doing so, each logic cell in the target module area 11a is not biasedly arranged at a specific portion in the target module area 11a. , Each of the logic cells is distributed evenly in the target module area 11a, which is preferable.

Further, in this embodiment, the terminals 14b, 14c, 14d of the virtual cells are provided at the centers of the virtual cells 13b, 13c, 13d of the non-target modules. The position is not limited to the center of each virtual cell, and may be any position in the virtual cell, but is preferably the center of the virtual cell for the same reason as the arrangement position of the virtual cell.

In step S6 of FIG. 1, the plurality of calculation means perform the placement and routing in parallel for each target module. These multiple calculation means
Hardware may be configured on separate computers, or may be configured on a single computer in a time division manner. Finally, in step S7 shown in FIG. 1, wiring is performed between the modules for which the parallel layout has been completed.

[0025]

As described above, according to the method of arranging logic cells of the present invention, virtual cells other than the target module are arranged to lay out the target module. Since it is not necessary to determine the position of the terminal for each module in advance, it is possible to greatly reduce the time required for the layout.

Further, according to the logic cell placement method of the present invention, the placement positions of the terminals connected to the non-target module are determined in consideration of the positional relationship between the target module and all the modules having a connection relationship. Therefore, it is possible to reduce the possibility that the wirings between the modules intersect and the wiring length becomes too long, and it is possible to obtain a placement and wiring that is almost optimal as a whole.

By arranging each virtual cell at the position of the center of gravity of each non-target module area, each logic cell is not unevenly arranged in the target module area, and the wiring length can be shortened as a whole.

[Brief description of drawings]

FIG. 1 is a flowchart of an embodiment of a method of arranging logic cells of the present invention.

FIG. 2 is a schematic diagram showing a state in which each module area is allocated in a module arrangement area.

FIG. 3 is a schematic diagram showing a state of placement and wiring of a target module.

FIG. 4 is an example of a flow of a conventional parallel layout method.

FIG. 5 is a schematic diagram showing how the terminal positions of the modules are determined by the conventional parallel layout method.

[Explanation of symbols]

10 module arrangement area 11a, 11b, 11c, 11d module area 12a, 12b, 12c, 12d module terminal 13b, 13c, 13d virtual cell 14b, 14c, 14d virtual cell terminal 15 connection line

Claims (2)

[Claims] 1. A plurality of logic cells constituting a plurality of modules each of which is formed by dividing one semiconductor integrated circuit according to its function are provided in each module region allocated on a semiconductor substrate and corresponding to each of the plurality of modules. In a method of arranging logic cells to be arranged in a simulated manner, in arranging a logic cell of a predetermined target module among a plurality of modules forming one semiconductor integrated circuit in a module region corresponding to the target module, In each module area corresponding to each non-target module excluding the target module among the modules, each virtual cell in which all the logic cells of each non-target module are collected for each non-target module is arranged. Based on the distance between the virtual cell and a plurality of terminals of the target module connected to each virtual cell, the pair Modules, the method for arranging the logic cells, characterized in that to determine the positions of the respective terminals connected to each non-target module. 2. When arranging each virtual cell in each module area corresponding to each non-target module, each virtual cell is arranged at a center of gravity of each module area. Item 1. A method of arranging logic cells according to item 1.