JP2002368097A - Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macros - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress operation failures of a semiconductor integrated circuit due to increase of delay caused by signals changed to antiphase while propagating on two adjacent parallel wirings among a plurality of parallel laid wirings, with reducing the increase of the area. SOLUTION: For laying e.g. 6-bit wirings, wirings 10 of three less significant bits of a high signal change frequency and wirings 20 of three significant bits of a low signal change frequency are alternately disposed to lay the wirings 20 of significant bits, each sandwiched between the right and left wirings 10 of less significant bits. Thus the wiring 20 of significant bit lines acts on the wiring 10 of less significant bit lines as a shield wiring against the signal change. This effectively suppresses the increase of the delay caused by signals changed to antiphase while propagating on the wirings 10 of less significant bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring method in a layout design method of a semiconductor integrated circuit, a semiconductor integrated circuit having a plurality of wirings, and a function macro.

[0002]

2. Description of the Related Art FIG. 17 shows a main part of a semiconductor integrated circuit wired by a conventional general wiring method. In the figure,
10 (0) is the lower bit of the 0th bit which is the least significant bit, 10 (1) is the lower bit of the 1st bit, 1
0 (2) is the lower bit wiring of the second bit, 20 (k) is the upper bit wiring of the k-th bit which is the highest bit, and 20 (k−
1) is the upper bit wiring of the (k-1) th bit, and 20 (k-
2) is an upper bit wiring of the (k-2) th bit, and the respective wirings are arranged in ascending order from the least significant 0th bit or in descending order from the most significant bit. In addition, the distance between the wirings is also set to the same distance. In this case, the arrangement is such that the lower bits and the upper bits are arranged side by side.

FIG. 19 is a view showing the wiring 20 for the k + 1 bits.
2 shows the configuration of a function macro 40 such as a memory to which (k) to 10 (0) are connected. The function macro 40 includes a wiring 2 of k + 1 bits arranged in ascending order from the lowest bit 0 (or descending order from the k-th bit).
K + 1 terminals 40 connected to 0 (k) to 10 (0)
t (k) to 40t (0). Therefore, these terminals 40t (k) to 40t (0) are also arranged in ascending order from the lowest 0th bit (or in descending order from the highest kth bit). These k + 1 terminals 40t (k) -4
0t (0) transmits or receives information as one data or address as a whole.

FIG. 18 is an explanatory diagram of the capacitance between wirings. Assuming two wirings 1 and 2 running in parallel, a parasitic capacitance is inevitably generated between them, and this is called an inter-wiring capacitance 3. 2
When one of the wires changes from 0 to 1 of the digital signal and the other changes from 1 to 0, the signal changes to the opposite phase. When the signals of the adjacent parallel wirings 1 and 2 change in opposite phases, the charges existing in the parasitic capacitance between them (synonymous with the inter-wiring capacitance 3) are attracted, so that the signal propagation delay is caused. Becomes larger.

Advances in semiconductor miniaturization manufacturing technology are very rapid. At a miniaturization level of 0.5 μm or less, a sufficient wiring interval is provided, and therefore, the value of the parasitic capacitance is small, and the above-mentioned increase in signal delay is increased. No problem occurred, but 0.35
From the miniaturization level of about μm and 0.25 μm, some high-speed wiring is taken up as a problem.
At a miniaturization level of 0.18 μm or less, the problem becomes more prominent each time the process is updated, and at the same time, it is difficult to accurately grasp the operation due to the capacitance between wirings, which may lead to unexpected design defects. It has become apparent.

Conventionally, as a technique for solving the problem of an increase in signal delay, when high-speed operation is required, rules are set so as to increase the distance between wirings or shield wiring is separately provided between wirings. Are run in parallel, or the wires are twisted (crossed).

[0007]

However, in the above-mentioned conventional techniques, any technique of setting a long distance between wirings, providing shield wirings, twisting, etc., comes at the cost of increasing the area of the semiconductor integrated circuit. Had to pay. In addition, when wires having a high frequency of signal change are arranged in parallel, the probability that both signals change to the opposite phase at the same time increases. However, in the conventional wiring method shown in FIG. The lower bit has a higher signal change frequency than the upper bit. Therefore, when such lower bit wirings are arranged in parallel and close to each other, the signal propagates along with the simultaneous change of the signal to the opposite phase. The delay increases, and the probability of malfunction of the semiconductor integrated circuit increases significantly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit having a plurality of wirings in layout design, while effectively suppressing the signal propagation delay due to signal interference between the plurality of parallel wirings while suppressing an increase in area. It is an object of the present invention to provide a wiring method capable of suppressing the interference, and a semiconductor integrated circuit and a function macro capable of effectively suppressing such interference between signals.

[0009]

In order to achieve the above object, according to the present invention, when a plurality of wirings are provided, signals transmitted through the wirings have different changing frequencies from each other.
Pay particular attention to the fact that the signal line of the upper bit has a much lower signal change frequency than the signal line of the lower bit in multi-bit wiring. By appropriately arranging them based on the frequency of change of signals propagating through the wiring, interference between signals is effectively suppressed.

That is, the wiring method in the layout design of a semiconductor integrated circuit according to the first aspect of the present invention is a wiring method for wiring a plurality of bits in a planar or three-dimensional manner and in parallel in the layout design of the semiconductor integrated circuit. When arranging the wiring of the plurality of bits in ascending or descending order of bits, wiring of upper bits of a predetermined bit or more is arranged adjacent to each other at a predetermined interval, and wiring of lower bits less than the predetermined bit is arranged. They are arranged adjacent to each other with a distance interval exceeding the predetermined interval.

According to a second aspect of the present invention, there is provided a wiring method in a layout design of a semiconductor integrated circuit, wherein the plurality of wirings are wired in a plane or three-dimensionally and in parallel in the layout design of the semiconductor integrated circuit. For each of the plurality of wirings, a signal change frequency per unit time of a signal propagating through its own wiring is estimated or obtained by simulation, and based on the signal change frequency of each wiring, a signal having a high signal change frequency The plurality of wirings are arranged so that wirings that change less frequently do not adjoin.

According to a third aspect of the present invention, in the wiring method for designing a layout of a semiconductor integrated circuit according to the second aspect, the plurality of wirings are arranged when a plurality of bit signals are transmitted by the plurality of wirings. Regardless of the ascending or descending order of the bits, it is performed based on the signal change frequency of each wiring.

According to a fourth aspect of the present invention, in the wiring method for designing a layout of a semiconductor integrated circuit according to the second aspect, the plurality of wirings are arranged such that wiring having a high signal change frequency is replaced with wiring having a low signal change frequency. It is characterized by being carried out so as to be sandwiched between.

According to a fifth aspect of the present invention, there is provided a wiring method for designing a layout of a semiconductor integrated circuit, wherein the wiring of a plurality of bits is wired in a plane or three-dimensionally and in parallel in the layout design of the semiconductor integrated circuit. When arranging the wiring of the plurality of bits, one or more bit
It is repeated to arrange the book wiring and the wiring less than the predetermined bit adjacent to each other, and to arrange the wiring other than the predetermined bit and the other wiring less than the predetermined bit adjacent to each other. Features.

According to a sixth aspect of the present invention, in the wiring method in the layout design of a semiconductor integrated circuit according to the fifth aspect, wiring is performed from a most significant bit to a predetermined bit at a wiring interval twice as large as a predetermined wiring interval in descending order. Are arranged two-dimensionally and in parallel, and between the arranged wirings, the wirings are arranged two-dimensionally and in parallel from the least significant bit in ascending order.

According to a seventh aspect of the present invention, in the wiring method in the layout design of a semiconductor integrated circuit according to the fifth aspect, the first least significant bit wiring is arranged at a predetermined position.
A second step of arranging wiring for two bits from the most significant bit at positions on both the left and right sides of the least significant bit wiring;
A third step of arranging the unplaced wiring of 2 bits from the lowermost side at the left and right sides of the wiring of 2 bits from the uppermost side arranged in the second step, and 2 bits from the uppermost side A fourth step of arranging the unplaced wiring at the left and right sides of the wiring of 2 bits from the least significant side arranged in the third step; and wiring the third and fourth steps for all bits. And a fifth step to be repeated until is arranged.

The wiring method in the layout design of a semiconductor integrated circuit according to the present invention is characterized in that the wiring of a plurality of bits is n (n ≧ 2) in the layout design of the semiconductor integrated circuit.
A wiring method for wiring three-dimensionally and in parallel using a plurality of wiring layers, wherein a first step of arranging wiring of the least significant bit in a predetermined wiring layer, and wiring of a plurality of bits from the most significant bit, A second step of disposing the least significant bit wiring in the same wiring layer as the least significant bit wiring and another wiring layer so as to surround the least significant bit wiring arranged in the first step; Disposing the arranged wiring in the same wiring layer as the wiring for the plurality of bits from the uppermost and another wiring layer so as to surround the wiring for a plurality of bits from the uppermost arranged in the second step. The method is characterized by including three steps and a fourth step in which the second and third steps are repeated until wirings for all bits are arranged.

According to a ninth aspect of the present invention, in the wiring method in the layout design of a semiconductor integrated circuit according to the eighth aspect, the n wiring layers are two wiring layers.
In the step, the wiring of the least significant bit is arranged at a predetermined position on the lower layer, and in the second step, the wiring of three bits from the most significant bit is located on both the left and right sides and above the wiring of the least significant bit. The lower and upper wirings are arranged in the lower and upper wiring layers, and the unplaced wiring for the lower 4 bits in the third step is positioned on the left and right sides of the wiring for the upper 3 bits. And in the fourth step, the second and third steps are repeated until wiring for all bits is arranged.

According to a tenth aspect of the present invention, in the wiring method in the layout design of a semiconductor integrated circuit according to the eighth aspect, the n-th wiring layer is a two-layer wiring layer, and the least significant bit is provided in the first step. Are arranged at predetermined positions on the upper layer, and the upper and lower wirings are arranged such that the wiring for three bits from the highest in the second step is located on both left and right sides and below the wiring for the least significant bit. In the third step, the unplaced wirings of 4 bits from the lowest order are arranged in the upper and lower wiring layers so as to be located on the left and right sides of the wirings of 3 bits from the highest order. , The fourth
The method is characterized in that the second and third steps are repeated until wirings for all bits are arranged.

According to an eleventh aspect of the present invention, in the wiring method in the layout design of a semiconductor integrated circuit according to the eighth aspect, the n-layer wiring layer is a three-layer wiring layer, and the least significant bit is provided in the first step. Are arranged at predetermined positions of a central wiring layer, and the wirings for the four bits from the uppermost in the second step are arranged at the center, the upper side and the lower side so as to be located on the left and right sides and above and below the wiring of the least significant bit. In the third step, the unplaced wiring for the 6 bits from the lowest is placed in the lower and upper wiring layers so as to be located on the left, right, upper and lower sides of the wiring for the 4 bits from the top, and In the fourth step, the unplaced wiring for the 6 bits from the top in the fourth step is placed on both the left and right sides and above and below the wiring for the 4 bits from the bottom arranged in the third step. Center to be located Place the wiring layer of the upper and lower, then, and repeating the third step and the fourth step until the wiring of all bits are arranged.

A semiconductor integrated circuit according to a twelfth aspect of the present invention is a semiconductor integrated circuit in which a plurality of bits of wiring are wired in a plane or three-dimensionally and parallelly in ascending and descending order of bits, wherein the plurality of bits of wiring are provided. Among them, the wiring interval of the lower wirings below the predetermined bit is wider than the wiring interval of the upper wirings above the predetermined bit.

A semiconductor integrated circuit according to a thirteenth aspect of the present invention is a semiconductor integrated circuit in which a plurality of wirings are wired in a two-dimensional or three-dimensional manner and in parallel, wherein the plurality of wirings are signals transmitted through each wiring. Are not arranged in ascending or descending order of signal change frequency.

The invention according to claim 14 is the invention according to claim 13.
In the above-described semiconductor integrated circuit, the plurality of wirings are wirings of a plurality of bits, and the wirings of the plurality of bits are arranged in a line independent of an ascending or descending order of bits.

According to a fifteenth aspect of the present invention, the thirteenth aspect is provided.
In the described semiconductor integrated circuit, a wiring with a high signal change frequency is sandwiched between two wirings with a low signal change frequency.

The invention according to claim 16 is the invention according to claim 1.
15. The semiconductor integrated circuit according to 3, 14, or 15, wherein each of the plurality of wirings has a wiring width of 0.18 μm or less.

According to a seventeenth aspect, in the first aspect,
In the semiconductor integrated circuit described in 3, 14, 15, or 16, the plurality of wirings are a plurality of address buses.

[0027] The invention according to claim 18 is the invention according to claim 1.
In the semiconductor integrated circuit described in 3, 14, 15, or 16, each signal transmitted through the plurality of wirings is a digital image or sound signal.

A semiconductor integrated circuit according to a nineteenth aspect of the present invention provides a semiconductor integrated circuit which performs a predetermined process on a plurality of wirings, and outputs a signal of a result of the predetermined processing to each of the plurality of wirings. Disposed between the wiring and the processing circuit,
Switch means for changing the arrangement order of the signals output from the processing circuit so as not to be arranged in ascending or descending order of the signal change frequency of the signals, and transmitting the output signals in the changed order to the plurality of wirings. It is characterized by having.

The invention according to claim 20 is the invention according to claim 19.
5. The semiconductor integrated circuit according to claim 2, wherein the receiving circuit receives each signal transmitted to the plurality of wirings, and is disposed between the plurality of wirings and the receiving circuit, and each of the plurality of wirings is transmitted to the plurality of wirings. Another switch means for changing the arrangement order of the signals in the ascending or descending order of the signal change frequency of the signals, and transmitting each signal in the changed order to the receiving circuit.

According to a twenty-first aspect of the present invention, there is provided a function macro having a plurality of terminals to which a wiring of a plurality of bits is connected, wherein the plurality of terminals are arranged in ascending or descending order of bits. In addition, the mutual interval between the terminals of the upper bits of the plurality of terminals is set to a predetermined terminal interval, and the mutual interval of the terminals of the lower bits of the plurality of terminals is set to a terminal interval longer than the predetermined terminal interval. It is characterized by being set.

The function macro according to the present invention is a function macro having a plurality of terminals to which a wiring of a plurality of bits is connected, and the arrangement order of the plurality of terminals does not depend on the ascending order or the descending order of bits. , Is set based on the frequency of change of a signal input to or output from each terminal.

The invention according to claim 23 is the invention according to claim 22.
In the function macro described above, the plurality of terminals are arranged such that terminals having a high signal change frequency are interposed between terminals having a low signal change frequency.

The invention according to claim 24 is the invention according to claim 23.
In the function macro described above, terminals of higher-order bits of a predetermined bit or more are arranged at an interval of twice a predetermined interval in descending order from terminals of the most significant bit, and terminals of lower-order bits less than the predetermined bit are assigned terminals of the least significant bit. The terminal is arranged between terminals of the most significant bit and terminals of the high order bit in ascending order from the terminal.

According to a twenty-fifth aspect of the present invention, the twenty-third aspect
The described functional macro is characterized in that a predetermined 2-bit terminal continuous from the lowest side is arranged inside or outside a predetermined 2-bit terminal continuous from the highest side.

The invention according to claim 26 is the invention according to claim 25.
In the described function macro, two terminals of the most significant two bits are arranged at both ends, and two terminals of the least significant two bits are arranged inside the two terminals of the most significant two bits. Features.

The invention according to claim 27 is the invention according to claim 25.
In the described function macro, the terminal of the least significant bit is located at the center position of the plurality of terminals arranged.

A semiconductor integrated circuit according to a twenty-eighth aspect of the present invention is arranged such that a plurality of terminals are arranged in ascending or descending order of bits and a function macro in which the plurality of terminals are arranged in an ascending order based on a signal change frequency. And a terminal rearranging block for connecting the plurality of terminals of the function macro to the other terminals corresponding to the plurality of terminals.

According to the twenty-ninth aspect, the twenty-eighth aspect of the present invention is the twenty-eighth aspect.
In the semiconductor integrated circuit described in the above, the function macro, the plurality of other terminals, and the terminal rearrangement block,
It is characterized by being formed integrally.

According to a thirtieth aspect of the present invention, there is provided the method of the twenty-second aspect.
In the described function macro, the function macro is a memory, a computing unit, or a CPU.

According to a thirty-first aspect of the present invention, in the wiring method in layout design of a semiconductor integrated circuit, a plurality of terminals are connected to a plurality of terminals of the function macro according to the twenty-third aspect, and a signal among the plurality of lines is output. A wiring method in a layout design of a semiconductor integrated circuit, wherein a wiring for transmitting a signal with a high frequency of change is sandwiched between two wirings for transmitting a signal with a low frequency of signal change.

According to a thirty-second aspect of the present invention, a semiconductor integrated circuit includes two or more function macros according to the twenty-third aspect, and a plurality of wirings connecting a plurality of terminals of each of the function macros. Are characterized by the fact that a wire that propagates a signal with a high signal change frequency is sandwiched between two wires that propagate a signal with a low signal change frequency.

The invention according to claim 33 is the invention according to claim 32.
In the semiconductor integrated circuit described above, three or more function macros are provided, and the plurality of wirings are a plurality of bit address buses.

The invention according to claim 34 is the invention according to claim 32.
In the semiconductor integrated circuit described above, two function macros are provided, one of the function macros is an A / D converter, and the plurality of wirings are digital signals obtained by converting analog values into digital values by the A / D converter. Is a data signal wiring which propagates the data.

As described above, according to the first, twelfth, and twenty-first aspects of the present invention, when wiring a plurality of bits in the ascending or descending order of bits, the wiring between lower-order bits of less than a predetermined bit having a high signal change frequency is high. The wiring interval between these wirings is set wide, so that the wiring capacitance between these wirings becomes small, and the malfunction of the semiconductor integrated circuit caused by the increase in the delay due to the change in the reverse phase of the signal between these wirings is effectively prevented. Suppressed or eliminated. In addition, since the wiring interval between the upper bits of the predetermined bit or more is set to a normal wiring interval smaller than the widened wiring interval, the wiring interval between all the wirings is set to the wide wiring interval. In comparison, an increase in the area of the semiconductor integrated circuit can be effectively suppressed.

Further, claims 2 to 11 and claims 13 to 2
In the invention described in No. 0, when arranging a plurality of wirings, a wiring having a high signal change frequency and a wiring having a low signal change frequency are arranged so as not to be adjacent to each other. Wiring having a low change frequency has the same effect as the shield wiring, and the probability that the signals of the two wirings change in mutually opposite phases as much as possible is reduced. As a result, malfunctions in the operation of the semiconductor integrated circuit due to the opposite phase change of the signal between the wirings with a high signal change frequency are effectively suppressed or eliminated. In addition, since only the arrangement order of signals propagated through the plurality of wirings is changed, it is possible to prevent the area of the semiconductor integrated circuit from being unnecessarily increased.

In the invention according to claims 22 to 34,
Just by the automatic placement and routing tool grasping the order of each terminal of the function macro 50, the normal automatic routing by the automatic placement and routing tool automatically lower-order bit wiring and upper-order bit wiring in the order of the terminals. Layout can be arranged. Therefore, without requiring a design change of the automatic placement and routing tool, the wiring of the upper bits having a low frequency of signal changes functions as a shield line for the wiring of the lower bits having a high frequency of signal changes, and the area of the entire semiconductor integrated circuit is reduced. Thus, it is possible to effectively suppress an increase in signal propagation delay due to signal interference without causing unnecessary increase.

[0047]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, for some signals, the difference between the behavior of the upper bit signal and the lower bit signal will be examined.

Examples of the bus signal include (a) a completely random control bus, (b) an address bus for controlling the sequential processing of computer programs and data access,
Representative examples are (c) information obtained by converting an image and a sound into an analog signal, and (d) data obtained by digitally encoding a transition state in a sequential machine. Of these,
The buses that account for a large proportion are (b) and (c) above. In (b) and (c), a difference in signal change frequency between bits is clearly recognized. First, as for the address bus of (b), assuming that a program is processed by a computer, approximately 80 to 90% of instruction codes sequentially access consecutive addresses. An exception is a branch instruction, which also has a limited address range in which a program is stored, and does not access until the address range is exceeded. Address bus is 2
Because it is expressed in hexadecimal, continuous address change,
In the case of an address change with a limited range, the lower bits have a higher probability of a signal change. This can be proved mathematically.

Next, in the case of an image (composed of luminance, hue, etc.) and audio information (composed of frequency, volume, etc.), information that a human sees or hears on a TV or stereo is short ( The probability that an abrupt change in the analog value will occur during one clock time is low. This is because if it changes in a short time, it will not be recognized by human senses, but will be merely noise. Therefore, in the case of (c), the value changes within a very limited range, as in the case of the address bus of (b). Therefore, the lower bits have a higher probability of signal change.

In the cases (a) and (d), the change frequency of the signal is substantially the same for each bit, and is out of the scope of the present invention.

Therefore, in the first to eighth embodiments described below, it is desirable that the plurality of wirings be a plurality of address buses. Further, it is desirable that the signal propagating through these wirings is a digital signal of an image or a sound. Furthermore,
The width of each of the plurality of wirings is not particularly limited. Even if the width is wide, it is within the scope of the present invention.
When m is equal to or less than m, the effect of the present invention is remarkably exhibited, and unexpected design defects can be effectively suppressed.

FIG. 1 is an explanatory view showing a wiring method and a semiconductor integrated circuit according to a first embodiment of the present invention. In the figure, 10 (0) is the wiring of the lower bit of the 0th bit which is the least significant bit, 10 (1) is the wiring of the lower bit of the 1st bit, and 10 (2) is the wiring of the lower bit of the 2nd bit , 2
0 (k) is the wiring of the most significant bit of the k-th bit, 20 (k-1) is the wiring of the high-order bit of the (k-1) th bit, and 20 (k-2) is the (k-2) th bit The wirings of the upper bits of the eye are arranged in ascending order from the lowest 0th bit or in descending order from the most significant bit.

With respect to the plurality of (k) wires, the wires 20 (k), 20 (k-1)... Of the upper bits are arranged adjacent to each other with a predetermined wire interval Th, and
The wiring intervals between the lower bit wirings 10 (0), 10 (1),... Are set adjacent to each other with a distance interval Tl exceeding the predetermined wiring interval Th.

The number of wirings to be set as lower bits, in other words, the wiring of a predetermined bit at the boundary between the lower bit and the upper bit depends on the distribution of expected data (signal).
The wiring of the bit is selected such that the frequency of change of the signal becomes larger than a predetermined value. Here, the change frequency of the signal (the change rate of the signal per unit time of each wiring) is based on the statistical distribution of the signal propagating through each wiring, and the distribution of the value and the range of change of the value when one clock changes. And can also be determined by simulation.

In the present embodiment, the wiring capacitance between the wiring of the lower bits can be reduced, and the probability that the operation of the semiconductor integrated circuit becomes defective due to an increase in the delay due to the simultaneous reverse phase change of the signal is reduced. be able to.

Further, if the wiring intervals of all the wirings are widened as in the prior art, the degree of increase in the area for wiring becomes large, but in this embodiment, the frequency of signal change is high. Since the wiring interval of only the lower bit wiring is widened, the increase in the area of the semiconductor integrated circuit can be suppressed.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. In this embodiment, the wiring is arranged so that the lower bit wiring 10 having a large value of the signal change frequency is sandwiched by the upper bit wiring 20 having a small value of the signal change frequency.

Therefore, in the present embodiment, the upper-bit wiring 20 with a lower signal change frequency acts as a shield against the lower-bit wiring 10 with a higher signal change frequency, and the delay in signal propagation can be increased as much as possible. It is possible to reduce.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. In the present embodiment, wirings 10 (0) of the lower bits of the 0th bit, the 1st bit, the 2nd bit,.
.. Are wired two-dimensionally and in parallel in ascending order at a wiring interval twice as large as a predetermined wiring interval. .. in the descending order of the upper bit wirings 20 (n), 20 (n-1), 20 (n-2). Position in a plane and parallel.

Therefore, in the present embodiment, the lower bit wirings 10 (0), 10 (1)... With less signal change frequency are replaced with the upper bit wirings 20 (n), 20 (n−
1) are sandwiched by the lower bit wirings 10 (0), 10 (1).
0 (n), 20 (n-1)... Function as a shield, and as a result, an increase in signal propagation delay can be minimized.

In this embodiment, the wiring of the lower bit is arranged first, and then the wiring of the upper bit is arranged between the wirings. However, the wiring of the upper bit is arranged first. Then, of course, lower-order bit wiring may be arranged between these wirings.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. In this embodiment, in FIG. 4, first, the wiring 10 (0) of the 0th bit of the least significant bit is arranged at a predetermined position such as the center position. Next, wirings 20 (n) and 20 (n-1) of the n-th bit and the (n-1) -th bit of the most significant bit are provided at a predetermined wiring interval on the right and left sides of the wiring 10 (0) of the 0th bit. Deploy. Furthermore, at the left and right sides of the upper bit wirings 20 (n) and 20 (n-1),
The first and second bit wirings 10 (1) and 10 (2) for the 2 bits from the least significant bit which are not arranged are arranged at a predetermined wiring interval. Thereafter, the lower bit wiring 10
At positions on both the left and right sides of (1) and 10 (2), the wirings 20 (n-2) and 20 (n-2) of the n-2th and n-3th bits of 2 bits from the most significant bit which are not arranged yet -3) are arranged at a predetermined wiring interval, and subsequently, the arranged upper bit wiring 20 (n
-2), wirings 10 (3) and 10 (4) of the third and fourth bits for the 2 bits from the least significant bit, which are not arranged, are located at the left and right sides of 20 (n-3). Arrange at wiring intervals. In the same manner, until wiring of all bits is completed,
The arrangement of the unarranged and uppermost two-bit wiring and the arrangement of the unarranged and lowermost two-bit wiring are sequentially repeated.

Therefore, also in the present embodiment, as in the third embodiment, the wiring of the lower bits having a high signal change frequency is sandwiched by the wiring of the upper bits having a low signal change frequency. The upper bit wiring serves as a shield for the bit wiring, and an increase in signal propagation delay can be reduced as much as possible.

(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. In the present embodiment, a case where wirings are arranged three-dimensionally and in parallel using two wiring layers will be described.

In the figure, first, the least significant bit wiring 1
0 (0) is arranged at a predetermined position such as the center position in the lower first wiring layer. Thereafter, the uppermost layer (second wiring layer) is located at a position directly above the least significant bit wiring 10 (0) and on both left and right sides of the least significant bit wiring 10 (0) from the most significant side. N-th bit for 3 bits of
The wiring 20 (n) of the (n−1) th bit and the (n−2) th bit,
20 (n-1) and 20 (n-2) are arranged. Subsequently, the uppermost wiring 20 disposed in the first and second wiring layers
On the left and right sides of (n), 20 (n-1) and 20 (n-2), wirings 10 (1) to 10 (4 ) Are arranged in the first and second wiring layers. Similarly, the lowermost wiring line 10
On the left and right sides of (1) to (4), the wiring 20 (n-
3) to 20 (n-6) are arranged in the first and second wiring layers.
In the same manner, the arrangement of the unplaced and uppermost 4-bit wiring and the unplaced and lowermost 4-bit wiring are sequentially repeated until the wiring of all the bits is arranged.

Therefore, also in the present embodiment, the wiring of the upper bits having a low frequency of signal change acts as a shield against the wiring of the lower bits having a high frequency of signal change, so that the delay of signal propagation is minimized. It is possible to reduce.

(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. The difference between this embodiment and the fifth embodiment is that in the fifth embodiment, the least significant bit wiring 10 (0) is first arranged in the first wiring layer. Is that the least significant bit wiring 10 (0) is arranged in the second wiring layer. The other wiring methods are the same as in the fifth embodiment, and a description thereof will be omitted. In this embodiment, the same operation and effect as those of the fifth embodiment can be obtained.

(Seventh Embodiment) FIG. 7 shows a seventh embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a wiring method and a semiconductor integrated circuit according to an embodiment. In the present embodiment, a case will be described in which wiring is three-dimensionally arranged in parallel using three wiring layers.

In the figure, first, the wiring 10 (0) of the 0th bit, which is the least significant bit, is arranged at a predetermined position such as the center position of the second wiring layer of the central layer. Next, the n-th bit wiring 20 (n), which is the most significant bit, is disposed at the position of the first wiring layer located immediately below the 0th bit wiring 10 (0), and the n-th bit wiring 20 (n) located immediately above the The wiring 20 (n-1) of the (n-1) th bit is arranged at the position of the third wiring layer, and
At the positions of the second wiring layer on the left and right sides of the bit wiring 10 (0), the wiring 20 (n-
2), 20 (n-3) are arranged.

Subsequently, the first 6 bits of the lower bits which are not arranged on the left and right sides of the upper bit side wirings 20 (n) to 20 (n-3) arranged in the first to third wiring layers. The wirings 10 (1) to 10 (6) of the sixth to sixth bits are arranged in the first to third wiring layers. Similarly, on the left and right sides of the arranged lower-bit-side six wires 10 (1) to 10 (6), the n-4th to n-9th bits of the 6-bit unarranged upper-bit side are similarly set. The second wirings 20 (n-4) to 20 (n-9) are arranged in the first to third wiring layers, and thereafter, until the wirings of all the bits are arranged.
The arrangement of the unarranged and upper 6-bit wiring and the arrangement of the unarranged and lower 6 bit wiring are sequentially repeated so as to surround the periphery.

Therefore, in the present embodiment, as in the fifth embodiment, even when the number of wiring layers is three, the wiring of the lower bits with a high signal change frequency is replaced with the signal with a low signal change frequency. Since the upper bit wiring can serve as a shield as a structure sandwiched by the upper bit wiring, an increase in signal propagation delay can be reduced as much as possible.

The wiring method in the case where the number of wiring layers is two or three has been described above.
It is needless to say that the same can be applied to the case where the wiring is arranged three-dimensionally and in parallel in the wiring layer (n ≧ 4). That is, after first arranging the wiring of the 0th bit of the least significant bit in the wiring layer located at the upper and lower middle position of the n wiring layers,
Wiring for 4 bits on the upper bit side is arranged in the wiring layers on the upper, lower, left and right positions, and then, on the upper, lower, left and right wiring layers of the four wirings on the upper bit side, 6 bits for the lower bit side The present invention also includes a method of repeating the wiring arrangement to complete the wiring arrangement of all the bits.

(Eighth Embodiment) FIG. 8 shows an eighth embodiment of the present invention.
1 is a configuration diagram of a semiconductor integrated circuit according to an embodiment.

In the semiconductor integrated circuit shown in FIG.
Reference numeral 00 denotes an arithmetic unit (processing circuit) that performs an operation as a predetermined process, 101 denotes a plurality of (four in the figure) bus wirings,
A switch circuit (switch means) 02 is disposed between the arithmetic unit 100 and one end of the bus line 101.

The 4-bit operation result obtained by the operation unit 100 is output to four bus lines 101 via the switch circuit 102. The switch circuit 102 changes the arrangement order of the 4-bit operation result signals of the operation unit 100 so that they are not arranged in the ascending or descending order of the signal change frequency of the operation result signals, and the changed signal change frequency is large. The operation result signals in which the bus lines are not arranged next to each other are transmitted to the bus lines 101. This switch circuit 102
Are as described in the second to seventh embodiments.

The operation result signal propagated to the other end of the bus line 101 is received by another operation unit (reception circuit) 104 via another switch circuit (other switch means) 103 and is taken in. , Is used for the operation in the arithmetic unit 104. The other switch circuit 103 includes a bus wiring 10
The order of the 4-bit operation result signal propagating 1 is
The arithmetic unit 100 changes the ascending or descending order of the signal change frequency, which is the arrangement order of the 4-bit output signals, and transmits the arithmetic result signal in the changed order to the arithmetic unit 104.

Therefore, in this embodiment, the bus wiring 10
Since the arrangement order of the signals propagating 1 is changed by the switch circuit 102, there is no need to change the configuration of the bus wiring 101 itself, and the same bus wiring 101 as the conventional one can be used. Moreover, the signals transmitted through the bus wiring 101 are returned to the original order by another switch circuit 103,
Since the other arithmetic units 104 take in the normal bit arrangement order, the arithmetic unit 104 can perform the intended operation.

(Ninth Embodiment) FIG. 9 shows a ninth embodiment of the present invention.
3 shows a function macro according to the embodiment. In the present embodiment,
The arrangement order of the plurality of terminals of the function macro connected to these wirings is set and arranged so as to match the arrangement order of the plurality of wirings described above.

That is, in FIG. 9, as in the second embodiment, the lower bits are arranged based on the signal change frequency so that the lower wirings 10 are sandwiched by the upper wirings 20. In some cases, CPU, SR
A plurality of terminals 50 (h) to 50 (l) of a function macro 50 constituting an AM or a computing unit are connected to the plurality of wirings 10, 2
The terminals 50 (l) connected to the lower bit wiring 10 are arranged in advance so as to be located between the terminals 50 (h) connected to the upper bit wiring 20 in correspondence with the order of 0s. It is something to keep. The function macro 50 is a new function macro having no terminals arranged in ascending or descending order of bits as in the related art. Terminal 50 of this function macro 50
(H), in addition to the case where the mutual intervals of 50 (l) are equal,
The intervals may be set to be different from each other, and both cases are included in the present invention. This is the same in the following tenth and subsequent embodiments.

Therefore, in the present embodiment, when the layout structure in which the plurality of lower bit wirings 10 with a large signal change are sandwiched between the plurality of upper bit wirings 20 with a small signal change is to be employed, each of the function macros 50 Terminal 50
(H) and 50 (l) are set and arranged in advance based on the frequency of signal change corresponding to the arrangement order of the wirings 10 and 20.
When the arrangement order of the terminals 50 (h) and 50 (l) is grasped, the automatic placement and routing tool automatically arranges the lower bit wiring 10 and the upper bit wiring 20 in the above arrangement order. It is not necessary to change the design of the automatic placement and routing tool.

(Tenth Embodiment) Next, a function macro according to a tenth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the arrangement order of a plurality of wirings and the arrangement order of a plurality of terminals of a function macro are specifically specified.

That is, in FIG. 10 showing the function macro of this embodiment, the uppermost bit wiring 20 (n) of the n-th bit, the (n-1) th bit, the (n-2) th bit,.
20 (n-1), 20 (n-2)... Are arranged in a descending order from the top at a wiring interval twice as large as a normal wiring interval.
The wirings 10 (0), 10 (1), 10 (2)... Of the lower bits of the lowest 0th bit, the first bit, the second bit... ), 2
0 (n-1)...

Further, in the function macro 50, the wiring 1
The n-th bit, the 0-th bit, the (n-1) -th bit, the first bit, and the n-th bit correspond to the arrangement order of 0 and 20 in order from the top in the figure.
.., That is, a plurality of terminals 50t (n), 50t (0), and 50t (n−n) in an order in which the lower terminal is interposed between the upper two bits.
1), 50t (1), 50t (n-2), 50t (2)
... are arranged.

Therefore, in this embodiment, as in the ninth embodiment, the lower and upper bit wirings 10 and 10 can be arranged without changing the design of the automatic placement and routing tool.
20 can be automatically arranged and arranged in the above-mentioned arrangement order other than the ascending order or the descending order.

(Eleventh Embodiment) Next, a function macro according to an eleventh embodiment of the present invention will be described with reference to FIG. In the present embodiment, the arrangement order of the plurality of terminals of the function macro is changed so as to be different from that of the tenth embodiment.

That is, in FIG. 11, the upper two bits are:
That is, the wiring 20 (n) of the n-th bit and the (n-1) -th bit,
20 (n-1) are arranged at the outermost ends, and wirings 10 (0) and 10 (1) of the 0th and 1st bits, which are the two least significant bits, are arranged inside the outermost ends. The n-2th bit and the n-3th bit which are not arranged on the upper side further inside
Bit wirings 20 (n-2) and 20 (n-3) are arranged. In this manner, the arrangement of the upper bit wiring and the lower bit wiring alternately inside is repeated, and n +
All one wiring is arranged.

In the function macro 50, the n-th bit, the 0-th bit, and the
Bit, the (n-2) th bit ... terminals 50t (n), 50t
(0), 50t (n-2)... Are arranged, and from the bottom in the figure,
The terminals 50t (n-1), 50t (1), 50t (n-3) of the (n-1) th bit, the first bit, the (n-3) th bit ...
Are lined up. In such an arrangement order of the terminals, for example, the terminal 50 of the n-th bit and the (n-1) th bit which is continuous from the most significant side
Inside the t (n) and 50t (n-1), terminals 50t (0) of the 0th bit and the 1st bit continuous from the least significant side,
50t (1) are arranged, and terminals 50t of, for example, the (n-2) th bit and the (n-3) th bit which are continuous from the most significant side
(N−2), 50t (n−3), terminals 50t of the 0th bit and the 1st bit continuous from the lowest side
(0) and 50t (1) are arranged.

As described above, in the present embodiment, as in the tenth embodiment, wiring of lower and upper bits 10 and 20 can be performed without changing the design of the automatic placement and routing tool.
Can be automatically laid out in the order described above, which is not the ascending order or the descending order.

(Twelfth Embodiment) FIG. 12 shows a function macro according to a twelfth embodiment of the present invention.

In this embodiment, as shown in FIG.
The wiring 10 (0) of the 0th bit which is the least significant bit is arranged at the center position, and the nth bit and the nth bit which are 2 bits from the most significant bit are located outside the wiring 10 (0) so as to sandwich the wiring 10 (0). -1 bit wiring 20 (n), 20 (n-
1) is arranged. Further, the first and second bit wirings 10 of lower bits are not arranged outside these two wirings.
(1), 10 (2) are arranged, and thereafter, alternately arranging two wirings of the upper bit and two wirings of the lower bit outside in this manner is repeated, so that all the wirings are arranged in rows. We can.

When a plurality of wirings are to be laid out in the above-described order, the function macro 50 is used. In the function macro 50, the terminal 50t of the 0th bit, the nth bit, the 1st bit, the (n-2) th bit,... 0), 50t (n), 50t
(1), 50t (n−2) are arranged, and the (n−1) th bit, the second bit, the n−th bit from the center position downward in the figure.
3 bits ... terminals 50t (n-1), 50t (2), 5
0t (n-3) is arranged.

As described above, in the present embodiment, the terminals 50t (n) to 50t (0) are similar to the eleventh embodiment.
When the function macros arranged in the order based on the signal change frequency are used, the wirings 10 and 20 of the lower and upper bits are not arranged in the ascending order or the descending order without the need for a design change of the automatic arrangement and wiring tool. It is possible to automatically arrange the layout.

(Thirteenth Embodiment) Next, a function macro according to a thirteenth embodiment of the present invention will be described with reference to FIG.

In FIG. 13A, the existing function macro 51
, A terminal rearrangement block 52 for changing the terminal arrangement order is arranged adjacently. The existing function macro 51 is an SRAM, an arithmetic unit, a CPU, or the like, and has a plurality of terminals (not shown) arranged in ascending (or descending) bit order.

In the present embodiment, the wiring arrangement order is the same as in the tenth embodiment. That is, the top n-th
, 20 (n−1), 20 (n−1), 20 (n−2) for the upper bits of the bit, the (n−1) th bit, the (n−2) th bit,...
Are arranged in a descending order from above in the drawing at a wiring interval twice as large as a normal wiring interval, and wirings 10 (0), 10 (0), 10 (0), 10
(1), 10 (2)... Are arranged between the upper bit wirings 20 (n), 20 (n−1).

Then, the terminal rearrangement block 52
Is formed so that its width (the length in the direction in which the wirings 20 (n) to 10 (0) are arranged) is the same as that of the function macro 51,
As shown in detail in FIG. 4B, the n-th most significant bit,
New pluralities of terminals (other terminals) 52t (n), 52t arranged in the order of least significant 0th bit, n-1th bit, 1st bit, n-2th bit, 2nd bit,.
(0), 52t (n-1), 52t (1), 52t (n
-2), 52t (2) ...

Further, the terminal rearranging block 52 includes a plurality of wirings 52a extending in the horizontal direction in the drawing and arranged on the first metal wiring layer (aluminum layer) and a second metal extending in the vertical direction in the drawing. A plurality of wirings 52 arranged on a wiring layer (aluminum layer)
b, connecting the first wiring layer and the second wiring layer to each other.
a and a plurality of vias 52c connecting the wiring 52a to the wiring 52b. These wirings 52a, 52b and via 52
c, the terminals (not shown) in the ascending or descending order of the bits arranged in the first layer of the existing function macro 51 are connected to the terminals 52 t (n) to 52 t of the terminal rearranging block 52.
Connected to (0), the arrangement order of the terminals is changed. The terminal rearranging block 52 including the terminals 52t (n) to 52t (0) and the function macro 51 are formed integrally.

The width of the terminal rearranging block 52 may be shorter or longer than the width of the function macro 51. Further, a plurality of terminals 52t (n) to 52t (0)
However, these terminals are not included, and the wiring 52 is formed.
a, 52b and via 52c alone. Further, when no terminal is included, the arrangement position of the terminal rearrangement block is determined by the function macro 51 and the terminals 52t (n) to 52t (n).
It is desirable to arrange it between t (0), but it is not limited to this arrangement position.

Therefore, in the present embodiment, even in the case of the existing function macro 51, only by arranging the terminal rearrangement block 52 on the side thereof, the terminal arrangement order is changed as desired in FIG. 12 can be arranged in the same order as the function macro 50 of FIG. Therefore, the automatic placement and routing tool executes each terminal 52 (n) to 52 (52) of the terminal rearranging block 52.
If the arrangement order of (0) is grasped, a plurality of wirings 20 (n) to 10 (0) can be automatically arranged and arranged in a predetermined arrangement order by the automatic arrangement and wiring tool.
This has the effect of not requiring a change in the design of the automatic placement and routing tool.

Although the tenth embodiment has been described by exemplifying the arrangement order of the wirings and terminals in the tenth embodiment, the wirings and terminals in the ninth, eleventh, or twelfth embodiments are described. Even if the present invention is applied to a device adopting the arrangement order, it is needless to say that the same operation and effect can be obtained.

In the present embodiment, the terminal rearrangement block 52 is provided for the existing function macro 51.
When a function macro is newly designed, the terminal rearrangement block 52 may be designed to be arranged in the function macro. In this case, the position of the terminal rearrangement block 52 may be any position in the function macro.

(Fourteenth Embodiment) Next, a semiconductor integrated circuit according to a fourteenth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the mutual intervals of a plurality of terminals included in the function macro are set to be different but not equal.

In FIG. 14, 10 (0) to 20 (k)
Are wirings in the ascending order from the least significant bit wiring 10 (0) (or the descending order from the most significant bit wiring 20 (k)), similarly to the arrangement order in FIG. 1 showing the first embodiment. Are arranged in this order, and the wirings 20 (k) and 20 (k-
1)... Are set at a predetermined wiring interval Th, and between the lower bit wirings 10 (0), 10 (1)..., The wiring interval is set at a distance Tl longer than the predetermined wiring interval Th. You.

The wirings 10 (0) to 2 (0) to 2
To place 0 (k), the function macro 53
Is adopted. The function macro 53 has terminals 53 (0) to 53 (k) to which the wirings are connected, and these terminals 53 (0) to 53 (k) are arranged in ascending order from the bottom in the drawing (or in the drawing). (From top to bottom). Terminals 53 to which the lower bit wirings 10 (0), 10 (1),.
(0), 53 (1)... Are equal to the long wiring interval Tl, and the upper bit wirings 20 (k), 20 (k)
-1) are connected to terminals 53 (k), 53 (k-1)
Are equal to the predetermined wiring interval Th.

Therefore, according to the present embodiment, the automatic placement and routing tool uses the terminals 53 (0) to 53 (53) of the function macro 53.
When the arrangement position of (k) is grasped, the wiring 10 arranged in the ascending order (or the descending order) can be obtained by the automatic arrangement and wiring tool.
(0) to 20 (k) can be automatically laid out at the above-mentioned wiring intervals Tl and Th, and there is no need to change the design of the automatic placement and routing tool.

(Fifteenth Embodiment) Next, a semiconductor integrated circuit according to a fifteenth embodiment of the present invention will be described with reference to FIG.

The semiconductor integrated circuit shown in the figure is a microprocessor, a CPU 60, a DMA controller 61 for transferring data without the intervention of the CPU 60, a RA,
M (memory) 62, ROM (memory) 63, multi-bit address bus 64, and multi-bit data bus 65
Is provided. The address bus 64 and the data bus 65 are used to transfer data between the CPU 60 and the RAM 62 or the ROM 63, and to transfer data between the DMA controller 61 and the RAM 62.
Alternatively, it is used for data transfer with the ROM 63.

In this embodiment, the CPU 60 and the DM
9 is applied to the A controller 61, the RAM 62, and the ROM 63, respectively. That is, the CPU 60 and the DMA controller 6
1, the order of the plurality of address terminals of the RAM 62 and the ROM 63 is set in the order of the terminals 50 (h) and 50 (l) of the function macro 50 shown in FIG. It should be noted that the order of the terminals 50 (h) and 50 (l) of the function macro 50 in FIG. 9 is not limited, and the terminals 50t (n) to 50t (0) of the function macro 50 shown in FIG. 10, FIG. 11 or FIG. And the terminal 5 of the terminal rearranging block 52 shown in FIG.
An arrangement order of 2t (n) to 50t (0) may be adopted.

Therefore, the present embodiment has the following operations. That is, access from the CPU 60 or the DMA controller 61 to the RAM 62 or the ROM 63 is often made to continuous addresses.
In No. 4, the frequency of change is higher for the lower bits compared to the upper bits. Therefore, in the CPU 60, the DMA controller 61, the RAM 62, and the ROM 63 to which the arrangement order of the terminals of the function macro 50 of FIG.
4 has a structure in which the lower-bit bus with a large signal change is sandwiched between the upper-bit buses with a small signal change, and the upper-bit bus serves as a shield. It is possible to effectively suppress an increase in signal propagation delay due to interference of the signals.

Further, an automatic placement and routing tool is provided for the CPU 60,
If the order of arrangement of each address terminal of the DMA controller 61, the RAM 62 and the ROM 63 is grasped, the arrangement order of the address bus 64 can be changed by the automatic placement and routing tool.
The layout can be automatically arranged in the arrangement order of the address terminals such as U60, so that the design change of the automatic arrangement and wiring tool is not required.

(Sixteenth Embodiment) Next, a semiconductor integrated circuit according to a sixteenth embodiment of the present invention will be described with reference to FIG.

The semiconductor integrated circuit shown in FIG. 16 converts audio information such as music into MP3 (MPEG-1 Audio La).
yer III) shows a part of a circuit that stores data in a format. In the figure, audio information that is an analog signal is converted into a digital signal by an A / D converter 70. The converted digital signal is supplied to a data signal wiring 71 of plural bits.
, And is input to the data compression circuit 72. The data compression circuit 72 compresses the received digital signal in the MP3 format.

In the present embodiment, the data signal wiring 7
1 are connected to a plurality of data output terminals of an A / D converter 70 connected to the data macro circuit 72 and a data input terminal of a data compression circuit 72 connected to the data signal wiring 71, for example, to the terminal 50 of the function macro 50 shown in FIG. h), the order of 50 (l) is applied. The arrangement order of the wirings 10 and 20 in FIG. 9 is applied to the arrangement order of the data signal wirings 71 of a plurality of bits, for example.

Since the digital signal of a plurality of bits on the data signal line 71 maintains the continuity of the analog signal before being digitally converted by the A / D converter 70, the signal of the lower bit is the signal of the upper bit. More frequently than the change. However, in the present embodiment, the arrangement order of the data signal wiring 71 of a plurality of bits is the same as the wirings 10 and 20 shown in FIG.
The order is such that the data signal wiring of the lower bit having a higher signal change frequency is sandwiched by the data signal wiring of the upper bit having a lower signal change probability. Data signal wiring serves as a shield. Therefore, an increase in delay of signal propagation on data signal wiring 71 is effectively limited.

Furthermore, the arrangement order of the plurality of terminals of the A / D converter 70 and the data compression circuit 72 is arranged so as to match the arrangement order of the data signal lines 71 in advance.
If the arrangement order of the terminals is stored in the automatic placement and routing tool, the automatic placement and routing tool enables the data signal wiring 71 to be automatically laid out in the above-mentioned arrangement order. No design change is required.

The order of the terminals of the A / D converter 70 and the data compression circuit 72 is shown in FIGS.
Terminals 50t (n) to 50t of the function macro 50 shown in FIG.
The order of (0) may be applied, or the order of terminals 52t (n) to 52t (0) of the terminal rearrangement block 52 in FIG. 13 may be applied. Further, the arrangement order of the data signal wirings 71 also depends on the wirings 20 (n) to 20 (n) shown in FIGS.
An arrangement order of 10 (0) may be applied.

In the fifteenth embodiment, the present invention is applied in the order in which the address buses 64 are arranged. In the sixteenth embodiment, the present invention is applied in the order in which the data signal lines 71 are arranged.
When there are a plurality of wirings other than the bus 64 or the signal wiring 71, among the wirings, the wiring having a low signal change frequency is replaced by the lower bit address bus 64 or the lower bit data signal wiring having the higher signal change frequency. Arrangement between the 71s is also included in the present invention.

[0119]

As described above, according to the first, twelfth, and twenty-first aspects of the present invention, when wiring a plurality of bits in ascending or descending order of bits, a predetermined bit having a high signal change frequency is used. Since the wiring spacing between the wiring of the lower bits less than is set wider than the wiring spacing of the predetermined bit or more,
To effectively suppress or eliminate a malfunction of a semiconductor integrated circuit caused by an increase in delay due to a reverse phase change of a signal between wirings having a high signal change frequency, while effectively suppressing an increase in the area of the semiconductor integrated circuit. Can be.

Further, claims 2 to 11 and claims 13 to 2
According to the invention described in Item No. 0, when arranging a plurality of wirings,
Wiring with a low signal change frequency has the same effect as shield wiring without unnecessarily increasing the area of the semiconductor integrated circuit because wiring with a high signal change frequency and wiring with a low signal change frequency are arranged so as not to be adjacent to each other. Accordingly, it is possible to effectively suppress or eliminate the malfunction of the operation of the semiconductor integrated circuit due to the reverse phase change of the signal between the wirings having a high signal change frequency.

Further, according to the inventions of claims 22 to 34, there is no need to change the design of the automatic placement and routing tool.
By the normal automatic wiring by the automatic arrangement and wiring tool, there is an effect that the wiring of the lower bits and the wiring of the upper bits can be automatically laid out in the arrangement order of the terminals of the functional macro.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a wiring method and a semiconductor integrated circuit according to a seventh embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a semiconductor integrated circuit according to an eighth embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of a function macro according to a ninth embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a function macro according to a tenth embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of a function macro according to an eleventh embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of a function macro according to a twelfth embodiment of the present invention.

FIG. 13A is a diagram showing a configuration of a function macro according to a thirteenth embodiment of the present invention, and FIG. 13B is an enlarged view showing details of a terminal rearrangement block arranged in parallel with the function macro; FIG.

FIG. 14 is a diagram illustrating a configuration of a function macro according to a fourteenth embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a semiconductor integrated circuit according to a fifteenth embodiment of the present invention.

FIG. 16 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a sixteenth embodiment of the present invention;

FIG. 17 is an explanatory diagram of a conventional wiring method.

FIG. 18 is an explanatory diagram of a capacitance between wirings.

FIG. 19 is a diagram showing a configuration of a conventional function macro.

[Explanation of symbols]

1, 2 wiring 3 inter-wiring capacitance 10 lower bit wiring with high signal change frequency 10 (0) 0th bit wiring 10 (1) 1st bit wiring 10 (2) 2nd bit wiring 10 (3 ) Third Bit Wiring 10 (4) Fourth Bit Wiring 10 (5) Fifth Bit Wiring 10 (6) Sixth Bit Wiring 20 Upper Bit Wiring with Less Frequency of Signal Change 20 (n) Wiring of the nth bit 20 (n-1) Wiring of the n-1th bit 20 (n-2) Wiring of the n-2nd bit 20 (n-3) Wiring of the n-3th bit 20 ( n-4) Wiring of the n-4th bit 20 (n-5) Wiring of the n-5th bit 20 (n-6) Wiring of the n-6th bit 20 (n-7) n-7 Wiring of the bit 20 (n-8) Wiring of the n-8th bit 20 (n-9) Wiring of the n-9th bit 50, 51, 53 Function macro 50 (h), 0 (l) terminal 50t (n) to 50t (0) terminal 51t (n) to 51t (0) terminal 52 terminal rearranging block 52a wiring of the first wiring layer 52b wiring of the second wiring layer 52c via 52t (n) to 52t (0) terminal (other terminal) 60 CPU 61 DMA 62 RAM (memory) 63 ROM (memory) 64 address bus 65 data bus 70 A / D converter 71 data signal wiring 72 data compression circuit 100 arithmetic unit (processing circuit) DESCRIPTION OF SYMBOLS 101 Bus wiring 102 Switch circuit (switch means) 103 Other switch circuit (other switch means) 104 Other arithmetic unit (reception circuit)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/41 H01L 21/82 W 5J022 H01L 21/3205 C 21/822 27/04 D 27/04 21 / 88 Z H03M 1/12 G11C 11/34 345 F term (reference) 5B015 HH01 HH03 JJ14 PP05 5B046 AA08 BA05 5F033 UU03 UU04 UU05 VV16 XX24 XX27 5F038 BH10 BH19 CA17 CD05 CD07 CD09 CD13 DF03 EZ04 DF04 DF03 DF04 DF04 DF04 DF04 DF04 EZ04 BB16 DD02 DD24 DD25 EE02 EE19 EE23 EE26 EE43 EE47 EE51 EE60 FF36 HH06 HH09 5J022 AA01 BA02 BA06 CD02 CG01

Claims (34)

[Claims] In a layout design of a semiconductor integrated circuit, there is provided a wiring method for wiring a plurality of bits in a plane or in a three-dimensional manner and in parallel, wherein the plurality of bits are wired in ascending or descending order of bits. Wiring of upper bits of a predetermined bit or more is arranged adjacent to each other at a predetermined interval, and wiring of lower bits less than the predetermined bit is arranged adjacent to each other at an interval exceeding the predetermined interval. A wiring method in layout design of a semiconductor integrated circuit. 2. A wiring method for wiring a plurality of wirings in a plane or three-dimensionally and in parallel in a layout design of a semiconductor integrated circuit, wherein a signal propagating through its own wiring to each of the plurality of wirings. Estimating or simulating the signal change frequency per unit time of the plurality of wirings based on the signal change frequency of each of the wirings so that a wiring having a high signal change frequency and a wiring having a low signal change frequency are not adjacent to each other. A wiring method in a layout design of a semiconductor integrated circuit, comprising: 3. The arrangement of the plurality of wirings is performed based on the signal change frequency of each wiring regardless of the ascending or descending order of bits when transmitting a signal of a plurality of bits through the plurality of wirings. 3. A wiring method in layout design of a semiconductor integrated circuit according to claim 2. 4. The layout design of a semiconductor integrated circuit according to claim 2, wherein the plurality of wirings are arranged such that a wiring having a high signal change frequency is sandwiched between wirings having a low signal change frequency. Wiring method. 5. A wiring method for wiring a plurality of bits in a plane or three-dimensionally and in parallel in a layout design of a semiconductor integrated circuit. Repeatingly arranging a book wiring and a wiring less than the predetermined bit adjacent to each other, and arranging another wiring equal to or more than the predetermined bit and another wiring less than the predetermined bit adjacent to each other. A wiring method in layout design of a semiconductor integrated circuit. 6. Wiring is arranged in parallel from a most significant bit to a predetermined bit at a wiring interval twice as large as a predetermined wiring interval in a descending order from a most significant bit, and between the arranged wirings, in ascending order from the least significant bit. 6. The wiring according to claim 5, wherein the wiring is arranged in a plane and in parallel.
The wiring method in the layout design of the semiconductor integrated circuit described in the above. 7. A first step of arranging wiring of the least significant bit at a predetermined position, and a second step of arranging wiring of two bits from the most significant bit at positions on the left and right sides of the least significant bit wiring. A third step of arranging the unplaced wiring of 2 bits from the least significant side at the left and right sides of the wiring of 2 bits from the most significant side arranged in the second step; A fourth step of arranging the unarranged wiring for the bits at the left and right sides of the wiring for the two bits from the lowest side arranged in the third step; and the third and fourth steps are performed for all bits. 6. A wiring method in layout design of a semiconductor integrated circuit according to claim 5, further comprising: a fifth step of repeating until wiring is arranged. 8. A wiring method for wiring a plurality of bits in a three-dimensional and parallel manner using n (n.gtoreq.2) wiring layers in a layout design of a semiconductor integrated circuit. A first step of arranging in a predetermined wiring layer, and wiring of a plurality of bits from the highest order in the same layer as the least significant bit wiring so as to surround the least significant bit wiring arranged in the first step. A second step of arranging in the wiring layer and the other wiring layer, the unplaced wiring for a plurality of bits from the lowest order, so as to surround the wiring for the plurality of bits from the highest order arranged in the second step, A third step of disposing in the same wiring layer and another wiring layer as the wiring for a plurality of bits from the highest order, and a fourth step of repeating the second and third steps until the wiring of all bits is disposed. Of a semiconductor integrated circuit characterized by having Wiring method in the layouts design. 9. The n-layer wiring layer is a two-layer wiring layer, wherein the wiring of the least significant bit is arranged at a predetermined position on a lower layer in the first step, Wiring for bits,
The lowermost and uppermost wiring layers are arranged on the lower and upper wiring layers so as to be located on the left and right sides and above the lowermost bit wiring. The second and third steps are arranged in the lower and upper wiring layers so as to be located on the left and right sides of the wiring for bits, and the second and third steps are repeated in the fourth step until the wiring for all bits is arranged. 9. A wiring method in layout design of a semiconductor integrated circuit according to claim 8. 10. The n-layer wiring layer is a two-layer wiring layer, wherein a wiring of the least significant bit is arranged at a predetermined position in an upper layer in the first step, and three bits from a most significant bit are arranged in the second step. Minute wiring,
The uppermost and lowermost wiring layers are arranged on the upper and lower wiring layers so as to be located on the left, right, left and lower sides of the least significant bit wiring, and the unplaced wiring for 4 bits from the least significant bit in the third step is replaced by 3 It is arranged on the upper and lower wiring layers so as to be located on the left and right sides of the wiring for bits, and the second and third steps are repeated in the fourth step until wiring for all bits is arranged. 9. A wiring method in layout design of a semiconductor integrated circuit according to claim 8. 11. The n-layered wiring layer is a three-layered wiring layer, wherein a wiring of the least significant bit is arranged at a predetermined position in a central wiring layer in the first step, Wiring for bits,
And disposing them in the center, upper and lower wiring layers so as to be located on the left, right, right and left sides and above and below the least significant bit wiring; The middle, upper and lower wiring layers are arranged on the left and right sides and upper and lower sides of the wiring for the upper 4 bits, and the unarranged wiring for the upper 6 bits is arranged in the fourth step. Arranged in the center, upper and lower wiring layers so as to be located on the left and right sides and upper and lower sides of the wiring for 4 bits from the lowest order arranged in the third step, and thereafter, the third and fourth steps are entirely performed. 9. The wiring method in a layout design of a semiconductor integrated circuit according to claim 8, wherein the method is repeated until bit wiring is arranged. 12. A semiconductor integrated circuit in which wirings of a plurality of bits are wired in a planar or three-dimensional manner and in parallel in ascending and descending order of bits, wherein lower-order wirings of less than a predetermined bit out of the plurality of bits of wirings. Wherein the wiring interval is wider than the wiring interval of the upper-level wiring of the predetermined bit or more. 13. A semiconductor integrated circuit in which a plurality of wirings are wired in a two-dimensional or three-dimensional manner and in parallel, wherein the plurality of wirings are arranged in ascending or descending order of a signal change frequency of a signal propagating through each wiring. A semiconductor integrated circuit characterized by the fact that: 14. The wiring according to claim 13, wherein the plurality of wirings are wirings of a plurality of bits, and the plurality of wirings of the plurality of bits are arranged in a line independent of an ascending or descending order of bits.
A semiconductor integrated circuit as described in the above. 15. The semiconductor integrated circuit according to claim 13, wherein a wiring having a high signal change frequency is sandwiched between two wirings having a low signal change frequency. 16. The wiring width of each of the plurality of wirings is 0.1
The semiconductor integrated circuit according to claim 13, wherein the thickness is 8 μm or less. 17. The method according to claim 13, wherein the plurality of wirings are a plurality of address buses.
A semiconductor integrated circuit as described in the above. 18. The semiconductor integrated circuit according to claim 13, wherein each signal propagating through the plurality of wirings is an image or audio digital signal. 19. A plurality of wirings, a processing circuit that performs predetermined processing, and outputs a signal of a result of the predetermined processing to each of the plurality of wirings, and a processing circuit disposed between the plurality of wirings and the processing circuit. Switching means for changing the arrangement order of the signals output from the processing circuit so as not to be arranged in ascending or descending order of the signal change frequency of the signals, and transmitting the output signals in the changed order to the plurality of wirings A semiconductor integrated circuit comprising: 20. A receiving circuit for receiving each signal transmitted to the plurality of wirings, a receiving circuit disposed between the plurality of wirings and the receiving circuit, and receiving each signal transmitted to the plurality of wirings. 20. The semiconductor integrated circuit according to claim 19, further comprising: another switching means for changing the arrangement order in ascending order or descending order of the signal change frequency of the signal, and transmitting each signal in the changed order to the receiving circuit. circuit. 21. A function macro having a plurality of terminals to which a plurality of bits of wiring are connected, wherein the plurality of terminals are arranged in ascending or descending order of bits, and A function is characterized in that a mutual interval between bit terminals is set to a predetermined terminal interval, and a mutual interval between lower bit terminals of the plurality of terminals is set to a terminal interval longer than the predetermined terminal interval. macro. 22. A function macro having a plurality of terminals to which a wiring of a plurality of bits is connected, wherein the arrangement order of the plurality of terminals is input to each terminal regardless of ascending order or descending order of bits. A function macro, wherein the function macro is set based on a frequency of change of a signal output from a terminal. 23. The function macro according to claim 22, wherein the plurality of terminals are arranged such that terminals having a high signal change frequency are sandwiched by terminals having a low signal change frequency. 24. Terminals of upper bits of a predetermined bit or more are arranged at an interval of twice a predetermined interval in descending order from terminals of the most significant bit, and terminals of lower bits less than the predetermined bit are terminals of a least significant bit. 24. The function macro according to claim 23, wherein the function macros are arranged between terminals of the most significant bit and terminals of the higher order bit in ascending order. 25. A predetermined two-bit terminal continuous from the lowest side is arranged inside or outside a predetermined two-bit terminal continuous from the highest side.
3. The function macro according to 3. 26. Two terminals of two bits from the most significant bit are arranged at both ends, and two terminals of two bits from the least significant bit are two bits from the most significant bit.
26. The function macro according to claim 25, wherein the function macro is arranged inside two terminals of the bit. 27. The terminal of the least significant bit is located at the center of a plurality of terminals arranged side by side.
The described function macro. 28. A function macro in which a plurality of terminals arranged in ascending or descending order of bits are arranged, and arranged in an arrangement order based on a signal change frequency, and the same number as the plurality of terminals corresponding to the plurality of terminals. A semiconductor integrated circuit, comprising: another terminal provided; and a terminal rearrangement block for connecting a plurality of terminals of the function macro to the corresponding other terminal. 29. The semiconductor integrated circuit according to claim 28, wherein said function macro, said plurality of other terminals, and said terminal rearrangement block are formed integrally. 30. The function macro may be a memory, a computing unit, or a C
23. The function macro according to claim 22, wherein the function macro is a PU. 31. A plurality of wirings connected to a plurality of terminals of the function macro according to claim 23, wherein a wiring for transmitting a signal with a high signal change frequency among the plurality of wirings is connected to a plurality of terminals with a low signal change frequency. A wiring method in a layout design of a semiconductor integrated circuit, wherein the wiring method is sandwiched between wirings for transmitting one signal. 32. A signal having a plurality of function macros according to claim 23, a plurality of wirings connecting a plurality of terminals of each of the function macros, and a signal having a high signal change frequency among the plurality of wirings. The semiconductor integrated circuit is characterized in that a wiring that propagates a signal is sandwiched between two wirings that propagate a signal with a low signal change frequency. 33. The semiconductor integrated circuit according to claim 32, wherein three or more function macros are provided, and said plurality of wirings are a plurality of bit address buses. 34. Two function macros are provided, one of which is an A / D converter, and the plurality of wirings propagate a digital signal obtained by converting an analog value into a digital value by the A / D converter. 33. The semiconductor integrated circuit according to claim 32, wherein the data signal wiring comprises: