JPH06177249A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To improve design controllability of a wiring delay time in an integrated circuit device in the case of high performance and an increase in scale by reducing the same wiring layer wirings aligned adjacently in parallel in a desired net as much as possible and further forming a structure in which other layer wiring aligned in parallel on two layers are reduced as much as possible. CONSTITUTION:Wirings of a desired wiring net A regarding signal wiring laid on a wiring lattice are provided separately at two pitches or more from the other wirings on the lattice for the net A on the same wiring layer on a part in which there is at least no opening for connecting between wiring layers, and the other wirings on the two layers of the wirings of a predetermined layer are provided by avoiding a part directly above the wirings of the predetermined layer in the case that there are three or more wiring layers. That is, other wiring is not provided on a lattice on adjacent lattice x411 and x611 of the lattice (c) and adjacent lattice y411 and y211 of the lattice y311 on the lattice. Therefore, a wiring capacitance for the net A can be reduced, and a chip layout having higher timing accuracy is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and, more particularly, to a wiring structure by automatic design.

[0002]

2. Description of the Related Art In the product in which circuit blocks are connected to each other by automatic wiring, the signal interval required for the circuit operation is increased against the increase of the delay time due to the wiring load composed of wiring capacitance and resistance of integrated circuit devices. In order to adjust the relative timing of or to reduce the absolute value of the delay time, a method is used in which the relative distance of the circuit block related to the signal in question is shortened to reduce the relative variation amount or absolute value of the delay time. ing.

Specifically, an automatic placement program is provided with an algorithm for placing the circuit groups including the above-mentioned circuit blocks preferentially closer to each other, or a specific circuit block is automatically placed upon acquisition. Before that, there is a method such as preferentially placing them close to each other. In addition, for timing adjustment, a method of adding an extra load capacity to secure relative timing has been devised. Furthermore, there are a large number of circuit blocks to be connected, such as a wiring system for transmitting clock signals, for example, hundreds, and the timing skews between them must be kept below a certain value at the input points of those circuit blocks. In this case, in order to reduce the wiring resistance and facilitate this adjustment, the wiring width can be made wider than that of other signal systems, or the wiring itself can be placed at a predetermined position to facilitate control of the wiring length. There is.

To summarize the above, there are a method of reducing the absolute value of the delay time due to the wiring load and a method of aligning the relative values regardless of the absolute value. In the former case, the absolute value naturally decreases, and the variation in the relative value naturally decreases.

[0005]

In the above-described method of forming wiring in the conventional integrated circuit device, the increase in integration scale accompanying the progress of technology and the improvement in operating speed, that is, the absolute timing value to be adjusted The miniaturization has increased the number of circuits that need to be adjusted, and the associated increase in design man-hours and design time can no longer be suppressed. Therefore, it is possible to reduce the unit capacity of the wiring to reduce the degree of the above problems, but if the interlayer insulating film is thickened to reduce the wiring interlayer capacitance in the multilayer wiring, the connection between the wiring The holes for making the connection are deeper and special additional manufacturing steps are required for the connection.

On the other hand, if a design standard for increasing the relative distance between wirings is provided in order to reduce the adjacent capacitance between the same wiring layers, another problem arises in that the chip area is increased and the cost is increased. come.

[0007]

An integrated circuit device of the present invention is provided on a wiring grid and is composed of at least two wiring layers, and the wiring of each layer is orthogonal to the wiring of one layer above (or below). In the integrated circuit device having the wiring for connecting the plurality of circuit blocks to each other, the predetermined wiring that constitutes one signal series wiring by using the plurality of wiring layers is at least for connection between the wiring layers. In the same wiring layer where there is no opening, the wiring grid is used to connect with other wiring.
When the wiring layers are provided at a pitch or more and the wiring layers are three layers or more, the other wirings on two layers (or below) of the predetermined wirings are provided directly above (or immediately below) the predetermined wirings. There is something.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a layout diagram of a first embodiment of the present invention.

In FIG. 1, a chip area 1 is divided into a wiring grid area 2 in which a wiring grid 11 is provided and an outer peripheral portion. For example, a bonding pad, an input / output buffer, etc. are provided in the outer peripheral portion. . A plurality of circuit blocks 3A to 3E are provided in the wiring grid region 2, and these circuit blocks are connected by wiring formed of a plurality of wiring layers as needed. The wiring of each layer is provided on the wiring grid and is configured to be orthogonal to the wiring of one layer above (or below).

Of the connections of various circuit blocks used in the chip area 1, one signal (equal potential) series wiring (net A) wiring and an opening portion are shown by 4 to 10.
That is, the output terminal 4 of the block 3A, the input terminal 5 of the block 3B, and the input terminal 5 of the block 3D are the first layer wiring 6 and the first layer-2.
It is connected by the interlayer opening 7, the second layer wiring 8, the second layer-3 interlayer opening 9 and the third layer wiring 10.

The wiring of the net A is provided at least two pitches apart from the other wirings on the wiring grid 11 for the net A in the same wiring layer at least in a portion where there is no opening for connection between the wiring layers. In the case where the number of wiring layers is three or more, the other wiring two layers above (or below) the wiring of the predetermined layer is provided directly above (or directly below) the wiring of the predetermined layer. A description will be given below with reference to FIG. 2 which is an enlarged view of a symbol in the vicinity of the block 3A.

In FIG. 2, nets B to D of different signal series wiring which are not shown in FIG. 1 are also shown. Net B is 1
Layer wiring 16, first-layer and second-layer opening 17, second layer wiring 18,
It is composed of the second-layer and third-layer apertures 19 and the third-layer wiring 110. The net C is a first layer wiring 26, a first layer-2 interlayer opening 27, a second layer wiring 28, a second layer-3 interlayer opening 29 and 3.
It is composed of layer wiring 210. Also on Net D,
Only the single layer wiring 36 is shown.

In FIG. 2, the wirings forming the net A are not provided with other wirings on the grid adjacent to the wiring grid provided with the wirings except for a part having an opening, that is, the wiring grid. 11 adjacent grids x411 and x611 of the grid x, adjacent grids y411 and y211 of the grid y311
No other wiring is provided on the upper grid or the like.

In the present example, the part excluded previously is the relationship between the wiring 12 of the block 3A and the first-layer wiring 6 of the net A placed on y911, and the adjacency at the lattice point.
Similarly, the first layer wiring 6 on y911 and the grid point (x411, y
811) This is the case with Net B. From this adjacent length, one point of the grid point (x411, y811) and the grid point (x211, y911) to (x411, y911)
Is less than a few percent of the total length of the net A. This is because the net A is usually on the order of mm, while the adjacent length is on the order of tens of μm. Further, immediately below the three-layer wiring 10 in FIG. 2 of the net A, the wiring of two layers below that in parallel therewith, that is, the one-layer wiring is not arranged.

In contrast to the characteristics of the net A described above, for example, the net C is adjacent to the net B for one grid pitch in a considerable part of FIG. 2, and the net D is provided immediately below the three-layer wiring 210. The one-layer wiring 36 is arranged. In fact
In the conventional chip design, when attention is paid to one net, it is inevitable that the above nets B and C are adjacent to each other in a combinational relationship of thousands of nets. On the other hand, the feature of the present application is to provide a net such as the net A.

In the first embodiment, the case of the three-layer wiring is shown as an example, but in the case of the two-layer wiring, the three-layer wiring 10 is replaced with the one-layer wiring in FIG. The three-layer wirings 110 and 210 are replaced with one-layer wiring, and the one-layer wiring 36 and the three-layer wiring 210 of the net D are replaced with one-layer wiring so that the same grid y611 is not shared and the net A has one grid pitch. If it is considered that different routes that are not adjacent to each other are taken, it becomes clear even in the case of two-layer wiring.

FIG. 3 is a layout diagram of the second embodiment of the present invention, and in particular shows wirings and the like consisting of four layers only on the wiring grid. Here, the 3rd layer-4th layer opening is shown by a black square mark 13 and the 4th layer wiring is shown by 14. In FIG. 3, four kinds of nets A to D are shown, and further, there are wirings 12 inside the block 3. The wiring grids are numbered x1 to x9 and y1 to y11.

The rules for using the grid shown in FIG. 3 will be described with reference to FIG.
In FIG. 4, the n-th layer wiring lattice is indicated by l _n . It should be noted that among the paired wirings of 1st layer-3rd layer and 2nd layer-4th layer which are laid in parallel, the wirings of 1st layer-3rd layer use all the lattices while 2nd layer of 3rd layer In the -4th layer wiring, the 2nd layer wiring uses the whole lattice, whereas the 4th layer wiring is used every 1 lattice. This is because of the relationship with the manufacturing process, the surface wiring becomes more severe as the upper layer wiring becomes, and it becomes difficult to perform fine processing.

A net to be noted in FIG. 3 is indicated by A, and this net is provided on the wiring grid adjacent by one grid pitch except for the wiring 12 at the lead-out portion from the block 3. Is not placed. Further, there is no portion where the first layer wiring, the third layer wiring, the second layer wiring and the fourth layer wiring run in parallel.

As is apparent from FIG. 3, this is not the net A but the ordinary ones, that is, the nets B, C and D, as shown in FIG. They run side by side between layers. What should be particularly noted in the second embodiment is the four-layer wiring, and the wiring is based on the design standard of 1
It is ruled that wiring is provided at every grid pitch and is not particularly limited to the net A, and in other portions (not shown in FIG. 3), four grid wirings are separated by two grid pitches. Run side by side.

In order to realize the above-described structure, for example, a desired designated net is automatically laid, and at the same time, wiring prohibition data is generated in the parallel adjacent lattices in the same layer, and the parallel lattices immediately above and below. It is possible to provide a function to prevent other nets from being placed, and to layout the specified net in preference to other nets.

[0022]

As described above, according to the present invention, the wirings of the same wiring layer that run adjacent in parallel for a desired net are reduced as much as possible, and the wirings of other layers running in parallel on two layers (or below) are also sought as much as possible. As a result of the reduced structure, the wiring capacitance can be reduced as far as the desired net is concerned. In particular, since there is no parallel running part that occupies most of the wiring capacitance component, not only the absolute value of the wiring capacitance is reduced, but also the variation in the capacitance value due to the difference in the parallel running distance (at the time of design, the actual value against the average predicted value)
Is also significantly reduced. This is because the actual automatic wiring program has no control over how much distance is run in parallel. In addition, the parallel running part with the strongest degree of coupling is also affected by the variation in the equivalent capacitance value (the capacitance is 0 in the same phase and twice the fixed potential in the opposite phase when the potential is fixed) due to the relationship of the change in the relative potential with the other side of the capacitance formation described above. As a result, it is reduced at the same time.

As a result of the above, according to the present invention, a chip layout with more accurate timing can be realized, and the performance and the degree of integration of the integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a layout diagram of a first embodiment of the present invention.

FIG. 2 is an enlarged layout diagram of the first embodiment.

FIG. 3 is a layout diagram of a second embodiment of the present invention.

FIG. 4 is a diagram for explaining a wiring grid allocation rule used in the second embodiment.

[Explanation of symbols]

 1 Chip Area 2 Wiring Grid Area 3A to 3E Circuit Block 4 Output Terminal 5 Input Terminal 6, 16, 26, 36 1 Layer Wiring 7, 17, 27 1 Layer-2 Interlayer Opening Port 8, 18, 28 2 Layer Wiring 9 , 19, 29 2-layer-3 interlayer opening 10, 110, 210 3-layer wiring 12 intra-block wiring 13 3-layer-4 interlayer opening 14 4-layer wiring

Claims (1)

[Claims] 1. A wiring grid is provided and is composed of at least two wiring layers. The wiring of each layer is configured to be orthogonal to the wiring of one layer above (or below), and a plurality of circuit blocks are connected to each other. In an integrated circuit device having wiring connected to
Predetermined wiring that uses a plurality of wiring layers to form one signal series wiring is 2 pitches from other wiring in the wiring grid in the same wiring layer at least in a portion where there is no connection opening between wiring layers. When the wiring layers are separated from each other and the number of wiring layers is three or more, the other wiring on two layers above (or below) the predetermined wiring is provided directly above (or immediately below) the predetermined wiring. An integrated circuit device characterized by the above.