JP2001291776A - Arranging and wiring apparatus and layout method for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize layout capable of preventing malfunction due to inter-wiring crosstalk without using any shield electrode for increasing a parasitic capacity. SOLUTION: After blocks and micros are arranged, objective wiring for preventing cross-talk is arranged in the m-th wiring layer, and a wiring grid with (n) pieces each from the most adjacent wiring at the both sides of the objective wiring to the outside in parallel in the same layer and a wiring grid positioned just above the objective wiring belonging to the (m+k)th wiring layer (k is more than 0 and not more than n) in the upper layer than that of the objective wiring and a wiring grid with (n-k) pieces each from the most adjacent wiring at the both sides of the wiring grid to the outside are formed as a wiring inhibition area, and all the signal wiring other than the objective wring is set while the wiring inhibition area is by-passes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a placement and routing apparatus and an LSI layout method, and more particularly to a placement and routing apparatus and a layout method of an LSI for placing and routing while preventing malfunction due to crosstalk of signals between wirings.

[0002]

2. Description of the Related Art In recent LSIs, wirings have become finer and multilayered, and accordingly, the distance between adjacent wirings and the distance between upper and lower wirings have been reduced. For this reason, the coupling capacitance between the upper and lower wirings and adjacent wirings is increased, and signal crosstalk due to capacitive coupling between the wirings is increasing. On the other hand, with the acceleration of the mixture of analog and digital, and the development of large-scale LSI chips, analog signal wiring sensitive to crosstalk has been placed next to digital signal wiring, and the signal level has changed simultaneously in the same direction. In some cases, a long wiring is surrounded by a large number of wirings, and crosstalk increases due to an increase in capacitance between wirings, which often leads to characteristic deterioration and malfunction. Under such circumstances, there is an increasing need for a layout design method that can prevent crosstalk.

FIG. 12 is a configuration diagram of a layout design system, and FIG. 13 is a flowchart of a layout design method according to a first conventional example.

In FIG. 12, a layout design system stores an arrangement and wiring device 121 for arranging block macros, which are the main parts of the layout design, and setting up wiring between them, and stores circuit connection information as a result of circuit design. Circuit connection information file 122, blocks realizing primitive or small-scale functions, block macro library 123 which is a library of macros realizing large-scale functions including a plurality of blocks, and various layout and wiring parameters , A parameter file 124 for storing constraint information on layout and wiring, an input / output display device 125 as an interface between the designer and the layout system, and a layout result file 126 for storing layout results from the layout and wiring device 121. I have.

In the wiring processing by the placement and routing apparatus 121, wiring paths (hereinafter, referred to as wiring grids) at fixed intervals in the X and Y directions are temporarily provided for each wiring layer, and wiring between blocks and macros is wired. This is performed by installing the device on a lattice and connecting the upper and lower wiring layers by providing vias.

In the first conventional example shown in FIG. 13, the placement and routing apparatus 121 operates as follows.

First, in step 131, circuit connection information is read from the circuit connection information file 122, and then, in step 132, blocks and large-scale macros are
It is read from the macro library 123 and placed in the internal area of the LSI, and in step 133, a target wiring to be subjected to a crosstalk prevention measure to prevent signal deterioration due to crosstalk is provided.

Next, in step 134, shield wirings of the same layer are installed on both the left and right sides of the target wiring. Step 13
In step 5, all of the wiring grids located above the target wiring and the shield wirings on both sides are set as wiring prohibited areas and registered in the parameter file 124.
At 36, automatic wiring processing is performed for signal wirings other than the target wiring, the layout and wiring results are output to the layout result file 126, and the layout is completed.

FIG. 14A is a schematic plan view of an LSI chip, and a wiring connecting between block A and block B is a wiring 141 for preventing crosstalk. FIG. 14B is a schematic cross-sectional view of an LSI chip to which the technology of the first conventional example is applied. The shield wiring 146 is formed on both sides of the target wiring 145 provided in the first wiring layer in step 134.
Are provided, and a second wiring layer, a third wiring layer,
The area of the fourth wiring layer is set as a wiring prohibited area in step 135. The other signal wiring 148 is set in step 136
Therefore, the coupling capacitance with the target wiring 145 can be reduced, and crosstalk can be prevented. Note that reference numeral 143 denotes a substrate, and 144 denotes an insulator.

However, in the first conventional example, since the shield wiring is always provided on both sides of the target wiring, there is a first problem that the parasitic capacitance of the target wiring increases and the signal delay increases. . Also, the target wiring 145
In addition, since all wiring grids in the upper layer of the shield wiring 146 are set as the wiring prohibited area, especially when the number of wiring layers is large,
There is a second problem that the number of wiring grids for which wiring is prohibited increases.

The second problem can be improved by providing a shield wiring above the target wiring and removing the wiring prohibited area. As a result, the parasitic capacitance of the target wiring further increases. The problem becomes even more serious.

A second prior art example intended to prevent crosstalk and reduce the parasitic capacitance is described in Japanese Patent Application Laid-Open No. Hei 10-214899. FIG. 15 is a flowchart of a layout method according to a second conventional example, and FIGS. 16A and 16B.
FIG. 2 is a schematic sectional view of an LSI chip to which a second conventional example is applied. Hereinafter, a second conventional example will be described with reference to FIGS.

At step 151 in FIG. 15, the circuit connection information is read. At step 152, an attribute is added to the cautionary wiring in which signal deterioration due to crosstalk is a problem to create attribute-attached circuit connection information. And the macro is arranged in the internal area of the LSI, and
To set the attributed wiring as the target wiring for preventing crosstalk.

After the target wiring is installed in step 155, shield wirings 146 of the same layer are installed on the left and right sides of the target wiring 145 in step 156, as shown in the schematic diagram of FIG. A shield wiring 147 in an upper layer is provided directly above the wiring.

Next, at step 157, signal wirings 148 other than the target wirings are installed by automatic wiring processing as shown in FIG. Next, in step 158, the target wiring 14
When the distance between the wiring 5 and the signal wiring 148 other than the target wiring is equal to or longer than d, the shield wiring 146 provided therebetween is deleted, and the target wiring 1 is removed as shown in the schematic cross-sectional view of FIG.
For example, it is possible to improve the signal delay by reducing the parasitic capacitance 45. The predetermined distance d is obtained from the dynamic range of the digital signal, the signal speed, the allowable S / N of the analog signal, the thickness and the dielectric constant of the interlayer insulating film on the semiconductor chip, and is stored in the parameter file.

However, in the second conventional example,
Step 15 determines whether or not the shield wiring 146 can be deleted.
8 depends on the result of the automatic wiring processing of the signal wiring 148 and is not always applicable to the target wiring. Therefore, the problem that the reduction of the parasitic capacitance of the target wiring 145 cannot always be realized. Remaining.

Furthermore, L having many large macros
In the SI chip, as shown in the schematic plan view of the LSI chip in FIG. 17A, the target wiring 141 needs to pass above the macro, but as a problem common to the first and second conventional examples, As shown in the schematic cross-sectional view of FIG. 17B, the problem that the target wiring 145 provided in the third layer is not provided with any measures against crosstalk from the intra-macro wiring 171 provided in the second layer. There is.

[0018]

As described above, in the conventional example, since the shield wiring is provided adjacent to the target wiring for preventing crosstalk in order to prevent crosstalk, the parasitic capacitance of the target wiring increases. In addition, when the present invention is applied to an LSI having a macro, there is a problem that no countermeasures are taken against crosstalk from wiring in the macro.

An object of the present invention is to reduce crosstalk from signal wiring around a target wiring for preventing crosstalk to a level that does not hinder practical use, to reduce the parasitic capacitance of the target wiring, and to reduce the macro. An object of the present invention is to provide a layout and wiring apparatus and an LSI layout method that can realize a layout having a crosstalk prevention effect even when applied to an LSI chip having the same.

[0020]

According to a first aspect of the present invention, there is provided a layout and wiring apparatus which reads circuit connection information of an LSI from a circuit connection information file, and adds attribute data to a cautionary wiring of a malfunction due to crosstalk to add an attribute. Circuit connection information editing means for creating attached circuit information; block / macro arrangement means for reading and arranging block and macro data from a block / macro library based on the attributed circuit connection information; and attributes of the attributed circuit connection information Target wiring extracting means for extracting a target wiring for preventing crosstalk from the wiring to which data has been added; and installing a main part of the target wiring in an m-th wiring layer (m is a positive integer) and Each n outward from the nearest neighbor on both sides of the main part
(N is a positive integer) in the same layer in the parallel wiring grid and the (m + k) th wiring layer (k
Is an integer of 0 <k ≦ n), and interconnects a wiring grid located immediately above the main part of the target wiring and (nk) wiring grids outward from the nearest neighbor on both sides of the wiring grid. Target wiring setting means for registering in the parameter file as a prohibited area; and automatic wiring processing executing means for setting all wirings without attributes based on the circuit connection information with the attribute while avoiding the wiring prohibited area. ing.

The LSI layout method according to a second aspect of the present invention includes a first step of reading the circuit connection information of the LSI from the circuit connection information file, and adding attribute data to the caution-required wiring due to malfunction due to crosstalk. A second step of creating circuit information with attributes; a third step of reading and arranging block and macro data from a block / macro library based on the circuit connection information with attributes; and crossing the wiring to which the attribute data has been added. A fourth step of setting the target wiring for the talk prevention; and disposing the main part of the target wiring in the m-th wiring layer (m is a positive integer) and extending at least outward from the nearest neighbor on both sides of the main part of the target wiring. n (n is a positive integer) same-layer parallel wiring grids and (m + k) -th layers above the main part of the target wiring
A wiring grid located immediately above a main part of the target wiring belonging to a wiring layer (k is an integer of 0 <k ≦ n), and (nk) wirings from the nearest neighbor on both sides of the wiring grid to the outside; A fifth step of registering the grid and the wiring as a wiring prohibited area in the parameter file, and a sixth step of setting all signal wirings other than the target wiring based on the attributed circuit connection information while avoiding the wiring prohibited area. And Preferably, the fifth step is a first sub-step of reading a designated number of prohibited areas n (n is a positive integer) from a parameter file, and the fifth step in which the main part of the target wiring for preventing crosstalk is the lowermost layer. A second sub-step of determining whether or not the target wiring can be installed in one wiring layer; and when it is determined in the second sub-step that the main part of the target wiring can be installed in the first wiring layer, A third sub-step of placing the main part of the target wiring in the first wiring layer, and wiring grids in n parallel directions in each of the same layers outward from the nearest neighbor on both sides of the main part of the target wiring; A wiring grid located immediately above the main part of the target wiring belonging to the (1 + k) th wiring layer (k is an integer of 0 <k ≦ n) above the main part of the target wiring, and both sides of the wiring grid; Each (n-
k) a fourth sub-step of registering the wiring grid as a wiring prohibited area in the parameter file;
In the sub-step, when it is determined that the main part of the target wiring cannot be installed in the first wiring layer, the wiring layer to which the uppermost wiring among the lower wirings that intersect with the wiring path of the target wiring belongs to A fifth sub-step of installing the main part of the target wiring in the m-th wiring layer defined by m = (u + n + 1) in the case of the u-th wiring layer; n wiring grids in the same layer in the parallel direction, a wiring grid located immediately above a main portion of the target wiring layer belonging to the (m + k) th wiring layer above the target wiring, and a wiring grid on both sides of the wiring grid. Each (n-
k) wiring grids and a (m) layer below the target wiring.
-K) a parameter file in which a wiring grid located immediately below the main portion of the target wiring belonging to the wiring layer and each of (nk) wiring grids from the nearest neighbor on both sides of the wiring grid to the outside are defined as a wiring prohibited area; A sixth sub-step of registering with
After the execution of the fourth sub-step or the execution of the sixth sub-step, it is determined whether or not the installation has been completed for all target wirings. And a seventh sub-step of terminating the fifth step when it is determined that the placement of all returned target wirings has been completed. In extracting the target wiring, a wiring with an attribute may be temporarily installed based on the circuit connection information with an attribute, and a wiring having a length equal to or longer than a predetermined wiring length L may be extracted to be a target wiring for preventing crosstalk.

Further, in the LSI layout method according to the third invention, the first step of reading the circuit connection information of the LSI from the circuit connection information file and the step of adding attribute data to the wiring requiring caution due to malfunction due to crosstalk and adding the attribute data A second step of creating attached circuit information, a third step of reading and arranging block and macro data from the block / macro library based on the attributed circuit connection information, and a prohibited area designation number n (n
Is a positive integer), and when the number of wiring layers used in the macro is v, the wiring grid on the macro belonging to the wiring layers from the (v + 1) th layer to the (v + n) th layer is set as the first wiring prohibited area. A fourth step, and a fifth step in which the wiring to which the attribute data is added is set as a target wiring for preventing crosstalk,
A sixth step of installing a main portion of the target wiring in an m-th wiring layer defined by m = (v + n + 1) based on the attributed circuit connection information, and a seventh step of deleting the first wiring prohibited area And a wiring grid in the n parallel layers in the same layer outward from the nearest neighbor on both sides of the main part of the target wiring, and the object belonging to the (m + k) th wiring layer above the main part of the target wiring. A wiring grid located immediately above the main part of the wiring, and (n−k) wiring grids outward from the nearest neighbor on both sides of the wiring grid; A) a wiring grid located immediately below the main part of the target wiring belonging to the wiring layer and (n−k) wiring grids outward from the nearest neighbor on both sides of the wiring grid;
An eighth step of registering in the parameter file as the wiring prohibited area of the ninth step, and setting a signal wiring other than the target wiring based on the circuit connection information with the attribute so as to avoid the second wiring prohibited area. And steps. In extracting the target wiring, a wiring with an attribute may be temporarily installed based on the circuit connection information with an attribute, and a wiring having a length equal to or longer than a predetermined wiring length L may be extracted to be a target wiring for preventing crosstalk.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The outline of the present invention is based on the assumption that a triangular prism having a wiring layer to which a target wiring for preventing crosstalk belongs on one side is located above, above, and below the target wiring. Wiring processing of signal wiring other than the target wiring is performed as a wiring prohibited area. The details will be described below with reference to the drawings.

FIG. 1 is a block diagram of a placement and routing apparatus according to an embodiment of the present invention. The layout design system has the same configuration as that of FIG. 12 in the present invention, and uses the placement and routing apparatus 10 of FIG.

The placement and routing apparatus 10 includes circuit connection information editing means 11, block / macro placement means 12, target wiring extraction means 13, target wiring setting means 14, and automatic wiring processing execution means 15.

The circuit connection information editing means 11 reads the circuit connection information of the LSI from the circuit connection information file 122, and adds attribute data to the caution wiring that may cause malfunction or characteristic deterioration due to crosstalk, and adds the attributed circuit. Create information.

The block / macro arranging means 12 reads the layout data of blocks and macros from the block / macro library 123 and executes the arrangement based on the circuit connection information with attributes.

The target wiring extracting means 13 extracts a target wiring for preventing crosstalk from the wiring to which the attribute data of the circuit connection information with attributes is added. Parameter file 1
When a special extraction parameter is provided in 24, extraction is performed based on that parameter, and when no parameter is provided, all wirings to which attribute data is added are set as target wirings.

The target wiring setting means 14 sets the main part of the target wiring for preventing crosstalk in the m-th wiring layer (m is a positive integer), and at least places the main part of the target wiring outward from the nearest neighbor on both sides of the main part of the target wiring. n wiring layers (n is a positive integer) in the same layer in the parallel direction and a (m) layer above the main part of the target wiring
+ K) a wiring grid located immediately above the main part of the target wiring belonging to the wiring layer (k is an integer of 0 <k ≦ n), and (n−k) wirings from the nearest neighbor on both sides of the wiring grid to the outside. The wiring grid is registered in the parameter file as a wiring prohibited area.

The main part of the target wiring refers to a main part where the target wiring is provided in one wiring layer, and a secondary wiring for pulling up from the block or macro to the wiring layer where the main part of the target wiring is arranged. Vias connecting layers and wiring layers are not included in the main part.

The automatic wiring processing execution means 15 sets all wirings to which no attribute is added based on the circuit connection information with attributes, avoiding the wiring prohibited area.

In the m-th wiring layer to which the target wiring belongs, (2n + 1) wiring grids including the target wiring located at the center are set to be prohibited by the target wiring setting means 14, and the (m + 1) th wiring above it is prohibited. In the layer, a total of (2n-1) wiring grids, that is, the wiring grid immediately above and (n-1) wiring grids on both sides, are set to wiring prohibition, and the wiring grid (m
In the (+2) layer, a total of (2n−3) wiring grids, that is, a wiring grid immediately above the target wiring and (n−2) wiring grids on both sides, are set to wiring prohibition. That is, roughly, the cross section is (n + 1) with the base length including the (2n + 1) wiring grids.
It can be considered that the wiring grid included in the triangular prism having a height including the wiring layers for the layers is set as the wiring prohibited area.

FIG. 2 is a flow chart of an LSI layout by the placement and routing apparatus 10.

First, in step 21, the circuit connection upper editing means 11 reads the LS from the circuit connection information file 122.
The circuit connection information of I is read.

Next, in step 22, the circuit connection upper editing means 11 creates attributed circuit information by adding attribute data to the wiring requiring caution for malfunction due to crosstalk.

Next, in step 23, the block / macro arranging means 12 reads and arranges block and macro data from the block / macro library 123 based on the circuit connection information with attributes.

Next, in step 24, the wiring to which the attribute data has been added is set as the target wiring for preventing crosstalk by the target wiring extracting means 13.

Next, in step 25, the main part of the target wiring is set in the m-th wiring layer by the target wiring setting means 14, and at least n lines are placed outward from the nearest neighbor on both sides of the main part of the target wiring. A wiring grid in the same layer in the parallel direction and a (m + k) th wiring layer (0 <k) above the main part of the target wiring
≤ n), a wiring grid located immediately above the main part of the target wiring and (nk) wiring grids extending from the nearest neighbors on both sides of the wiring grid to the outside, as a wiring prohibited area. Register with.

Next, in step 26, the automatic wiring process executing means 15 sets all the signal wirings other than the target wiring on the basis of the circuit connection information with attributes, avoiding the wiring prohibited area, and the layout ends.

FIG. 3 is a detailed flowchart for setting the wiring prohibited area in step 25 of FIG. The setting of the prohibited area when there is no wiring that causes crosstalk in the layer below the target wiring and the setting of the prohibited area when there is a wiring that causes crosstalk in the lower layer are separately processed. FIG. 4 is a schematic cross-sectional view of an LSI chip in the case where there is no wiring that causes crosstalk in a lower layer, and FIG. 5 is a layout diagram for each wiring layer. FIG. 6 is a schematic cross-sectional view of an LSI chip in a case where there is a wiring which causes a crosstalk in a lower layer.
Hereinafter, a description will be given along the flow of FIG. 3 with reference to FIGS.

First, in sub-step 31, the number of prohibited area designations n registered in the parameter file 124 in advance
(N is a positive integer). The number n of prohibited areas is determined from the dynamic range of digital signals, the signal speed, the thickness and dielectric constant of the interlayer insulating film on the semiconductor chip, and is specified in advance as a parameter.

Next, in sub-step 32, it is determined whether or not the main part of the wiring to be prevented from crosstalk can be installed in the first wiring layer which is the lowermost layer.

When it is determined in sub-step 32 that the main part of the target wiring can be installed in the first wiring layer, the operation proceeds to sub-step 33, in which the main part of the target wiring is installed in the first wiring layer.

Next, in sub-step 34, n wiring grids of the same layer in the parallel direction outward from the nearest neighbors on both sides of the main part of the target wiring, and a first (1) layer above the main part of the target wiring.
+ K) a wiring grid located immediately above the main part of the target wiring belonging to a wiring layer (k is an integer of 0 <k ≦ n), and (n−k) wirings extending outward from the nearest neighbor on both sides of the wiring grid File 12 with the wiring grid of
Register to 4.

FIG. 4A is a schematic cross-sectional view of an LSI laid out through sub-steps 33 and 34 assuming that n = 2. In the first wiring layer where the target wiring 43 is provided, two lines are provided on both sides of the target wiring. A wiring grid 45 that prohibits wiring is set. In the second wiring layer corresponding to k = 1, a wiring grid immediately above the target wiring and (nk) = 1 wiring grids on both sides thereof are set as wiring prohibited wiring grids 45. k =
In the third wiring layer corresponding to No. 2, only the wiring grid located immediately above the target wiring 43 is set as the wiring grid 45 whose wiring is prohibited. The signal wirings 44 other than the target wiring 43 are arranged outside the wiring grid 45 where wiring is prohibited. In addition,
41 indicates a substrate, and 42 indicates an insulator.

5 (a) to 5 (d) are schematic diagrams showing a plan view of FIG. 4 (a) for each wiring layer, and FIG. 5 (a) shows a fourth wiring layer. b) shows the third wiring layer, and (c)
Indicates a second wiring layer, and (d) indicates a first wiring layer. FIG.
In (d), two wiring grids on both sides of the target wiring 51 among the wiring grids 53-1 in the Y direction of the first wiring layer are wiring prohibition wirings. Avoid being placed. The portion where the first-layer wiring grid 54-1 in the X direction intersects with the wiring grid in the Y direction set to wiring prohibited is a part of the wiring grid in the Y direction set to wiring prohibited, so that wiring is prohibited. Is considered to be included in the area of
Prohibit installation even if wiring in the direction. Similarly, FIG.
In (c), among the wiring grids 53-2 in the Y direction, the three wiring grids immediately above and on both sides of the target wiring 51 are set in the wiring prohibited area, so that the signal wiring 52-2 is a wiring in the Y direction. However, even if the wiring is in the X direction, it is installed so as to avoid the wiring prohibited area. Similarly, in FIG. 5B, among the wiring grids 53-3 in the Y direction, the wiring grid immediately above the target wiring 51 is set in the wiring prohibited area, so that the signal wiring 52-3 is a wiring in the Y direction. However, even if the wiring is in the X direction, it is installed so as to avoid the wiring prohibited area.

FIG. 4B is a schematic cross-sectional view of the case where the present invention is applied to an LSI in which odd-numbered wiring layers and even-numbered wiring layers are set in directions orthogonal to each other. Even if the wiring is in a direction perpendicular to the wiring grid set in the wiring prohibited area, it is prohibited to install the wiring passing through the wiring prohibited area. By connecting to the upper layer wiring, the layout is performed avoiding the wiring grid 45 where wiring is prohibited.

Returning to the flowchart of FIG.
When it is determined that the main part of the target wiring cannot be installed in the first wiring layer, the process proceeds to sub-step 35, where the wiring layer to which the uppermost wiring among the lower wirings intersecting with the wiring path of the target wiring belongs to the u-th wiring layer. In the case of a wiring layer, m = (u + n + 1)
The main part of the target wiring is set in the m-th wiring layer defined by the above.

Next, in a sub-step 36, n parallel wiring grids of the same layer outward from the nearest neighbor on both sides of the main portion of the target wiring, and the (m + k)
A wiring grid located immediately above the main part of the target wiring layer belonging to the wiring layer, and (n−k) wiring grids outward from the nearest neighbor on both sides of the wiring grid; mk) A parameter file in which a wiring grid located immediately below a main part of a target wiring belonging to a wiring layer and each of (nk) wiring grids from the nearest neighbor on both sides of the wiring grid to the outside are defined as a wiring prohibited area. Register at 124.

FIG. 6 is a schematic cross-sectional view of an LSI laid out through sub-steps 35 and 36 with n = 2 and u = 1. Since m = 4, the target wiring 43 is installed in the fourth wiring layer. In the fourth wiring layer, two wiring prohibition wiring grids 45 are set on both sides of the target wiring, and in the upper fifth wiring layer and the lower third wiring layer corresponding to k = 1, immediately above the target wiring And the wiring grid immediately below and (n
-K) = 1 wiring grid is set as the wiring grid 45 for which wiring is prohibited, and the upper sixth wiring layer and the lower second wiring layer corresponding to k = 2 are directly above and immediately below the target wiring 43. Is set as the wiring grid 45 whose wiring is prohibited, and the signal wirings 44 other than the target wiring 43 are arranged outside the wiring grid 45 whose wiring is prohibited.

After the execution of the sub-step 34 or the execution of the sub-step 36, the process proceeds to the sub-step 37, where it is determined whether or not the installation has been completed for all the target wirings. When it is determined that the placement of all target wirings has been completed, step 25 in the flowchart of FIG. 2 is ended.

FIG. 7A shows that the wiring grid pitch is 0.8.
Using a CMOS parameter of μm, the coupling capacitance value C with the surrounding wiring of the target wiring with respect to the designated number n of the prohibited area when the target wiring is arranged in the lowermost layer as shown in FIG.
FIG. 9 is a diagram of a result obtained by simulation of c. n ≦
In No. 1, the change in the capacitance Cc with the surrounding wiring is steep, whereas in n ≧ 2, the capacitance is saturated, and n ≧ 2 is preferable in consideration of LSI manufacturing variations.

FIG. 7B is a diagram showing the number G of wiring grids whose wiring is prohibited for the specified number n of prohibited areas. Since the number of wiring grids G for which wiring is prohibited increases as n increases, n
= 3 is a practical limit, and in accordance with FIG. 7A, 2 ≦ n ≦ 3 is a preferable range of the designated prohibited area number n.

FIG. 8 is a flowchart of the second embodiment.
In the present embodiment, a wiring having a short wiring length has a margin in the driving force of a circuit for driving the wiring, so that even if the signal level changes due to crosstalk, it can be easily recovered.
Even if caution is required for malfunction due to crosstalk,
Including the processing for omitting from the target wiring for which the crosstalk prevention measures are actually implemented, the process shown in FIG.
Has been deleted, and steps 84, 85 and 86 have been added instead. FIGS. 9A, 9B, and 9C are schematic plan views of the LSI for explaining the installation of the target wiring according to the flow of FIG.

In FIG. 8, steps 21 to 2 in FIG.
As in the case of step 3, circuit information is read in step 81, an attribute is added to the wiring requiring caution due to malfunction due to crosstalk in step 82, and block and macro are arranged in step 83.

In the next step 84, based on the circuit connection information with attributes, only the attributed wiring is extracted and temporarily installed. As shown in FIG. 9A, attributed wirings Lab, L
It is assumed that bc, Lcd, and Lda are temporarily installed, and the wiring length of Lcd and Lda is equal to or longer than a predetermined value L. Here, the predetermined wiring length L is the driving capability of the circuit for driving the wiring, the wiring width, the wiring interval, the wiring thickness, the thickness of the insulating film between wiring layers, the dielectric constant of the insulating film, the wiring resistance. , And is determined in advance from the operation speed of the LSI and registered in the parameter file 124.

In the next step 85, if there is a wiring longer than a predetermined wiring length L among the temporarily provided attributed wirings, this is extracted and set as a crosstalk prevention target wiring. In FIG. 9, Lcd and Lda are extracted as target wirings.

In the next step 86, the attributed wiring of the attributed wiring, which is longer than the wiring length L and less than the remaining wiring length L excluding the wiring set as the target wiring, is determined at the position where the temporary installation was performed. I do. As shown in FIG. 9B, the wiring La
b and Lbc are determined at the temporary installation position.

Next, in step 87, the wirings Lcd and Lda extracted as target wirings are set in the m-th wiring layer as shown in FIG. 9C, and a wiring prohibited area is provided in the periphery in step 25 in FIG. And step 8
7 is executed in the flow of FIG. 3 in the same manner as in step 25.

Finally, in step 88, the signal wiring to which no attribute is added is set by automatic wiring processing while avoiding the wiring prohibited area, and the layout is completed.

In the present embodiment, only wiring having a wiring length equal to or longer than a predetermined wiring length, which is likely to cause a malfunction, among wirings to which attributes are added, is set as a target wiring for preventing crosstalk. Can be greatly reduced, and accordingly, the installation of the wiring prohibited area can be suppressed. Therefore, there is an advantage that the integration density is improved as compared with the first embodiment of FIG. Note that 2 ≦ n ≦ 3 is a preferable range of the designated number n of prohibited areas, as in the first embodiment of FIG.

Next, a second embodiment of the present invention will be described. FIG. 10 is a flow chart of a layout method according to the second embodiment, and FIG. 11 is a schematic cross-sectional view of an LSI for explaining this. The flow of FIG.
The flow is based on the premise that the target wiring is installed in the upper layer of the macro as shown in FIG.

In FIG. 10, first, at step 101
Then, the circuit connection information of the LSI is read from the circuit connection information file 122.

Next, in step 102, attribute data is added to the cautionary wiring for malfunction due to crosstalk to create attributed circuit information.

Next, in step 103, based on the circuit connection information with attributes, the block macro library 123
Reads block and macro data from and arranges them.

Next, at step 104, the designated number n of prohibited areas (n is a positive integer) is read from the parameter file 124, and when the number of wiring layers used in the macro is v, the number of (v +
1) A wiring grid on a macro belonging to the wiring layers from the layer to the (v + n) th layer is defined as a first wiring prohibited area. FIG.
(A) schematically shows this state. In a large-scale macro, the first wiring layer and the second wiring layer constitute the intra-macro wiring 91, so that v = 2, and the prohibited area designation number n = 2
Then, the wiring grids belonging to the third to fourth wiring layers on the large-scale macro are set as the wiring grids 92 in the first wiring prohibited area.

Next, at step 105, the wiring to which the attribute data has been added is set as the target wiring for preventing crosstalk.

Next, at step 106, the main part of the target wiring is set on the m-th wiring layer defined by m = (v + n + 1) based on the attributed circuit connection information. FIG.
In (a), since m = 5, the target wiring 43 is provided in the fifth wiring layer.

Next, in step 107, the first wiring prohibited area is deleted. In FIG. 11A, the setting of the wiring grid 92 of the first wiring prohibited area set in the wiring grid of the third wiring layer and the wiring grid of the fourth wiring layer located on the large-scale macro is canceled.

Next, at step 108, n parallel wiring grids of the same layer outward from the nearest neighbors on both sides of the main part of the target wiring, and the (m +
k) a wiring grid located immediately above the main part of the target wiring belonging to the wiring layer and (n−k) wiring grids outward from the nearest neighbors on both sides of the wiring grid; A wiring grid located immediately below the main portion of the target wiring belonging to the lower (mk) th wiring layer and each of the (nk) wiring grids from the nearest neighbor on both sides of the wiring grid to the outside. 2 is registered in the parameter file as a wiring prohibited area. As a result, as shown in the schematic cross-sectional view of the LSI in FIG.
In the two wiring grids, the sixth wiring layer on the upper layer side and the fourth wiring layer on the lower layer side corresponding to k = 1, the wiring grids immediately above and immediately below the target wiring and (nk) = 1 on both sides thereof, respectively. In the seventh wiring layer on the upper layer side and the third wiring layer on the lower layer side corresponding to k = 2, the wiring grids located immediately above and immediately below the target wiring 43 correspond to the second wiring prohibited area. Are set as the wiring grid 93.

Next, in step 109, based on the circuit connection information with attributes, all the signal wirings other than the target wiring are set up by the automatic wiring processing while avoiding the second wiring prohibited area, and the layout is completed.

In the present embodiment, since the first wiring prohibited area is uniformly provided on the macro and the target wiring is set, the lower wiring of the lower wiring crossing the target wiring in step 35 of FIG. There is no need to detect the top layer wiring,
There is an advantage that the speed can be increased.

In the flow of FIG. 10, step 105 is deleted, and steps 84, 85,
It is needless to say that by adding the step corresponding to 86, the number of target wirings can be reduced, the placement of the wiring prohibited area can be suppressed, and the integration density can be improved. In addition, the fact that 2 ≦ n ≦ 3 is a preferable range of the designated number n of prohibited areas is the same as in the first embodiment of FIG.

[0074]

As described above, by applying the arrangement and wiring apparatus of FIG. 1 or the layout method of FIG. 2 according to the present invention, the coupling capacitance between the target wiring for preventing crosstalk and the surrounding signal wiring is reduced. In addition to the reduction in malfunction, the parasitic capacitance of the target wiring can be reduced, and a layout having an effect of preventing crosstalk can be realized even when applied to an LSI chip having a macro.

In the embodiment shown in FIG. 8, only wires having a wire length equal to or longer than a predetermined wire length, which is likely to cause a malfunction, among wires to which attributes are added, are set as target wires for the crosstalk prevention measure. Since the number of target wirings can be significantly reduced, and accordingly, the installation of a wiring prohibited area can be suppressed,
There is a new advantage that the integration density is improved in addition to the effect of the embodiment.

In the embodiment of FIG. 10, since the first wiring prohibited area is uniformly provided on the macro and the target wiring is installed, it is not necessary to detect whether the target wiring intersects with the lower wiring. In addition to the effects of the embodiment of FIG.

[Brief description of the drawings]

FIG. 1 is a block diagram of a placement and routing apparatus according to an embodiment of the present invention.

FIG. 2 is a flow chart of an LSI layout according to the present invention.

FIG. 3 is a detailed flowchart of step 25 in FIG. 2;

FIG. 4 is a schematic cross-sectional view of an LSI chip in a case where there is no wiring that causes crosstalk in a lower layer.

FIG. 5 is a layout diagram for each wiring layer corresponding to the schematic cross-sectional view of FIG. 4;

FIG. 6 is a schematic cross-sectional view of an LSI chip in a case where a wiring that causes a crosstalk is present in a lower layer.

FIG. 7A is a diagram illustrating a simulation result of a coupling capacitance value Cc between a target wiring and a surrounding wiring with respect to a specified prohibited area number n, and FIG. 7B is a wiring in which wiring is prohibited for the specified prohibited area number n; It is a figure showing lattice number G.

FIG. 8 is a flowchart of a second example of the first embodiment.

FIGS. 9A, 9B, and 9C are schematic plan views of the LSI for explaining the installation of the target wiring according to the flow of FIG. 8;

FIG. 10 is a flowchart of a layout method according to the second embodiment.

11A is a schematic cross-sectional view of the LSI showing the state of step 106 in FIG. 10, and FIG.

FIG. 12 is a configuration diagram of a layout design system.

FIG. 13 is a flowchart of a layout design method of a first conventional example.

14A is a schematic plan view of an LSI chip, and FIG. 14B is a schematic cross-sectional view of an LSI chip to which the technology of the first conventional example of the LSI chip of FIG.

FIG. 15 is a flowchart of a layout method according to a second conventional example.

16A and 16B are schematic cross-sectional views of an LSI chip to which a second conventional example is applied.

17A is a schematic plan view of an LSI chip including a macro, and FIG. 17B is a schematic sectional view corresponding to FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 placement and wiring device 11 circuit connection information editing means 12 block / macro placement means 13 target wiring extraction means 14 target wiring installation means 15 automatic wiring processing execution means 43, 51, 141, 145 target wiring 44, 148 signal wiring 45 wiring prohibition Wiring grid 46 Via 91, 171 Wiring in macro 92 Wiring grid in first wiring prohibited area 93 Wiring grid in second wiring prohibited area 121 Place and route device 122 Circuit connection information file 123 Block macro library 124 Parameter file 125 Input / output Display device 126 Layout result file 146, 147 Shield wiring

Claims (8)

[Claims] 1. A circuit connection information editing means for reading circuit connection information of an LSI from a circuit connection information file and adding attribute data to wiring requiring caution for malfunction due to crosstalk to create circuit information with attributes; Block / macro arranging means for reading and arranging block and macro data from a block / macro library based on the connection information; and extracting a crosstalk prevention target wiring from the wiring to which the attribute data of the attributed circuit connection information is added. Means for extracting the target wiring, and setting the main part of the target wiring in the m-th wiring layer (m is a positive integer) and n-pieces (where n is positive) at least outward from the nearest neighbor on both sides of the main part of the target wiring. An (integer) wiring layer in the same layer in the parallel direction and an (m + k) -th wiring layer (k is 0 <k ≦ n) above the main portion of the target wiring. The wiring grid located immediately above the main part of the target wiring belonging to the (integer) and each (n−k) wiring grids from the nearest neighbor on both sides of the wiring grid to the outside are registered in the parameter file as the wiring prohibited area. A placement and routing apparatus comprising: target wiring setting means; and automatic wiring processing execution means for setting all wirings to which no attribute is added based on the attributed circuit connection information while avoiding the wiring prohibited area. . 2. A first step of reading circuit connection information of an LSI from a circuit connection information file, and a second step of adding attribute data to wiring requiring caution for malfunction due to crosstalk and creating circuit information with attributes. A third step of reading and arranging block and macro data from a block / macro library on the basis of the attributed circuit connection information, and a fourth step of setting a wiring to which the attribute data has been added as a target wiring for preventing crosstalk Placing the main part of the target wiring in the m-th wiring layer (m is a positive integer) and n-pieces (n is a positive integer) of the same layer at least outward from the nearest neighbor on both sides of the main part of the target wiring And the main wiring of the target wiring belonging to the (m + k) th wiring layer (k is an integer of 0 <k ≦ n) above the main part of the target wiring. A fifth step of registering, in a parameter file, a wiring grid located immediately above the minute and the (nk) wiring grids from the nearest neighbor on both sides of the wiring grid to the outside as a wiring prohibited area; And setting a signal wiring other than the target wiring based on the circuit connection information so as to avoid the wiring prohibited area. 3. The fifth step includes: a first sub-step of reading a designated prohibited area number n (n is a positive integer) from a parameter file; and a fifth step in which a main portion of a crosstalk prevention target wiring is a lowermost layer. A second sub-step of determining whether or not the target wiring can be installed in one wiring layer; and when it is determined in the second sub-step that the main part of the target wiring can be installed in the first wiring layer, A third sub-step of placing the main part of the target wiring in the first wiring layer; and wiring grids in n parallel directions in each of the same layers outward from the nearest neighbor on both sides of the main part of the target wiring; A wiring grid located immediately above the main part of the target wiring belonging to the (1 + k) th wiring layer (k is an integer of 0 <k ≦ n) above the main part of the target wiring, and both sides of the wiring grid; (N−k) wiring grids from the nearest neighbor to the outside A fourth sub-step of registering the main wiring of the target wiring in the parameter file as a wiring prohibited area; and determining that the main part of the target wiring cannot be installed in the first wiring layer in the second sub-step. M = (u + n) when the wiring layer to which the uppermost wiring among the lower wirings intersecting with the wiring path of (i) belongs is the u-th wiring layer.
A fifth sub-step of installing the main part of the target wiring in the m-th wiring layer defined by +1); A wiring grid, a wiring grid located immediately above a main portion of the target wiring layer belonging to the (m + k) th wiring layer above the target wiring, and (n−k) outside from the nearest neighbor on both sides of the wiring grid. A) a wiring grid, a wiring grid located immediately below a main portion of the target wiring belonging to the (mk) th wiring layer below the target wiring, and a wiring grid extending outward from the nearest neighbor on both sides of the wiring grid. A sixth sub-step of registering (nk) wiring grids as a wiring prohibited area in a parameter file; and all target wirings after execution of the fourth sub-step or after execution of the sixth sub-step. Installation completed And determining whether there is an unplaced target wiring, returning to the second sub-step, and determining that the placement of all the target wirings has been completed, and ending the fifth step in a seventh sub-step. An LSI according to claim 2
Layout method. 4. A first step of reading the circuit connection information of the LSI from the circuit connection information file, and a second step of adding attribute data to the caution wiring requiring malfunction due to crosstalk to create attributed circuit information. A third step of reading and arranging block and macro data from a block / macro library based on the attributed circuit connection information, and a fourth step of temporarily installing attributed wiring based on the attributed circuit connection information; A fifth step of extracting a wire having a length equal to or longer than a predetermined wire length L registered in the parameter file from the temporarily provided wire with attributes and setting the wire as a target wire for preventing crosstalk; A sixth step of determining the installation of the attributed wiring, and setting the main part of the target wiring in the m-th wiring layer (m is a positive integer) At least n (n is a positive integer) parallel wiring grids in the same layer outward from the nearest neighbor on both sides of the main part of the target wiring, and the (m + k) -th layer above the main part of the target wiring. A wiring grid located immediately above a main part of the target wiring belonging to a wiring layer (k is an integer of 0 <k ≦ n), and (nk) wirings from the nearest neighbor on both sides of the wiring grid to the outside; A seventh step of registering a grid as a wiring prohibited area in the parameter file, and installing all signal wirings to which no attribute is added based on the attributed circuit connection information while avoiding the wiring prohibited area. LS characterized by having the following steps:
I layout method. 5. The method according to claim 1, wherein the seventh step is a first sub-step of reading a prohibited area specification number n (n is a positive integer) from a parameter file, and the main part of the crosstalk prevention target wiring is a lowermost layer. A second sub-step of determining whether or not the target wiring can be installed in one wiring layer; and when it is determined in the second sub-step that the main part of the target wiring can be installed in the first wiring layer, A third sub-step of placing the main part of the target wiring in the first wiring layer; and wiring grids in n parallel directions in each of the same layers outward from the nearest neighbor on both sides of the main part of the target wiring; A wiring grid located immediately above the main part of the target wiring belonging to the (1 + k) th wiring layer (k is an integer of 0 <k ≦ n) above the main part of the target wiring, and both sides of the wiring grid; (N−k) wiring grids from the nearest neighbor to the outside A fourth sub-step of registering the main wiring of the target wiring in the parameter file as a wiring prohibited area; and determining that the main part of the target wiring cannot be installed in the first wiring layer in the second sub-step. M = (u + n) when the wiring layer to which the uppermost wiring among the lower wirings intersecting with the wiring path of (i) belongs is the u-th wiring layer.
A fifth sub-step of installing the main part of the target wiring in the m-th wiring layer defined by +1); A wiring grid, a wiring grid located immediately above a main portion of the target wiring layer belonging to the (m + k) th wiring layer above the target wiring, and (n−k) outside from the nearest neighbor on both sides of the wiring grid. A) a wiring grid, a wiring grid located immediately below a main portion of the target wiring belonging to the (mk) th wiring layer below the target wiring, and a wiring grid extending outward from the nearest neighbor on both sides of the wiring grid. A sixth sub-step of registering (nk) wiring grids as a wiring prohibited area in a parameter file; and all target wirings after execution of the fourth sub-step or after execution of the sixth sub-step. Installation completed And determining whether there is an unplaced target wiring, returning to the second sub-step, and determining that all the target wirings have been placed, and ending the seventh step when determining that all the target wirings have been completed. An LSI according to claim 4
Layout method. 6. A first step of reading circuit connection information of an LSI from a circuit connection information file, and a second step of adding attribute data to a cautionary wiring for malfunction due to crosstalk to create attributed circuit information. A third step of reading and arranging block and macro data from the block / macro library based on the attributed circuit connection information, and reading a prohibited area designation number n (n is a positive integer) from a parameter file and using the read data in the macro. A fourth step of setting the wiring grid on the macro belonging to the wiring layers from the (v + 1) th layer to the (v + n) th layer as the first wiring prohibited area when the number of wiring layers is v; A fifth step in which the selected wiring is used as a target wiring for preventing crosstalk, and a main part of the target wiring is an m-th wiring determined by m = (v + n + 1). A sixth step of setting a layer based on the attributed circuit connection information, a seventh step of deleting the first wiring prohibition area, and each of n outside the nearest neighbor on both sides of the main portion of the target wiring A wiring grid in the same layer in the parallel direction, a wiring grid positioned immediately above the main part of the target wiring belonging to the (m + k) th wiring layer above the main part of the target wiring, and a wiring grid on both sides of the wiring grid. (N−k) wiring grids from the nearest neighbor to the outside,
A wiring grid located immediately below the main part of the target wiring belonging to the (mk) th wiring layer below the main part of the target wiring, and each (n-
k) an eighth step of registering the wiring grids as a second wiring prohibited area in the parameter file, and the second wiring prohibition of all signal wirings other than the target wiring based on the attributed circuit connection information. Ninth step of setting the area to avoid the area.
SI layout method. 7. A first step of reading circuit connection information of an LSI from a circuit connection information file, and a second step of adding attribute data to a cautionary wiring of a malfunction due to crosstalk to create attributed circuit information. A third step of reading and arranging block and macro data from a block / macro library based on the attributed circuit connection information, and a fourth step of temporarily installing attributed wiring based on the attributed circuit connection information; A fifth step of extracting a wire having a length equal to or longer than a predetermined wire length L registered in the parameter file from the temporarily provided wire with attributes and setting the wire as a target wire for preventing crosstalk; The sixth step of deciding the installation of the attributed wiring, and reading the prohibited area designation number n (n is a positive integer) from the parameter file A seventh step in which when the number of wiring layers used in the macro is v, the wiring grid on the macro belonging to the wiring layers from the (v + 1) th layer to the (v + n) th layer is set as a first wiring prohibited area; An eighth step of installing a main portion of the target wiring in an m-th wiring layer defined by m = (v + n + 1) based on the attributed circuit connection information; and a ninth step of deleting the first wiring prohibited area. A wiring grid extending in parallel from the nearest neighbor on both sides of the main part of the target wiring in each of the n layers and the target wiring belonging to the (m + k) th wiring layer above the main part of the target wiring; And (n−k) wiring grids located immediately above the main part of the wiring grid and outward from the nearest neighbor on both sides of the wiring grid;
A wiring grid located immediately below the main part of the target wiring belonging to the (mk) th wiring layer below the main part of the target wiring, and each (n-
k) a tenth step of registering the wiring grids as a second wiring prohibited area in the parameter file, and replacing all signal wirings to which no attribute is added based on the attributed circuit connection information with the second wiring. An eleventh step of avoiding the prohibited area for installation.
I layout method. 8. The method according to claim 2, wherein 2 ≦ n ≦ 3.
8. The layout method of an LSI according to 5, 6, or 7.