JP3649344B2 - Delay-considered wiring method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a delay-considering wiring system, and more particularly, to a delay-considering wiring system suitable for use in wiring for path delay optimization in determining a wiring path of a semiconductor integrated circuit or the like that operates at high speed.
[0002]
[Prior art]
As a conventional technique related to a wiring method in consideration of a path delay, for example, a technique described in Japanese Patent Laid-Open No. 4-151853 is known.
[0003]
In this prior art, the signal propagation delay time (delay) of each path is calculated after the automatic wiring process, and for the wiring that is in violation of the delay, the parallel wiring adjacent to the wiring, the crossing crossed in multiple layers The wiring is removed and these wirings are rewired to other positions to reduce the delay caused by the capacitance between the wiring that is in violation of the delay, the parallel wiring, and the cross wiring.
[0004]
[Problems to be solved by the invention]
In the prior art, when changing the path of the parallel wiring and the cross wiring with respect to the wiring that is in violation of the delay, the wiring path of the change destination cannot be found, and the path change may not be possible. There is a problem that due to the change, there is a possibility that other wiring may cause a delay violation, and the delay cannot be greatly improved.
[0005]
The object of the present invention is to solve the above-mentioned problems of the prior art, make it possible to reliably optimize the wiring delay and load delay, and to suppress the path delay within a limit value determined from the operating speed of the apparatus. An object of the present invention is to provide a delay-considered wiring method.
[0006]
[Means for Solving the Problems]
The object according to the present invention, the delay consideration wiring method of a semiconductor integrated circuit for determining the wiring between the plurality of connection terminals each other provided on a wiring substrate, between the location information of the gate of the semiconductor integrated circuit from the library and the terminal Input means for inputting connection information and a gate type table for specifying a wiring pattern shape for each gate type, and between terminals based on a virtual wiring length estimated from element arrangement data before wiring between connection terminals A calculation means for calculating a signal propagation delay time, and a path between terminals whose signal propagation delay time calculated by the calculation means exceeds a limit value determined from the operation speed of the apparatus, and this path is configured. The net that requires wiring that takes into account the signal propagation delay time between gates is extracted as a critical net using the weight attached to the net as an index. Means and, after the wide wiring in favor of critical nets extracted to other nets by extraction means, and a wiring means for performing wire nets than the critical nets at the normal wiring width, the wiring in the wide wiring The converted critical net is converted into a wiring having a normal wiring width according to the contents of the gate type table , or a wiring having a wiring width narrower than the wide wiring , having a wiring width of arbitrary, a plurality of wirings This is achieved by including a conversion unit that converts the wirings having different wiring widths or at least one of the wirings having different starting point widths and end point widths .
[0007]
[Action]
The present invention calculates a path delay between flip-flops based on a virtual wiring length estimated from element arrangement data before wiring, and extracts a critical net based on the result. And, the present invention performs a wide wiring in advance considering a delay only for a net having a maximum path delay that is a factor that determines the operation speed of a semiconductor integrated circuit, and a net that configures a path having a delay margin. A normal width wiring is performed. The wide wired net is then converted into a normal wiring width or a width and shape designated for each source gate type.
[0008]
Accordingly, the present invention can reduce the wiring delay due to the load capacitance between the adjacent parallel wiring and the ground of the path having the critical net, and the wiring delay depending on the wiring resistance. Optimization can be achieved.
[0009]
Further, in the present invention, for the delay optimization described above, there is no change in adjacent wiring or crossing wiring, and the wiring delay is optimized without requiring extra man-hours. Wiring can be performed.
[0010]
【Example】
Hereinafter, an embodiment of a delay-considering wiring system according to the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 is a diagram for explaining the processing operation of a delay-considered wiring system according to an embodiment of the present invention, FIG. 2 is a diagram for explaining extraction of a critical net, and FIG. 3 is a table structure for designating a wiring pattern shape for each gate type FIG. 2 and 3, 201 to 204 are flip-flops, 206 and 207 are paths, 301 is a gate type table, and 302 is a section / wiring width definition table.
[0012]
First, the processing operation according to the embodiment of the present invention will be described with reference to the processing flow shown in FIG.
[0013]
(1) Prior to performing wiring, a library of arrangement information such as gates and connection information is input into the processing apparatus in order to extract critical paths and critical nets (step 101).
[0014]
(2) Based on the input library information, the path delay between all connection terminals is calculated, the path causing the delay violation, that is, the critical path is searched, and the path is further configured. A critical net is extracted in consideration of the weight of the net (step 102).
[0015]
(3) The critical net extracted in step 102 is wired with, for example, a 5-fold wide wiring (step 103).
[0016]
(4) All other nets that have not been extracted as critical nets are wired with normal width wiring (step 104).
[0017]
(5) In accordance with the contents of the gate type table read as a library, the wiring that is wired at a five-fold width is converted into a normal width or a specified shape (step 105).
[0018]
Next, the critical path and critical net extraction processing in step 102 will be described in detail with reference to the path configuration example shown in FIG.
[0019]
Now, as shown in FIG. 2, there are a path 206 connecting the start-point flip-flop 201 and the end-point flip-flop 204, and a path 207 connecting the start-point flip-flop 202 and the end-point flip-flop 203. Assume that paths are connected by a plurality of nets via a plurality of gates, and one net 205 is used in common. It is assumed that both of these paths 206 and 207 cause a delay violation due to delay over.
[0020]
In such a case, in the processing of step 102, the processing device weights each net configuring these paths according to the number of paths to which the net belongs, and sets the net with a large weight as the critical net. Extract. In this example, the net 205 at the center is used for both paths 206 and 207, and its weight is 2. Thereby, the processing apparatus extracts the net 205 as a critical net.
[0021]
The reason why such a net is extracted as a critical net is that the delay violation of the paths 206 and 207 can be easily eliminated by reducing the delay of the net.
[0022]
Next, with reference to FIG. 3 showing the structure of the table for designating the wiring pattern shape for each gate type, the processing for changing the wiring width in step 105 will be described in detail.
[0023]
The library input in step 101 includes a table that defines a section specified by a distance based on the source terminal for each gate type and a wiring width for each section. In the process of step 105, according to the contents of this table, a process of changing a wide wiring to a predetermined width and shape is performed.
[0024]
As shown in FIG. 3, the above-described table includes a gate type table 301 and a section / wiring width definition table 302. The gate type table 301 is configured to store the number of wiring sections provided for each gate type and the start address of the section / wiring width definition table 302 provided for each wiring section. The section / wiring width definition table 302 includes: The start point information and end point information of the section, and the start point width and end point width of the section are stored.
[0025]
In the process of step 105, based on the information of the table configured as described above, the wiring once widened, in this example, 5 times wide, is changed to a normal width, or a predetermined wiring shape is formed. Change to By this processing, the wiring shape can be changed so that the delay depending on the driving capability of the gate is optimized for each gate type.
[0026]
Next, the wiring situation according to the embodiment of the present invention described above will be described with reference to the drawings.
[0027]
FIG. 4 is a diagram showing an image in the case where a 5-fold wide wiring is applied to two wiring layers according to an embodiment of the present invention. In FIG. 4, 401 is a source terminal, 402 is a sink terminal, 403 and 405 are 5 times wider wiring patterns than the first layer, 404 is 5 times wider wiring patterns than the second layer, and 406 and 407 are through holes. .
[0028]
In FIG. 4, the wide wiring pattern 403 that is five times as large as the first layer connects the source terminal 401 and the through hole 406, and the wide wiring pattern 404 that is five times as wide as the second layer is the through hole 406 and the through hole. 407 and a wide wiring pattern 405 that is five times the first layer connects the through hole 407 and the sink terminal 402.
[0029]
The example of FIG. 4 shows a state after the process of step 103 of FIG. 1 is completed, and thereafter, another net is wired with a normal width by the process of step 104.
[0030]
FIG. 5 is a diagram showing an image after the wiring that is five times wide as shown in FIG. 4 is converted to the normal width by the process of step 105 in FIG. Such wiring width conversion can be performed by defining all the wiring widths as normal widths in the table described with reference to FIG. In FIG. 5, reference numerals 501 and 503 are normal-width wiring patterns of the first layer, 502 is a normal-width wiring pattern of the second layer, 504 and 505 are through-holes, and 506 is an adjacent parallel running parallel to the target net. A wiring pattern, 507 is a source terminal, and 508 is a sink terminal.
[0031]
In FIG. 5, the first layer normal width wiring pattern 501 connects the source terminal 507 and the through hole 504, and the second layer normal width wiring pattern 502 includes the through hole 504 and the through hole 505. The first-layer wiring pattern 503 having a normal width connects the through hole 505 and the sink terminal 508. These wiring patterns are formed by once changing the wiring that is five times wide as shown in FIG. 4 to the normal width.
[0032]
As a result, it is possible to reduce the load capacity between the adjacent parallel wiring pattern 506, which is a net wired in parallel with the above-described wiring pattern as a critical net, and shorten the load delay of this net. can do.
[0033]
FIG. 6 is a diagram showing an image after the wiring that is five times wide as shown in FIG. 4 is converted so as to be different for each section in the process of step 105 of FIG. Such wiring width conversion can be performed by defining the section width and the section width for each gate type in the table described with reference to FIG. 3 so that the start point width and end point width of the section are equal. In FIG. 6, 601 is a wide wiring pattern 5 times as large as the first layer, 602 is a wide wiring pattern three times as large as the first layer, 603 is a wiring pattern with a normal width of the second layer, and 604 is a normal width of the first layer. 605 and 606 are through holes, 607 is a source terminal, and 608 is a sink terminal.
[0034]
In FIG. 6, a wide wiring pattern 601 that is five times as large as the first layer and a wide wiring pattern 602 that is three times as large as the first layer connect the source terminal 607 and the through hole 605, and have the normal width of the second layer. The wiring pattern 603 connects the through hole 605 and the through hole 606, and the normal-width wiring pattern 604 of the first layer connects the through hole 606 and the sink terminal 608. These wiring patterns are formed by once changing the wiring that is five times wide as shown in FIG. 4 according to the information stored in the table.
[0035]
FIG. 7 shows the result of converting the wiring wired at 5 times width as shown in FIG. 4 so that the wiring width of each section is different between the starting point width and the ending point width of the section in the process of step 105 of FIG. It is a figure which shows an image. Such wiring width conversion can be performed by defining the section and the wiring width of each section for each gate type so that the start point width and end point width of the section are different in the table described with reference to FIG. it can. In FIG. 7, reference numeral 701 denotes a variable-width wiring pattern of the first layer, 702 a normal-width wiring pattern of the second layer, 703 a normal-width wiring pattern of the first layer, 704 and 705 through holes, and 706 a source. A terminal 707 is a sink terminal.
[0036]
In FIG. 7, a variable wiring pattern 701 in the first layer connects a source terminal 706 and a through hole 704, and a normal wiring pattern 702 in the second layer has a through hole 704 and a through hole 705. The first-layer wiring pattern 703 having a normal width connects the through hole 705 and the sink terminal 707. These wiring patterns are formed by once changing the wiring that is five times wide as shown in FIG. 4 according to the information stored in the table.
[0037]
In the example shown in FIG. 6 and FIG. 7 described above, the wiring width of a certain net can be changed depending on the position from the source gate. Therefore, the wiring delay depending on the wiring resistance determined by the wiring width and the interval between adjacent parallel wirings. Therefore, it is possible to optimize the delays which are mutually contradictory with the load delays depending on the load capacity determined by
[0038]
In the above description, one example of changing the wide wiring has been described with reference to FIGS. 5 to 7. However, in the present invention, in addition to this, instead of changing to the normal width, double width, triple width The width may be changed to an arbitrary width, and the wiring can be performed by combining these.
[0039]
In the above-described embodiment of the present invention, the extracted critical net is wired five times wide, and then the wiring width is changed to optimize the delay. The wiring may be arranged to have an arbitrary n (n ≧ 2) double width instead of the double width, and the load capacity and wiring resistance between adjacent parallel wirings can be greatly improved.
[0040]
According to the embodiment of the present invention described above, a semiconductor integrated circuit in which a plurality of wiring patterns having a plurality of wiring widths and wiring shapes are mixed can be obtained by optimizing the delay of all paths.
[0041]
【The invention's effect】
As described above, according to the present invention, a critical net is wired broadly first, and the widened critical net can be converted into a normal width after the wiring of all nets is completed. It is possible to reduce the load capacity between the wiring and the load delay.
[0042]
In addition, according to the present invention, a critical net that is widely wired can be converted into a predefined shape for each source gate type after the wiring of all nets is completed. The load delay depending on the capacity can be optimized.
[0043]
Furthermore, according to the present invention, since the load capacity and wiring resistance of the critical net can be lowered, it is possible to expect a reliable delay reduction.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a processing operation of a delay-considering wiring method according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a method for extracting a critical net.
FIG. 3 is a diagram illustrating the structure of a table for designating a wiring pattern shape for each gate type.
FIG. 4 is a diagram showing an image when a 5-fold wide wiring is applied to two wiring layers.
FIG. 5 is a diagram illustrating an image after a wiring that is wired with a width of 5 times is converted into a normal width;
FIG. 6 is a diagram illustrating an image after a wiring that is wired with a width of 5 times is converted so as to be different for each section;
FIG. 7 is a diagram showing an image after wiring having been wired with a width of 5 times is converted so that the wiring width of each section is different between the start point width and the end point width of the section;
[Explanation of symbols]
201-204 Flip-flop 206, 207 Path 301 Gate type table 302 Section / wiring width definition table 401, 507, 607, 706 Source terminal 402, 508, 608, 707 Sink terminal 403, 405, 601 5 times the first layer Wide wiring pattern 404 Wide wiring patterns 501, 503, 604, 703 five times the second layer Normal width wiring patterns 502, 603, 702 Second layer normal width wiring patterns 506 Adjacent parallel wiring patterns 602 Wide wiring pattern 701 three times as large as the first layer Variable width wiring pattern of the first layer

Claims (1)

In a delay-considered wiring method of a semiconductor integrated circuit that determines wiring between a plurality of connection terminals provided on a wiring board,
Input means for inputting gate arrangement information and inter-terminal connection information of a semiconductor integrated circuit from a library, and a gate type table for specifying a wiring pattern shape for each gate type,
Calculation means for calculating a signal propagation delay time between terminals based on a virtual wiring length estimated from element arrangement data before wiring between connection terminals;
A path between terminals whose signal propagation delay time calculated by the calculation means exceeds a limit value determined from the operating speed of the device is extracted, and a weight given to a net constituting the path is used as an index to gate An extraction means for extracting a net that requires wiring in consideration of a signal propagation delay time as a critical net;
Wiring means for wiring a net other than the critical net with a normal wiring width after the critical net extracted by the extracting means is preferentially wired with priority over other nets;
The critical net wired by the wide wiring is converted into a wiring having a normal wiring width according to the contents of the gate type table , or a wiring having a wiring width narrower than the wide wiring, and an arbitrary wiring width is set. A delay-considering wiring system comprising: a wiring having a plurality of wirings having a plurality of different wiring widths; or a conversion unit that converts the wirings into different wirings having different start point widths and end point widths .

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