JPH0212857A - Wiring process of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To minimize the wiring intersections near the channel boundary for restraining the channel track numbers from increasing by a method wherein, before performing the wiring process in detail, the channel boundary terminals are classified into two groups meeting specified requirements and then one terminal is selected from respective groups to make a pair which is provided with the relative position thereof. CONSTITUTION:When the space between the first block BL1 and the second block BL2 adjacent to each other is referred to as the first channel CH4 while the other space perpendicular to the CH4 is referred to as the second channel CH1 as well as the channel boundary terminals are referred to as A1-A3, B1-B3, the channel boundary terminals are classified into two groups i.e., the group A required to be connected in the first direction in parallel with the channel boundary 4 (in the direction of the first block BL1 side) in the second channel CH1 and the second group B required to be connected in the second direction in parallel with the channel 4 (in the direction of the second block BL2 side) and then one each out of respective groups A, B is selected to make a pair so that the relative positions thereof may be set up by locating the channel boundary element belonging to the first group A out of the pair on the first block BL1 side that belonging to the second group B on the second block BL2 side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a wiring method between blocks of a semiconductor integrated circuit using a building block method.

(Prior art) In the building block layout, a circuit is divided into multiple functional units, then these are individually laid out as blocks, and finally each block is placed on a chip and the wiring between the blocks is determined. Do the following.

Figure 2 shows block division and distribution Q! Blocks 1 indicated by BL to BL4, which show the state of region division, are laid out, and the wiring regions 2 around these blocks 1 are divided into a plurality of channels CH, so that a channel boundary 4 indicated by a broken line is formed. - Divide into CH7. An input/output circuit block 3 is arranged around the chip.

When wiring between blocks, it is common practice to divide the wiring area 2 into multiple channels CH1 to CH7 as shown in Figure 2, first determine the general wiring route, and then process the detailed wiring. It is true. The flow of this wiring process is shown in FIG. 5. During this wiring process, a virtual terminal (channel boundary terminal) is set on the channel boundary 4 between adjacent channels, and the channel to which the wiring process is performed first Its exact position is determined on one side, and the wiring is drawn out with reference to that position on the other adjacent channel side. At this time, the positions r! of the channel boundary terminals! In the conventional method of performing wiring processing without giving any consideration to the A section, there is a problem in that the wiring crosses near the channel boundary, resulting in an increase in the channel width.

Figure 6 shows this situation. This corresponds to the two blocks BL1. This is a conventional example in which wiring processing is performed on two channels CH4 and CH1 that are in contact with BL2 and are orthogonal to each other. In this example, it is necessary that the wiring process for the horizontal channel CH4 always precedes that for the vertical channel CH1, and by determining the wiring 5 for the horizontal channel CH4, the terminal on the channel boundary 4 is determined, and this is referred to. The wiring 6 in the vertical channel CH1 is then determined. In this manner, in the conventional method, it remains unclear in what direction the terminals determined on the channel boundary 4 in the wiring process of the horizontal channel CH4 will be drawn out within the vertical channel CH1, resulting in unnecessary cross wiring.

(Problems to be Solved by the Invention) As described above, in the conventional building and block wiring methods, wiring crosses occur at the boundary between a channel in one direction and a channel in an adjacent and orthogonal direction. However, as a result, the channel width increases, which hinders the improvement of the degree of integration of integrated circuits.

An object of the present invention is to provide a wiring method for semiconductor integrated circuits that does not solve these problems.

[Configuration of the Invention (Means for Solving the Problems) In the present invention, on the channel boundary connecting channels, channel boundary terminals set for signal lines crossing the boundary are set in a partial order. Determine the relative positional relationship between the two blocks, and perform detailed wiring for each channel while maintaining that positional relationship.More specifically, the first channel is connected between the adjacent first block and the second block. , the one that is in contact with and orthogonal to this is the second channel, and when considering the channel boundary terminal between these, first, in the second channel, the first direction parallel to the channel boundary (direction on the first block side) ) and a second group that requires connection in the second direction parallel to the channel boundary (direction toward the second block side), and one from each group. Take out each pair to form a pair, and set the relative positional relationship so that the items in the first group are located on the first block side and the items in the second group are located on the second block side of each pair. .

Preferably, when investigating how to draw out wiring from a channel boundary, in order to reduce the deviation from the detailed wiring processing time, the channel width is estimated in advance, and the position of each block, block terminal position, and channel boundary position is estimated in advance. Estimate.

(For f1!) When processing the wiring of adjacent channels across a channel boundary separately in this way, divide the multiple channel boundary terminals on the channel boundary into two groups, and arbitrarily select between these groups. By determining the relative order of the selected pairs, wiring congestion near adjacent portions of the channel darkness can be alleviated.

(Example) Hereinafter, an example of the wiring method according to the present invention will be described according to the processing procedure. FIG. 1 shows the processing flow.

It is assumed that the layout within a block, the approximate location of each block, and the inter-block channels have already been defined.

5TEPI C Determining the general wiring route] Here, for each signal line, determine the channel to be passed through to connect between block terminals, and set the channel boundary terminal for that signal on the channel boundary that it crosses on the route. .

5TEP2 (Determination of channel wiring order) Determine the detailed wiring processing order for a plurality of inter-block channels based on their adjacency relationships.

5TEP3 (Estimate channel width) Find the degree of wiring congestion for each channel based on the approximate wiring route for each signal line,
Estimate the channel width from this value. The degree of wiring congestion and the channel width are related by an empirical formula.

5TEP4 (Calculation of block placement position) Calculate the block placement position using the estimated value of the channel width.

5TEP5 (Calculation of block terminal position) Calculate the digit 1 of the terminal from the block arrangement position.

This position is an estimated value that depends on the estimation accuracy of the channel width, but it is necessary for grouping the channel boundary terminals in the next 5TEP6, and if it has sufficient accuracy for that process. good.

5TEP6 (Grouping of channel boundary terminals) Channel boundary terminals are grouped for relative ordering.

This grouping will be explained in detail below with reference to FIG. FIG. 3 shows a part of FIG. 2, that is, adjacent blocks BL and BL2, a channel CH therebetween, and a channel CH1 orthogonal thereto. Now, B
Let Ll be the first block and BL2 be the second block,
CH4 is called a first channel, and CH1 is called a second channel.

The channel boundaries 4 run vertically. The y coordinates of the lower and upper ends of the channel boundary 4 are yl, respectively.

Let it be y2.

At this time, find a set of channel boundary terminals that satisfy the following conditions.

Nu: A signal in which the connection terminal in the second channel CH1 running in the vertical direction has at least one y-cosode WyT of 3'7≧y2, and none of which has 3'T<3'1. This is a group of terminals that require connection only in the direction of the first block BL1 side parallel to the channel boundary within the second channel CH1, and this is called the first group. .

N: A channel that connects to a signal that also goes to the connection terminal in channel CH1 and has one or more y-coordinates y≦y1, and no signal 5'7>'l2. Boundary terminal, 1st
A second block BL2 parallel to the channel boundary (a group in which a connection request is made only in the direction of lit) is called a second group.

In FIG. 3, terminal A is an example of set Nu.

In this example, terminal B is N. However, like terminal C, N
There are also things that do not belong to either category.

In addition, if the channel boundary runs horizontally, Shobara is 9
Consider a 0" rotation and perform the same processing as above.

5TEP7 (Determination of relative order of channel boundary terminals) 3rd
An example will be explained in which the channel boundary 4 in the figure runs in the vertical direction. Select one terminal nu from the channel boundary terminals belonging to the first group Nt3, and then select one terminal nu from the channel boundary terminals belonging to the first group Nt3.
Select one terminal nD from the channel boundary terminals belonging to o, and set a relative ordering for this pair of terminals such that nU is above nD.6 Next, n and n are respectively NU.

Remove this operation from N or NDD
U
Repeat until there are no more elements.

5. If the channel boundary runs in the horizontal direction, the coordinates are rotated by 90 degrees and the same processing as above is performed.

The above processing of 5TEP6 and 5TEP7 is executed for all channel boundaries.

5TEP8 (Detailed wiring) Extract the unprocessed channels of detailed wiring one by one.
Perform detailed wiring within channels. Processing order is 5TEP
Based on the order determined in step 2, all channels are executed and terminated. At this time, processing is performed in consideration of the relative positional order of the channel boundary terminals determined in 5TEP7.

FIG. 4 shows the wiring processing results of an embodiment according to the present invention.

In this example, the channel boundary terminals belonging to the first group Nυ, that is, the channel boundary terminals corresponding to the signals having connections only above the channel boundary 4 in the second channel CH1 in the vertical direction, are There are 3 channel boundary terminals, and the channel boundary terminal that corresponds to the channel boundary terminal belonging to the second group NO, that is, the signal that is connected only below the channel boundary 4 in the second channel CH1, is 81.
There are 3 pieces, ゜B and B, and the relative position ordering is 3.
This is done for each terminal pair. In the figure, in order to make the terminal pair easier to understand, the vertical wires of the pair are drawn in the same track within the vertical second channel. That is, (AI, B1), (A2.
This figure shows the case where pairs B2) and (A3.B3> are created.In actual wiring, they are not necessarily assigned to the same track like this, but each signal line of the terminal pair selected above is The degree of wiring congestion within the vertical channel can be suppressed to at most one track.

Note that if the wiring width of the signal line requires a space of one track or more, the number of channel boundary terminals corresponding to the wiring width is virtually increased to N.

Or N. If it is included in , it will be easy to extend the methods described so far.

[Effects of the Invention] As described above, according to the present invention, before detailed wiring, channel boundary terminals are classified into two groups under predetermined conditions, one terminal is selected from each group, and the pairs are assigned a relative position order. By doing so, wiring crossings near the channel boundaries can be kept to the minimum necessary, and an increase in the number of tracks in the channel can be suppressed.

In this case, when determining the relative positions of the channel boundary terminals, the first... If the partial order is equal to the smaller number of terminals in the second group, this will only be a very loose constraint for detailed wiring processing of the first channel, which has this channel boundary on the short side of the channel. The number of tracks in the channel can be made almost the same as in the case where the channel boundary terminals are not ordered.

Therefore, according to the present invention, it is possible to suppress unnecessary increase in channel width and improve the double integration density of a logic integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the processing flow of the present invention, FIG. 2 is a diagram showing an example of the structure of a chip, FIG. 3 is a diagram for explaining grouping of channel boundary terminals, and FIG. 4 is a diagram showing the implementation of the present invention. FIG. 5 is a diagram showing a wiring result according to an example, FIG. 5 is a diagram showing a conventional processing flow, and FIG. 6 is a diagram for explaining problems with the conventional method. 1 (BL, BL2....)...Block, 2
(cH, CH2,...)...channel, 3...
Human output circuit block, 4... Channel boundary, 5.6.
...Wiring, A to A, B-5-B3...Channel boundary terminal. Applicant's agent Patent attorney Suzue Takehiko0〒0 Diagram Condolences

Claims (1)

[Claims] A plurality of circuit blocks for which wiring design has been completed are arranged on a semiconductor chip, and a wiring area for connection between the circuit blocks is divided into a plurality of channels, and connections between the circuit blocks are made for each channel. In inter-block wiring processing for sequentially designing wiring, (a) means for setting channel boundary terminals at channel boundaries and determining an approximate wiring route for each signal line;
(b) means for estimating the position of the circuit block and the terminal position of the circuit block; (c) a first channel between the first and second phase-adjacent circuit blocks; Among the plurality of channel boundary terminals set for a signal line drawn out from the first channel side to the second channel side at the channel boundary between the second channels that are in contact with and orthogonal to the second channel, On the second channel side, a set of connection requests only from the channel boundary to a first direction parallel to the channel boundary is defined as a first group, and on the second channel side, from the channel boundary to the channel boundary. means for performing a process on the channel boundary of classifying a set of connection requests only in a parallel second direction as a second group;
) are selected from the channel boundary terminals of the first group and the second group to form terminal pairs, and for each terminal pair, the one belonging to the first group is In the direction of 1,
means for performing a process on the channel boundary to set a relative order relationship such that those belonging to the second group are located in the second direction; (e) the channel boundary set in (d); A wiring method for a semiconductor integrated circuit, comprising: means for wiring the channels while satisfying the relative positional relationship of terminals.