JP2006285445A - Layout design method, layout design program and layout design device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout design method, a layout design program and a layout design device capable of performing layout design in a short time while suppressing a bad effect of cross-talk or the like by performing rough wiring after estimating the load of wiring. <P>SOLUTION: Signal lines in which signals are transferred in the same time unit are classified to a simultaneous transition group based on cell arrangement information, signal lines belonging to the simultaneous transition group are assigned to Gcells at double or more wiring track pitches, and first delay information is assigned to the assigned signal lines for each Gcell to perform a timing analysis. The time unit for transferring the signals is reevaluated to update the simultaneous transition group, and whether signal lines belonging to the updated simultaneous transition group can be arranged at the double or more wiring track pitches or not. When they cannot be arranged at the double or more pitches, the signal lines are reassigned to the Gcells, and the processing is performed again. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal wiring technique in a semiconductor integrated circuit, and more particularly to a signal wiring technique in which crosstalk between signal wirings is suppressed.

  In the semiconductor integrated circuit disclosed in Patent Document 1, when the first signal wiring and the second signal wiring are wired at the initial stage of the layout design after the floor plan of the chip, the first signal wiring whose characteristics are to be taken into consideration is arranged. Wire as priority wiring. At this time, the wiring rule is set to a wiring pitch that is twice the normal wiring pitch. Next, the second signal wiring is wired at a normal wiring pitch. Thus, the second signal wiring is disposed so as to be interposed between the first signal wirings adjacent to each other.

  In addition, the layout verification apparatus disclosed in Patent Document 2 reads a netlist that does not have layout information, and a connection relationship or an arrangement relationship among functional blocks, input / output terminals of function blocks, I / O pads, and the like. Based on the above, according to the wiring rules determined by the circuit designer's experience and experimental data, the wiring that is likely to cause crosstalk belongs to the same group, and a layout rule that separates the wirings by a predetermined value or more and prevents them from running in parallel is provided.

Japanese Patent Application Laid-Open No. 2004-119921 JP 2003-44540 A

  However, in Patent Document 1, in order to wire the first signal wiring uniformly at twice the wiring pitch, the wiring area must be secured by a layout design rule that is looser than the original layout design rule. A wiring area larger than that required for wiring with a normal wiring pitch is required. In addition, although the second signal wiring that is wired at a normal wiring pitch can be routed between the first signal wirings, the first signal wiring is wired in consideration of the wiring position of the second signal wiring. Therefore, the inter-line region of the first signal wiring cannot be used sufficiently effectively, and there is a possibility that the non-wired inter-line region remains as a dead space. Contrary to the demand for high-density wiring, an unwired dead space remains, which may cause a problem in that a highly integrated layout design cannot be performed.

  In addition, when the number of signal wirings for which characteristics are to be considered further increases in addition to the first signal wiring, each signal wiring is wired at twice the wiring pitch. In this case, it is necessary to secure a wiring area having a double wiring pitch for each signal wiring, and there is a possibility that the dead space of the unwiring may further increase.

  Moreover, in the said patent document 2, generation | occurrence | production of crosstalk is suppressed by putting together the wiring which is easy to produce crosstalk into the same group, keeping the distance between wirings, and not running in parallel. However, since the wiring grouping is performed on the net list at the logic design stage that does not have layout information, the accuracy may be lower than the characteristics after the actual layout design. This is because the wiring resistance component and wiring capacitance component of the laid out wiring are not taken into consideration.

  The present invention has been made in view of the problems of the background art, and in layout design, after estimating the load of wiring and performing schematic wiring according to the timing of signal change, crosstalk between signal wirings and the like An object of the present invention is to provide a layout design method, a layout design program, and a layout design apparatus that can perform layout design in which the adverse effects of the above are suppressed in a short time.

  In order to achieve the above object, a layout design method and a layout design program according to the present invention are layout design methods for performing schematic wiring in estimating a wiring path of a signal wiring, and the schematic wiring is based on cell arrangement information. , A step of grouping signal wirings in which signals transition in the same time unit among time units of a predetermined time width as a simultaneous transition group, and for signal wirings belonging to the simultaneous transition group, a wiring track pitch of twice or more, Assigning signal wiring to a general wiring unit section partitioned for each predetermined number of general wirings, and according to the number of signal wirings adjacent to the assigned signal wiring for each general wiring unit section, A step of providing first delay information and a timing analysis considering the first delay information. Re-evaluating the time unit in which the signal in the signal wiring transitions and updating the simultaneous transition group; and for each of the updated simultaneous transition groups, the number of signal wirings belonging to each of the schematic wiring unit sections is doubled Determining whether or not the wiring track pitch can be routed, and assigning the signal wiring to the general wiring unit section when it is determined in the determination step that the wiring track pitch cannot be doubled or more. It returns to a step and it processes again.

  In the layout design method and the layout design program of the present invention, when performing rough wiring for estimating the wiring path of the signal wiring, the signal transitions in the same time unit among the time units having a predetermined time width based on the cell arrangement information. Signal wiring to be grouped as a simultaneous transition group, and for signal wirings belonging to the simultaneous transition group, the signal wiring is divided into a predetermined number of schematic wiring units with a wiring track pitch of twice or more. And assigning first delay information to the assigned signal wiring in accordance with the number of adjacent signal wirings for each schematic wiring unit section, and then performing timing analysis in consideration of the first delay information Re-evaluate the time unit that the signal in the wiring transitions to update the concurrent transition group and update the same Determining for each of the transition groups, each global routing unit blocks, whether or not the signal lines that belong can interconnect at least twice the wire track pitch. If it is determined that wiring cannot be performed with a wiring track pitch of twice or more, the signal wiring is reassigned to the general wiring unit section and the processing is performed again.

  The layout design apparatus according to the present invention is a layout design apparatus that performs schematic wiring in estimating a wiring path of a signal wiring. In performing schematic wiring, a layout design apparatus of a time unit having a predetermined time width is provided based on cell arrangement information. Among them, a grouping unit that groups signal wirings in which signals transition in the same time unit as a simultaneous transition group, and a signal wiring that belongs to the simultaneous transition group has a predetermined number of signal wirings with a wiring track pitch of twice or more. The first delay information is assigned according to the number of adjacent signal wirings to the assigned signal wiring for each general wiring unit section, and the allocation unit allocated to the general wiring unit section divided for each general wiring number. By the first delay information giving unit to be given and the timing analysis in consideration of the first delay information, The update unit that re-evaluates the time unit in which the signal in the signal wiring transitions and updates the simultaneous transition group, and the signal wirings that belong to each of the approximate wiring unit sections more than double for each of the updated simultaneous transition group And a determination unit that determines whether or not wiring can be performed at a wiring track pitch, and when the determination unit determines that wiring cannot be performed at a wiring track pitch that is twice or more, processing is performed again. To do.

  In the layout design apparatus of the present invention, when performing schematic wiring, a grouping unit uses signal wiring in which a signal transitions in the same time unit among time units of a predetermined time width as a simultaneous transition group based on cell arrangement information. Divide into groups. Then, the assignment unit assigns the signal wiring to the general wiring unit section divided by a predetermined number of the general wiring numbers with respect to the signal wiring belonging to the simultaneous transition group, with the wiring track pitch being twice or more, and the first delay information The assigning unit assigns the first delay information to the assigned signal lines in accordance with the number of adjacent signal lines for each schematic wiring unit section. Further, by the timing analysis in consideration of the first delay information by the update unit, the time unit in which the signal in the signal wiring transitions is reevaluated to update the simultaneous transition group, and each of the updated simultaneous transition groups by the determination unit On the other hand, for each of the schematic wiring unit sections, it is determined whether or not the signal wiring to which it belongs can be wired at a wiring track pitch that is twice or more. If it is determined that wiring cannot be performed at a wiring track pitch of twice or more, the process is performed again.

  As a result, in the schematic wiring that is an estimate of the wiring path before the actual wiring, in addition to the signal transition timing in the logic design, the first delay information corresponding to the number of adjacent signal wirings is given to the signal wiring. Can do. In the initial stage of layout design, adverse effects such as a crosstalk phenomenon at a transition timing close to the actual wiring state can be evaluated, and rough wiring with less influence of signal transition noise can be performed.

  In addition, timing analysis is performed by adding first delay information to the signal wiring, and signal wirings in which signals transition in the same time unit can be grouped into simultaneous transition groups. By taking measures such as separating at a wiring track pitch of twice or more, adverse effects such as crosstalk between wirings can be effectively suppressed.

  The simultaneous transition group is updated according to the timing analysis performed after the first delay information is added, and the process of changing the assignment of the signal wiring to the general wiring unit section is repeated again. By repeating this process, it is possible to prevent an adverse effect such as a crosstalk phenomenon at a transition timing close to the actual wiring at the schematic wiring stage.

  By performing schematic wiring with little influence of signal transition noise, the probability of re-wiring due to signal transition noise in subsequent detailed wiring can be suppressed. In this case, the wiring process may be repeated at the stage of the rough wiring, but the processing time is shorter in the rough wiring process than in the detailed wiring process. The wiring processing time of signal wiring can be shortened, and the time required for layout design can be shortened.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a layout design method, a layout design program, and a layout design apparatus according to the present invention will be described below in detail with reference to the drawings based on FIGS.

  FIG. 1 shows a flow diagram when performing schematic wiring after circuit cell placement in a layout design method or layout design program according to an embodiment of the present invention.

  After the circuit cell is arranged in a predetermined region such as a chip in the semiconductor integrated circuit (S1), second delay information is given to the estimated signal wiring according to the distance between the signal terminals arranged in the circuit cell and connected by the signal wiring. (S2). In accordance with the second delay information, the transition timing of the signal propagating through the signal wiring is estimated, and the signal wiring whose signal level transitions in the same time unit is grouped into simultaneous transition groups (S3). In assigning each signal wiring to a schematic wiring unit section (hereinafter abbreviated as Gcell) and determining the signal path connecting the signal terminals, the wiring priority for each signal wiring is determined (S4).

  For example, it is preferable to assign Gcell preferentially to a critical path through which a clock signal or the like propagates. This is because it is preferable to assign the Gcell constituting the shortest path so that the signal propagation delay is minimized. In addition, it is preferable that a Gcell is preferentially assigned to a signal wiring having a long total wiring length. This is because a long wiring has a high probability of crossing the wiring paths of a large number of signal wirings, and therefore, if it is allocated to Gcell in advance, other signal wirings can be smoothly allocated to Gcell.

  FIG. 2 exemplifies wiring path candidates for signal wiring according to the circuit cell arrangement on the chip. It is assumed that circuit cells A, B, and C are arranged on the chip 1. Now, consider the wiring path of the signal wiring connecting the signal terminal P1 of the circuit cell A and the signal terminal P2 of the circuit cell C. It is assumed that the wiring path candidates can be three types of wiring paths 11, 12, and 13. The wiring paths 11 and 12 are both the shortest paths. The wiring path 13 is a bypass path that bypasses the circuit cell B. In each wiring path, the chip 1 is partitioned by a Gcell in a grid pattern for each predetermined number of wiring tracks in the X / Y direction. The wiring path is performed by selecting Gcell and assigning signal wiring to Gcell. Due to the cell arrangement, the wiring paths 11 and 12 are preferentially assigned from the signal wiring that requires the shortest path.

  FIG. 3 shows that the second delay information estimated in the procedure (S2) is given in accordance with the signal transition timing obtained in the already established logic design stage or in the logic design stage. Thus, the estimated signal transition timing is shown for each signal wiring A [12: 0], B [7: 0], C [1: 0], and D [1: 0]. The clock cycle TCK is divided into seven by a predetermined time width, and the divided time widths are set as time units T1 to T7, and the time units T1 to T7 to which the transition timing of each signal wiring belongs are shown. . From FIG. 3, the signal level of the signal wiring A [12: 0] changes in the time unit T2. The signal level of the signal wiring B [7: 0] changes in the time unit T4. The signal level of the signal wiring C [1: 0] transitions in the time unit T6. The signal wiring D [1: 0] is an asynchronous signal, and the signal level transition timing is not limited to a specific time unit.

  As shown in the procedure (S3), signal wirings that undergo signal level transitions in the same time unit are grouped as simultaneous transition groups. The signal wiring A [12: 0] is grouped into the simultaneous transition group GT2, the signal wiring B [7: 0] is grouped into the simultaneous transition group GT4, and the signal wiring C [1: 0] is grouped into the simultaneous transition group GT6. . At this stage, the second delay information, which is an approximate value, is added to estimate the transition timing of the signal level, so that the name does not greatly deviate from the transition timing predicted in the logic design.

  In FIG. 1, after the procedure (S4), the signal wirings belonging to the simultaneous transition group are allocated to Gcell as wiring track pitches of N times (N ≧ 2) (S5). Here, N is a natural number of 2 or more, and N-fold pitch means allocation to every N wiring tracks. As a result, signal wirings that belong to the simultaneous transition group and whose signal level transitions in the same time unit have a wiring track pitch of N times each other, that is, have (N-1) wiring track regions between the wiring paths. A wiring track is assigned. It is possible to prevent a so-called crosstalk phenomenon in which a signal level transition of one signal wiring adversely affects the other signal wiring in a signal wiring having overlapping timings in the same time unit. It is possible to prevent malfunction such as a signal level transition at a timing earlier than the original timing or a transition after a delay from the original timing.

  In this case, signal wirings belonging to different simultaneous transition timings or asynchronous signal wirings can be assigned to adjacent wiring tracks. This is because signal wirings having different transition timings do not overlap with each other in signal level transitions, and malfunction due to a crosstalk phenomenon caused by signal level transitions does not occur.

  Allocation of signal wiring to Gcell needs to be performed after observing the allocation rules in Gcell. That is, if the total number of wirings in the Gcell exceeds the specified number, and / or if there are no remaining wiring tracks allocated at the N-times wiring track pitch in the Gcell, allocation of signal wiring to the Gcell is not allowed. It is determined that it is possible (S6: Y), and assignment to wiring tracks belonging to other Gcells is performed while leaving signal wirings with high priority (S7). When the total number of wirings is within the specified number or / and the number of wiring tracks to be allocated with a wiring track pitch of N times (S6: N), as long as there is a signal wiring to be allocated (S8: N), Returning to the procedure (S5), the allocation process is continued.

  FIG. 4 exemplifies the Gcell with respect to the wiring track arranged in the Y direction of the chip 1 (FIG. 2). In the vertical direction, of the six wiring layers M1 to M6, there are three wiring layers M2, M4, and M6 that are wiring in the Y direction. In the horizontal direction, there are ten tracks YT1 to YT10 due to the layout configuration on the plane. A wiring track is formed at the intersection of the vertical track and the horizontal track. Ten wiring tracks are formed for each of the wiring layers M2, M4, and M6, and a total of 30 wiring tracks are formed. If the horizontal track is the basic pitch, the vertical track has a double pitch.

  FIG. 5 shows signal wirings A [12: 0], B [7: 0], C [1: 0], and D [1: 0] grouped into three simultaneous transition groups in FIG. The state assigned to the wiring track in one Gcell by (S5)-(S8) is shown. In FIG. 5, it is assumed that N = 2 in the procedure (S5), and signal wirings belonging to the simultaneous transition group are assigned to wiring tracks at a wiring track pitch of twice.

  The signal wirings A [12: 0] grouped into the simultaneous transition group GT2 are assigned to wiring tracks every other wiring track. Five lines are allocated to the wiring layers M2 and M4, and three lines are allocated to the wiring layer M6. Further, the signal wiring B [7: 0] grouped in the simultaneous transition group GT4 is also assigned to the wiring track every other wiring track. Five lines are allocated to the wiring layer M2, and three lines are allocated to the wiring layer M4. Further, the signal wiring C [1: 0] grouped in the simultaneous transition group GT6 is also assigned to the wiring track every other wiring track. Two lines are allocated to the wiring layer M4. Two asynchronous signals D [1: 0] are assigned to the wiring layer M6.

  Signal wirings belonging to the same simultaneous transition group are assigned to wiring tracks at twice the wiring track pitch, and signal wirings belonging to different simultaneous transition groups are assigned to adjacent wiring tracks. It is possible to prevent malfunction due to a crosstalk phenomenon between signal wirings having the same transition timing in a time unit. Furthermore, signal wirings having different transition timings that are unlikely to cause a crosstalk phenomenon can be assigned to adjacent wiring tracks. By assigning signal wiring that may cause crosstalk to a separate wiring track pitch while assigning signal wiring that is not likely to cause crosstalk to adjacent wiring track pitch, the signal wiring caused by crosstalk Thus, it is possible to accurately determine the wiring path that can prevent the malfunction in a compact wiring area from the stage of the rough wiring.

  In the procedure (S8) of FIG. 1, when all signal wirings are assigned to Gcell (S8: Y), timing analysis is performed after giving first delay information to each signal wiring for each Gcell (S9). (S10).

  Here, the provision of the first delay information in the procedure (S9) is to estimate the number of signal wirings assigned to the adjacent wiring track of the Gcell to which the target signal wiring is assigned in the Gcell. The average number is calculated, and calculation is performed with a delay coefficient obtained in advance according to the calculated number.

  FIG. 6 shows a formula for calculating the average number α of adjacent signal wirings. FIG. 6 is an estimate for a single layer wiring track. When there are multiple wiring layers, the average number α of adjacent signal wirings in the Gcell is calculated by performing the same calculation for each layer and averaging.

  FIG. 6 shows a calculation formula when signal wiring is allocated to more than half of the total wiring tracks. When the number of wiring tracks to which signal wiring is assigned is less than half of the total number, it is assumed that no signal wiring is assigned to adjacent wiring tracks. When no signal wiring is assigned to the adjacent wiring track, it is evaluated that the influence of delay due to parasitic resistance, parasitic capacitance, etc. between the signal wirings running in parallel is minimal. In the schematic wiring, since the influence of the delay in this case can be ignored, it is not considered in the calculation of the first delay information.

If the total number of wiring tracks per layer of Gcell is n and the number of signal wirings to be assigned is s, the average of the signal wirings assigned to the wiring tracks adjacent to the wiring tracks to which the signal wirings are assigned The number α is
α = 2 × (2 × s−n) / s is calculated. FIG. 6 illustrates a case where there are seven wiring tracks. As a precondition, signal wirings are assigned to four wiring tracks at double pitch. In response to the addition of the signal wiring to the wiring track during this period, two wires are adjacent inside the assigned wiring track, and one wire is adjacent on both sides. Thereby, the above equation is obtained.

  For the average number α, the length of the signal wiring L, the unit resistance value RG for each wiring layer, and the unit capacitance value CT determined by the conditions around the signal wiring, according to a predetermined relational expression, Delay information of the signal wiring is calculated. The first delay information is obtained by integrating the delay information for each Gcell along the wiring path shown in FIG.

  In the procedure (S10) of FIG. 1, since the timing analysis is performed on the signal wiring to which the first delay information is added, the signal level transition timing for each signal wiring is different from the timing in FIG. The simultaneous transition group is updated according to the transition timing obtained as a result of the analysis (S11).

  FIG. 7 illustrates the transition timing of the signal level analyzed by the procedure (S10). Compared to the transition timing shown in FIG. 3, the transition timing is delayed for the signal wirings A [12: 8] and A [6: 0] except the signal wiring A [7], and the simultaneous transition group is changed from the group GT2. Shift to GT3. Also, the signal wiring B [6: 0] except for the signal wiring B [7] has a faster transition timing, and the simultaneous transition group shifts from the group GT4 to GT3. As a result, it can be seen that 19 signal wirings are concentrated in the simultaneous transition group GT3.

  In FIG. 1, after the simultaneous transition group is updated (S11), it is checked whether or not the signal wirings belonging to the simultaneous transition group can be wired with a wiring track pitch of N times (S12).

  As shown in FIG. 8, since 19 signal wirings are concentrated in the simultaneous transition group GT3, in the procedure (S8) stage, Gcell ( In FIG. 5), multiple signal wirings belonging to the simultaneous transition group GT3 cannot be double pitch wiring.

  It becomes clear that double-pitch wiring is not possible (S12: Y), and the procedure returns to procedure (S4), and priority is set for signal wiring as necessary based on the updated simultaneous transition group (S4). The Gcell is assigned again (S5), the signal wiring is assigned to the Gcell while keeping the assignment rules in the Gcell (S6 to S8), the first load information is given (S9), and the timing analysis is performed. (S10) and repeat the analysis.

  As a result, it is possible to analyze the transition timing of the signal level after estimating the delay information given to the signal wiring at the schematic wiring stage, and the crosstalk phenomenon between the signal wirings in which the signal level transitions in the same time unit does not occur. Allocation of signal wirings with different transition timings while realizing wiring paths to adjacent wiring tracks makes it possible to determine wiring paths that effectively use the wiring area without wasteful space. Can be performed accurately.

  Next, when there are a plurality of simultaneous transition groups, a method of assigning signal wirings belonging to each group to wiring tracks will be described with reference to FIGS.

  Consider a circuit from the flip-flop circuit FF1 shown in FIG. 9 to the flip-flop circuit FF2 via the logic circuits L1 to L5. The flip-flop circuit FF1 and the logic circuits L1 to L5 are connected to the next stage circuit by signal wirings N1 to N6, respectively. A signal output from the flip-flop circuit FF1 propagates from the signal wiring N1 to the flip-flop circuit FF2 via the logic circuits L1 to L5.

  The state of signal level transition timing is shown in FIG. Due to the propagation delay in each circuit and the propagation delay in the signal wiring, the level transition timings of the signals S1 to S6 propagating through the signal wirings N1 to N6 are sequentially delayed. Here, the propagation delay in each circuit is a delay determined in the logic design stage. The propagation delay in the wiring is, for example, the delay due to the second delay information given in the procedure (S2) in FIG. 1 or the first delay information given in the procedure (S9) in FIG. It is.

  The simultaneous transition group is performed by grouping signal wirings belonging to time units having the same signal level transition timing. In FIG. 10, signals S1 and S2, signals S3 and S4, and signals S5 and S6 are grouped as belonging to simultaneous transition groups GA, GB, and GC, respectively. Let it be grouped into three simultaneous transition groups.

  FIG. 11 shows a method of assigning signal wirings belonging to each group to wiring tracks. In step I, the simultaneous transition group GA is selected, and signal wirings belonging to the simultaneous transition group GA are assigned to twice the wiring track pitch.

  In Step II, the simultaneous line group GB is selected, and signal wirings belonging to the simultaneous transition group GB are assigned to twice the wiring track pitch. At this time, the wiring track pitch is also doubled from the wiring track of the signal wiring belonging to the previously assigned simultaneous transition group GA. This is because the simultaneous transition group GA and the simultaneous transition group GB are adjacent groups, and depending on the signal wiring between the groups, there is a possibility of being adversely affected by the crosstalk phenomenon. Specifically, for example, the signal wiring N2 and the signal wiring N3 are applicable.

  In Step III, the simultaneous line group GC is selected, and signal wirings belonging to the simultaneous transition group GC are assigned to twice the wiring track pitch. At this time, the wiring track pitch of the signal wiring belonging to the previously assigned simultaneous transition group GB is also doubled. This is because the simultaneous transition group GB and the simultaneous transition group GC are adjacent groups and may be adversely affected by the crosstalk phenomenon depending on the signal wiring between the groups. Specifically, for example, the signal wiring N4 and the signal wiring N6 are applicable. Since the simultaneous transition group GA and the simultaneous transition group GC are not adjacent groups, there is little possibility of being adversely affected by the crosstalk phenomenon, and the signal wirings belonging to the simultaneous transition group GA and the GC are 1 time. Assigned to wiring track pitch.

  In step IV, the remaining signal wiring X is assigned to a wiring track. In this case, since the signal wiring X is a signal wiring having a transition timing different from that of any of the simultaneous transition groups GA to GC, the wiring track pitch of the signal wiring X belonging to each of the groups GA to GC is a single wiring track pitch. can do.

  As a result, even when there are a plurality of simultaneous transition groups and there is a concern about the adverse effects due to the crosstalk phenomenon in the signal wiring between the groups, the wiring track pitch of the signal wiring is set to 2 between predetermined groups such as adjacent groups. By setting the pitch to be twice or more, adverse effects due to the crosstalk phenomenon can be prevented.

  FIG. 12 is a configuration diagram of the layout design apparatus according to the embodiment. The layout design apparatus 10 includes a memory 30, a magnetic disk device 40, a display device (hereinafter abbreviated as CRT) 50, and a keyboard via a bus 90 centered on a central processing unit (hereinafter abbreviated as CPU) 20. 60, a communication line 70 such as the Internet, and an external storage medium driving device 80 are connected to each other, and an external storage medium 100 such as a CDROM or a magnetic medium is detachably installed in the external storage medium driving device. is there.

  The program for executing the layout design procedure shown in FIG. 1 is not only recorded in the memory 30 or the magnetic disk device 40, but also when it is recorded in the external storage medium 100 such as a CDROM or a magnetic medium. The data is recorded in the memory 30 and the magnetic disk device 40 via the device 80 or directly transferred to the CPU 20. Further, with respect to circuit cell arrangement information and Gcell, the number of wiring tracks, the wiring length L of the signal wiring, the unit resistance value RG for each wiring layer, the unit capacitance value CT determined by the conditions around the signal wiring, and the first delay information Various information such as a relational expression for calculating the value is recorded in the magnetic disk device 40, an external storage medium 80 such as a CDROM, a magnetic medium, and the like, and is referred to as necessary by a command from the CPU 20 according to the processing of the program. Is done. Then, according to the flow of FIG. 1, the procedure for rough wiring, the result of timing analysis, the allocation status of signal wiring to Gcell, etc. are confirmed by the confirmation means such as CRT 50, and then input instruction from the keyboard 60 etc. The process proceeds according to

  In addition, via a communication line 70 such as the Internet, it is also possible to exchange computer programs and various information for realizing the flow shown in FIG. 1 with other systems.

  As described above in detail, according to the layout design method, the layout design program, and the layout design apparatus according to the present embodiment, the transition timing of the signal in the logical design in the schematic wiring that is the estimation of the wiring path before the actual wiring. In addition, the first delay information corresponding to the number of adjacent signal lines can be given to the signal lines. Timing analysis can be performed at the transition timing close to the actual wiring at the stage of rough wiring. An adverse effect such as a crosstalk phenomenon caused by a close transition timing can be evaluated at the initial stage of layout design, and a schematic wiring with little influence of signal transition noise can be performed.

  In addition, since the timing analysis is performed by giving the first delay information to the signal wiring, the signal wiring in which the signal transitions in the same time unit at the transition timing close to the actual wiring can be grouped into the simultaneous transition group. By separating the signal wirings belonging to the simultaneous transition group at a wiring track pitch of twice or more, adverse effects due to signal transition noise such as a crosstalk phenomenon between the wirings can be effectively suppressed.

  As a result of the timing analysis performed after adding the first delay information, if the signal wiring belonging to the simultaneous transition group increases and the signal wiring belonging to the simultaneous transition group cannot be routed at a double pitch, the signal to the Gcell is again transmitted. The timing analysis is performed after the wiring assignment is changed and the first delay load information is reapplied, and the process of updating the simultaneous transition group and determining whether or not the signal wiring is possible is repeated. By repeating this process, it is possible to perform schematic wiring having signal wiring that is less adversely affected by signal transition noise such as a crosstalk phenomenon with respect to transition timing close to transition timing in actual wiring.

  By performing schematic wiring with little influence of signal transition noise, the probability of re-wiring due to signal transition noise in subsequent detailed wiring can be suppressed. In this case, the wiring process may be repeated at the stage of the rough wiring, but the processing time is shorter in the rough wiring process than in the detailed wiring process. The wiring processing time of signal wiring can be shortened, and the time required for layout design can be shortened.

In addition, this invention is not limited to the said embodiment, It cannot be overemphasized that various improvement and deformation | transformation are possible within the range which does not deviate from the meaning of this invention.
For example, in the present embodiment, the case where the signal wiring is grouped into simultaneous transition groups according to the signal level transition timing in the schematic wiring stage has been described, but the present invention is not limited to this, In the detailed wiring stage in addition to the wiring stage, it is also possible to group the signal wirings into a simultaneous transition group and wire the signal wirings belonging to the simultaneous transition group at a wiring track pitch of N times.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Appendix 1) A layout design method for performing schematic wiring in estimating the wiring path of signal wiring,
The schematic wiring is
Grouping the signal wirings in which signals transition in the same time unit among time units of a predetermined time width based on cell arrangement information as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, assigning the signal wirings to a general wiring unit section divided for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
Assigning first delay information to the assigned signal wirings according to the number of adjacent signal wirings for each of the schematic wiring unit sections;
Re-evaluating the time unit in which a signal in the signal wiring transitions by timing analysis in consideration of the first delay information and updating the simultaneous transition group;
For each of the updated simultaneous transition groups, determining, for each of the schematic wiring unit sections, whether or not the signal wiring to which it belongs can be wired at the wiring track pitch of twice or more,
A layout design method comprising: returning to the step of assigning the signal wiring to a schematic wiring unit section and performing the processing again when it is determined in the determining step that wiring cannot be performed at the wiring track pitch of twice or more.
(Supplementary Note 2) In the step of grouping the signal wirings based on the arrangement information of the cells, second delay information is given to the signal wirings according to the distance between the terminals of the cells connected by the signal wirings. The layout design method according to appendix 1, wherein:
(Supplementary note 3) The layout design method according to supplementary note 1, wherein, in the step of assigning the signal wiring to the schematic wiring unit section, the assignment is performed according to priority order information assigned to the signal wiring.
(Supplementary note 4) The layout design method according to supplementary note 3, wherein the priority order information is critical path information or / and wiring length information.
(Supplementary Note 5) When there are a plurality of the simultaneous transition groups, in the step of assigning the signal wiring to the schematic wiring unit section, the signal wiring is between the simultaneous transition groups in which signals transition in the adjacent time units. The layout design method according to appendix 1, wherein the layout track pitch is assigned twice or more.
(Supplementary Note 6) The step of providing the first delay information to the signal wiring includes:
Estimating the number of adjacent signal wirings based on the number of signal wirings assigned to the schematic wiring unit section;
And a step of calculating first delay information in the signal wiring based on a wiring length, a resistance coefficient, and a capacitance coefficient of the signal wiring in addition to the number of the adjacent signal wirings. The layout design method described in 1.
(Supplementary note 7) The layout design method according to supplementary note 6, wherein the schematic wiring unit section includes a plurality of stacked wiring layers in the wiring track.
(Appendix 8) A layout design program for performing schematic wiring in estimating the wiring path of signal wiring,
The schematic wiring is
Grouping the signal wirings in which signals transition in the same time unit among time units of a predetermined time width based on cell arrangement information as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, assigning the signal wirings to a general wiring unit section divided for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
Assigning first delay information to the assigned signal wirings according to the number of adjacent signal wirings for each of the schematic wiring unit sections;
Re-evaluating the time unit in which a signal in the signal wiring transitions by timing analysis in consideration of the first delay information and updating the simultaneous transition group;
For each of the updated simultaneous transition groups, determining, for each of the schematic wiring unit sections, whether or not the signal wiring to which it belongs can be wired at the wiring track pitch of twice or more,
A layout design program for returning to the step of assigning the signal wiring to the general wiring unit section and performing the process again when it is determined in the determining step that the wiring cannot be performed at the wiring track pitch of twice or more. .
(Supplementary note 9) A layout design apparatus for performing schematic wiring in estimating a wiring path of a signal wiring,
In performing the general wiring,
Based on the cell arrangement information, a grouping unit that groups the signal wirings in which signals transition in the same time unit among time units of a predetermined time width as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, an allocation unit that allocates the signal wirings to a general wiring unit section that is partitioned for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
A first delay information providing unit that assigns first delay information to the assigned signal wiring in accordance with the number of adjacent signal wirings for each of the schematic wiring unit sections;
An update unit that updates the simultaneous transition group by re-evaluating the time unit in which the signal in the signal wiring transitions by timing analysis in consideration of the first delay information;
For each of the updated simultaneous transition groups, a determination unit for determining whether or not the signal wiring belonging to each of the schematic wiring unit sections can be wired at the wiring track pitch of twice or more, and
A layout design apparatus that performs processing again when it is determined in the determination unit that wiring cannot be performed at a wiring track pitch of twice or more.

It is a flowchart of an embodiment. It is a figure which illustrates the wiring route in Gcell arrangement map on a chip, and outline wiring. It is a figure which illustrates the simultaneous delay group obtained by giving the 2nd delay information based on logic design information or based on cell arrangement information. It is a figure which illustrates Gcell about the wiring track of a chip Y direction. It is a figure which illustrates the allocation state to the wiring track of the signal wiring based on the simultaneous transition group of FIG. It is a figure which shows calculation of the number of the signal wiring adjacent within Gcell. It is a figure which illustrates the simultaneous delay group which gives 1st delay information and is obtained by timing analysis. FIG. 8 is a diagram reflecting the timing analysis result of FIG. 7 in the assignment of FIG. It is a circuit diagram for demonstrating grouping to a simultaneous transition group. It is a figure which illustrates grouping to the simultaneous transition group of each signal wiring of FIG. FIG. 11 is a diagram illustrating assignment of a plurality of simultaneous transition groups grouped in FIG. 10 to wiring tracks. It is a block diagram which shows the layout design apparatus in embodiment.

Explanation of symbols

1 chip 10 layout design apparatus 11, 12, 13 wiring path 20 central processing unit (CPU)
30 Memory 40 Magnetic disk device 50 Display device (CRT)
60 Keyboard 70 Communication line 80 External storage medium driving device 90 Bus A, B, C Circuit cells A [12: 0], B [7: 0], C [1: 0], D [1: 0] Signal wiring Gcell General wiring unit sections GT2, GT3, GT4, GT6, GA, GB, GC Simultaneous transition groups M1 to M6 Wiring layer P1, P2 Signal terminals YT1 to YT10 Track

Claims (5)

A layout design method for performing schematic wiring in estimating the wiring path of signal wiring,
The schematic wiring is
Grouping the signal wirings in which signals transition in the same time unit among time units of a predetermined time width based on cell arrangement information as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, assigning the signal wirings to a general wiring unit section divided for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
Assigning first delay information to the assigned signal wirings according to the number of adjacent signal wirings for each of the schematic wiring unit sections;
Re-evaluating the time unit in which a signal in the signal wiring transitions by timing analysis in consideration of the first delay information and updating the simultaneous transition group;
For each of the updated simultaneous transition groups, determining, for each of the schematic wiring unit sections, whether or not the signal wiring to which it belongs can be wired at the wiring track pitch of twice or more,
A layout design method comprising: returning to the step of allocating the signal wiring to the schematic wiring unit section and performing the process again when it is determined in the determining step that wiring cannot be performed at the wiring track pitch of twice or more. .   When there are multiple simultaneous transition groups, in the step of assigning the signal wiring to the schematic wiring unit section, the signal wiring is more than doubled between the simultaneous transition groups in which signals transition in adjacent time units. 2. The layout design method according to claim 1, wherein the layout design method is assigned to a wiring track pitch. The step of providing the first delay information to the signal wiring is as follows:
Estimating the number of adjacent signal wirings based on the number of signal wirings assigned to the schematic wiring unit section;
And a step of calculating first delay information in the signal wiring based on a wiring length, a resistance coefficient, and a capacitance coefficient of the signal wiring in addition to the number of the adjacent signal wirings. 2. The layout design method according to 1. A layout design program for performing schematic wiring in estimating the wiring path of signal wiring,
The schematic wiring is
Grouping the signal wirings in which signals transition in the same time unit among time units of a predetermined time width based on cell arrangement information as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, assigning the signal wirings to a general wiring unit section divided for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
Assigning first delay information to the assigned signal wirings according to the number of adjacent signal wirings for each of the schematic wiring unit sections;
Re-evaluating the time unit in which a signal in the signal wiring transitions by timing analysis in consideration of the first delay information and updating the simultaneous transition group;
For each of the updated simultaneous transition groups, determining, for each of the schematic wiring unit sections, whether or not the signal wiring to which it belongs can be wired at the wiring track pitch of twice or more,
A layout design program for returning to the step of assigning the signal wiring to the general wiring unit section and performing the process again when it is determined in the determining step that the wiring cannot be performed at the wiring track pitch of twice or more. . A layout design device that performs schematic wiring in estimating the wiring path of signal wiring,
In performing the general wiring,
Based on the cell arrangement information, a grouping unit that groups the signal wirings in which signals transition in the same time unit among time units of a predetermined time width as a simultaneous transition group;
For the signal wirings belonging to the simultaneous transition group, an allocation unit that allocates the signal wirings to a general wiring unit section that is partitioned for each predetermined number of general wiring lines, with a wiring track pitch of twice or more;
A first delay information providing unit that assigns first delay information to the assigned signal wiring in accordance with the number of adjacent signal wirings for each of the schematic wiring unit sections;
An update unit that updates the simultaneous transition group by re-evaluating the time unit in which the signal in the signal wiring transitions by timing analysis in consideration of the first delay information;
For each of the updated simultaneous transition groups, a determination unit for determining whether or not the signal wiring belonging to each of the schematic wiring unit sections can be wired at the wiring track pitch of twice or more, and
A layout design apparatus that performs processing again when it is determined in the determination unit that wiring cannot be performed at a wiring track pitch of twice or more.

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