JPH10256375A - Arrangement of cells for integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the concentration of wirings on a local area and make available such an arrangement of cells which allows an easy achievement of an upper limit value of a delay time after the wiring is done by distributing the cells according to the ratio of the number of virtual wiring grid lines used to the total number of the lines. SOLUTION: In order to divide a substrate 10a, a plurality of cut lines are set in the vertical and the horizontal directions. With the substrate 10a deemed as one cell arrangement region, all the cells 8a-8j in a circuit are distributed in the cell arrangement region constituted of the entire substrate 10a. At that time, care should be taken so that the number of signal lines 9a-9k which cross a cut line 13b may be minimum. At the same time, the ratio of the number of virtual wiring grid lines used to the total number of the lines should be nearly the same in all divided cell arrangement regions. Furthermore, the sum of the areas of the cells distributed to two divided cell arrangement regions should not exceed the total area of cells which can be located in the same divided cell arrangement regions. By this method, a local wiring concentration wherein wirings are gathered only in one part of the substrate 10a can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for arranging cells constituting an integrated circuit device, and more particularly to a method for arranging cells by a mini-cut method.

[0002]

2. Description of the Related Art The design of a physical layout on a chip of an integrated circuit device is performed in units of "cells" which express one integrated function. The layout design using such cells is automatically performed according to various algorithms. One of the methods for efficiently arranging and wiring such cells on a chip is a method called a mini-cut method.

FIGS. 10A and 10B schematically show a flow of cell layout by the mini-cut method. Hereinafter, the mini-cut method will be briefly described.

First, as shown in FIG. 10A, cells CL constituting this integrated circuit device are arranged in a cell arrangement area CA. Next, the cell arrangement area CA is divided into two areas DRA and DRB by a cut line CTa. In these two regions DRA and DRB, the cell density (the ratio of the sum of the areas of the cells allocated in the cell placement region to the cell area that can be placed in the cell placement region) is equal, and the cut line CTa The cell CL is distributed to the regions DRA and DRB such that the number of signal lines intersecting with the cells CL is minimized.

[0005] When the cell CL allocation process based on the cut line CTa is completed, another cut line is selected.

That is, as shown in FIG. 10B, a cut line CTb extending in the horizontal direction is arranged, and
RA is divided into regions DRAa and DRAb, and region DRB is divided into regions DRBa and DRBb.
Similarly, in each of the areas divided into the cut lines CTb, the cells CL are distributed so that the number of signal lines (the number of cuts) intersecting the cut lines is minimized and the cell density in the divided areas is equal. . This distribution is performed in an area divided by the cut line CTb. In other words, cells in sub-areas DRAa and DRAb are sorted in area DRA, and sub-areas DRBa and DRAb are assigned in area DRB.
Cell distribution to Bb is performed. Thereafter, the division of the small area by the cut line and the distribution of the cells in the area intersecting the cut line are performed. When the division of all the cut lines and the distribution of the cells are completed, the arrangement of the cells on the chip is completed. Hereinafter, a specific example will be described.

Now, as shown in FIG. 11A, the cell 8a
To 8j on a semiconductor chip. The cells 8a to 8g are interconnected by signal lines 9a to 9f, respectively. Cell 8g further includes cell 8h and signal line 9
g, connected to the cell 8j via the signal line 9h, and further connected to the cell 8i via the signal line 9i. Cells 8h and 8j are interconnected by signal line 9a, and cells 8i and 8j are interconnected by signal line 9k.

[0008] These cells 8a to 8j are shown in FIG.
Are arranged on a substrate (semiconductor chip) shown in FIG. In the mini-cut method, first, in order to divide the substrate 10a into small regions, cut lines 1 are cut in the vertical and horizontal directions.
3a to 13e are arranged. Cut range 13a to 13e
In each divided small area, slots 11a to 11l for arranging cells are arranged. This figure 1
In the arrangement shown in FIG. 1 (B), one slot is arranged so that one cell can be arranged in a small area. These slots 11a to 11l represent areas where cells can be arranged in the corresponding small areas.

To interconnect these slots,
The wiring grid lines 12a are arranged. This wiring grid line 12a
Indicates a position where a wiring can be arranged. In FIG. 11B, it is assumed that all the nets for connecting the terminals of the cell are connected to two terminals in order to simplify the description. The wiring is arranged on the wiring grid line 12a.
Normally, a plurality of wiring grid lines represent wiring that can be arranged in each region, and a plurality of wiring grid lines are arranged. However, in FIG. 11B, in order to simplify the drawing, they are arranged in a horizontal direction. One example is shown in which one wiring grid line is arranged for each of the small regions, and one wiring grid line is arranged for the wiring arranged in the vertical direction.

In the mini-cut method, the substrate 10a
, The cells 8a to 8j are appropriately arranged. Next, one cut line is selected from the cut lines 13a to 13e in accordance with a predetermined processing order. Now, among the cut lines 13a to 13e, the cut line 13b, the cut line 13d, the cut line 13e, the cut line 1
The processing is performed by selecting a cut line in the order of 3a and the cut line 13c.

First, the cut line 13b is selected according to the processing order. With this cut line 13b,
A small area including the slots 11a to 11f;
The image is divided into two small regions including g to 11j. In these divided regions, cells are allocated so that the number of signal lines intersecting the cut line 13b is minimized and the cell density in these two small regions is equal.

As shown in FIG. 12, the cut line 13b
The cells 8a to 8e are arranged in the small area including the slots 11a to 11f on the left side of the cut line 13b, and the cells 8f to 8e are arranged in the small area including the slots 11g to 11l on the right side of the cut line 13b.
Consider a state where j is arranged. Assuming that the cells 8a to 8j have the same area, five cells 8a to 8e are arranged in the small area on the left side of the cut line 13b, and five cells 8f to 8j are arranged in the small area on the left side. And the cell density is uniform. In addition, only one signal line 9e intersects with the cut line 13b. Therefore, in the state shown in FIG. 12, the conditions at the time of allocation (i) are that the cell densities in the divided areas are equal, and (i)
i) The condition that the number of signal lines intersecting the cut line serving as the dividing line is minimized is satisfied, and the cell allocation by the cut line 13b is completed. When this processing is completed, the next cut line 13e is selected, and this cut line 1e is selected.
The area intersecting 3e is divided, and the cells are allocated again. Thereafter, the substrate 10a is divided for all cut lines, and cell allocation is repeated.

As a result, cells are equally allocated in each area. In addition, by using an evaluation criterion that minimizes the number of signal lines (the number of cuts) in the cut line, the signal lines are locally concentrated, and unwired areas occur in the concentrated area or the wiring area increases. To prevent

Further, in the integrated circuit device, it is necessary to propagate signals at high speed for high-speed operation. However, as the degree of integration increases and the wiring width becomes finer, the signal propagation delay in this wiring has a greater effect than the gate delay. In order to minimize the signal propagation delay in such a signal line, a critical path (a signal propagation path in which an upper limit is set for the signal propagation delay) is weighted, and compared with other unweighted signal lines. The length of the virtual wiring (the wiring is a signal wiring whose wiring is expected to pass through the small area, and the length of the virtual wiring) is shortened by making it difficult to cross the cut line, thereby reducing the signal propagation delay. Is done.

Now, as shown in FIG. 13A, the cell 8k
８8q are arranged, and the cell arrangement when the signal line 9o connecting the cell 8n and the cell 8o is a critical path is considered. Signal line 9l between cells 8k and 8l, signal line 9m between cells 8l and 8m and cells 8m, 8n, 8p
The signal line 9n interconnecting the signal lines 8q and 8q is not a critical path, and the upper limit of the delay time is not set.

The cells 8k to 8q shown in FIG.
Is arranged on the substrate 10b shown in FIG.

Prior to arranging the cells, first, the substrate 10
For b, vertical cut lines 13f to 13h and a horizontal cut line 13i are set. For each of the areas divided by these cut lines 13f to 13i, one slot, a total of eight slots 1
1 m to 11 t are arranged. This slot 11m ~ 11
In order to perform wiring during t, a wiring grid line 12b is arranged. The two wiring grid lines 12b are arranged in parallel with and adjacent to the cut line 13i in the horizontal direction, and two in each of the slots arranged in the vertical direction.

In the arrangement considering the delay time (timing drive arrangement), first, the cell 8k is placed on the substrate 10b.
８8q are appropriately arranged. Next, weighting is performed on the signal line 9o to which the upper limit value of the delay is specified. Here, it is assumed that a weight of 2 is set for the signal line 9o to which the upper limit value of the delay is specified, and that the remaining signal line 9ln and the signal lines 8p and 8q have a weight of 1. Therefore, the number of intersections (the number of cuts) when the signal line 9o crosses the cut line is 2.

The cut lines 13f to 13i are cut line 13g, cut line 13i, and cut line 13f.
And the cut line 13h is selected in this order and the processing is performed.

First, the first cut line 13g is selected, and the substrate 10b is divided into a small area including the slots 11m to 11p and a small area including the slots 11q to 11t.
In these small areas, cells are allocated so that the sum of the weights of the signal lines intersecting the cut line 13g is minimized and the cell densities of these small areas are equal.

Now, as shown in FIG.
In a small area including the slots 11n to 11p on the left side of 3g,
Cells 8k to 8m are arranged, and cells 8n to 8m are arranged in a small area including slots 11q to 11t on the right side of cut line 13g.
Consider a state where q is assigned. It is assumed that all the cells 8k to 8q have the same size. The signal line 9n intersects with the cut line 13g, and the weight of the signal line 9n is 1, and therefore, the weight of the signal line intersecting with the cut line 13g is 1. In addition, the cell density in the cell arrangement region generated by this division, that is, the small region is 3 /
4 (= 0.75) and 4/4 (= 1), and as much as possible the allocation is realized under these conditions. Therefore, the processing for the cut line 13g is completed, the area is further divided using the next cut line 13i, and the same cell allocation is performed.

[0022]

In the mini-cut method shown in FIGS. 11 and 12, one of a plurality of line segments called cut lines set on a substrate (chip) is selected, and the cut line is selected. 2 lines on board
After the division, (i) cells in two small regions generated by dividing the region on the substrate into two by the cut lines so that the number of signal lines (nets) intersecting the cut lines is minimized. The process of "distributing cells to small areas so that the densities become uniform" is hierarchically repeated to determine the cell arrangement position. Therefore, as a result, the cell density on the substrate becomes uniform. However, since the amount of wiring passing through each small area is not considered at all, local wiring congestion may occur. That is, it is assumed that the cells are allocated as shown in FIG. 12, and after the processing for all the cut lines is completed, the cell arrangement as shown in FIG. 15 is given. In this state, cells 8a, 8b, 8c, 8d and 8e are arranged in slots 11d, 11a, 11b, 11c and 11f, respectively, and slots 11i, 11l, 11k, 11j and 1
In 1h, cells 8f, 8i, 8j, 8h and 8g are arranged, respectively.

Eventually, when the cell arrangement is completed, wiring patterns 14a to 14k are arranged on the wiring grid lines 12a, and interconnection (connection) between cells is performed. However, the corresponding wiring grid line 12a does not exist in the wiring pattern 14h corresponding to the signal line connecting the cells 8g and 8i. Therefore, signal line 9i shown in FIG.
Cannot be provided for the wiring pattern 14i.

When the timing drive arrangement is performed by using the mini-cut method taking the delay time shown in FIGS. 13 and 14 into consideration, "a net (signal line) whose delay time is desired to be reduced is weighted. In order to reduce the virtual wiring length and reduce the signal propagation delay caused by the wiring, the method is used in which the signal lines are less likely to intersect with the cut lines than the unweighted signal lines. However, in this case, only reduction of the virtual wiring length of the signal line (weighted signal line) for which the delay time is to be reduced is considered. When the cell arrangement shown in FIG. 14 is finally realized after the processing for all the cut lines is completed, the wiring result is as shown in FIG. In the arrangement shown in FIG. 16, the slots 11m, 11n, 11o, 11r, 1
Cells 8l, 8k, 8m, 1s and 11t, respectively,
8n, 8p, 8o and 8q are arranged. The cells 8l and 8k are interconnected by a wiring pattern 141 on the wiring grid line 12b. The cells 8l and 8m are interconnected by a wiring pattern 14m on the wiring grid line 12b. Cell 8m has wiring patterns 14 connected to cells 8n and 8p.
n and are connected to the cell 8q by the wiring pattern 14n. Cells 8n and 8o are interconnected by a wiring pattern 14o.

In general, the smaller the capacitance of the wiring forming the signal line, the shorter the signal propagation delay time. Therefore, it is desirable to reduce the capacitance of the wiring for the signal line whose delay is to be reduced. According to the wiring result shown in FIG. 16, the wiring pattern 14o of the signal line 9o whose delay should be reduced is
The cells 8n and 8o connected to the signal line 9o are arranged in the adjacent slots 11q and 11s, and the wiring length of the wiring pattern 14o is shortened, so that a desirable arrangement for shortening the delay time is realized. . However, the wiring pattern 14n exists in parallel with the wiring pattern 14o, so that the capacitance between the wirings adjacent to the wiring pattern 14o and the wiring pattern 14n is increased, and the signal propagation delay time of the signal line 9o is increased. Thus, there arises a problem that the required upper limit of the delay time cannot be satisfied.

As described above, according to the conventional method of arranging cells by the mini-cut method, local wiring congestion may occur, and signal lines that cannot be wired may occur. Further, in the case of arranging and wiring an integrated circuit device in which an upper limit value of the delay time is specified for some of the signal lines, only reducing the virtual wiring length by weighting based on the delay time is considered. Since no consideration is given to the capacitance between adjacent wirings, the delay time increases due to an increase in the capacitance between adjacent wirings, and the specified upper limit value of the delay time may not be satisfied.

Further, when calculating the delay time in consideration of not only the capacitance of the wiring but also the resistance, the delay differs between each cell pair even for the same signal line. For example,
In the arrangement shown in FIG. 16, the delay time of signal line 9n between cell 8m and cell 8p is shorter than the delay time of signal line 9n (wiring pattern 14n) between cell 8m and cell 8q. Therefore, when calculating the delay in consideration of the resistance component, the upper limit value of the delay time is specified for the segment between the cell pairs included in the signal line, but in an actual method, the delay time of the entire signal line is Since only the upper limit of the cell pair is considered and the delay between the cell pairs is not taken into account, it is not possible to realize such a cell arrangement in consideration of the upper limit of the delay time between the cell pairs.

Therefore, an object of the present invention is to prevent the occurrence of local wiring congestion and, when an upper limit value of the delay time is specified for some signal lines or cell pairs, after the wiring processing, It is an object of the present invention to provide a cell arrangement method capable of generating an arrangement result in which a delay time easily achieves its upper limit.

Another object of the present invention is to provide a cell placement method according to the mini-cut method which can reduce the degree of wiring congestion and easily satisfy the upper limit of the delay time.

[0030]

The invention according to claim 1 is
A method for arranging cells for an integrated circuit device, comprising: arranging cells on a substrate, and then connecting the cells with wiring segments that pass through wiring grid lines set in advance on the substrate. A cut line setting step for setting a plurality of line segments each called a cut line for dividing the substrate along the vertical direction and the horizontal direction on the substrate, and assuming the entire substrate as one cell arrangement region, A pre-processing step of allocating all the cells included in the integrated circuit device to the cell arrangement area; and selecting one cut line from a plurality of cut lines in accordance with a predetermined processing order; An area dividing step of dividing each of the cell arrangement areas intersecting the line into two cell arrangement areas using the selected cut line as a dividing line; For each of the divided cell arrangement areas, it is expected that (i) the wiring will pass through the divided cell arrangement area at the time of wiring so that the number of signal lines intersecting the selected cut line is minimized. (Iii) The sum of the areas of the cells allocated in each divided cell arrangement region is set such that the ratio between the length of the wiring and the length of the wiring grid line in the divided cell arrangement region becomes equal. A cell allocation step of allocating the cells in the divided cell arrangement area to the divided cell arrangement area so as not to exceed a cell area that can be arranged in the divided cell arrangement area; and a region division step and a cell allocation step. A step of repeatedly executing the processing for all of the plurality of cut lines.

According to a second aspect of the present invention, an upper limit value of a delay time is specified for a signal line connecting specific cells, and a plurality of cells are set so as to satisfy the specified upper limit value of the delay time. A method for arranging cells for an integrated circuit device, comprising: arranging cells on a substrate and then interconnecting the cells by wiring segments passing on wiring grid lines set in advance on the substrate, comprising: A cut line setting step for setting a plurality of line segments each called a cut line for dividing a substrate along a vertical direction and a horizontal direction, and an upper limit of a designated delay time for each signal line A weight determination step of determining the weight of the signal line according to the value; a preprocessing step of allocating all the cells included in the integrated circuit device in the placement area by regarding the entire substrate as one cell placement area; One cut line is selected from a plurality of cut lines in accordance with a predetermined processing order, and each cell arrangement area on the substrate intersecting with the selected cut line is arranged in two cells by using the selected cut line as a dividing line. (Ii) For each of the area dividing step to divide the area and the cell arrangement area divided by the area dividing step, (i) the sum of the weights of the signal lines intersecting the selected cut line is minimized. The weighted virtual wiring length obtained by multiplying the wiring length of each signal line in the divided cell placement area by the weight obtained for all signal lines expected to pass through the divided cell placement area at the time of wiring (Iii) Sum of the areas of the cells allocated in each divided cell arrangement region so that the ratio of the sum and the length of the wiring grid line in the corresponding divided cell arrangement region becomes equal. A cell allocating step of allocating cells in each divided cell placement area to a divided cell placement area so as not to exceed a cell area that can be placed in the divided cell placement area; A step of repeatedly executing a cell allocation step for all of the plurality of cut lines.

According to a third aspect of the present invention, an upper limit value of a delay time is specified for a signal line connecting specific cells, and a plurality of cells are placed on a substrate such that the upper limit value of the delay time is satisfied. A cell placement method for an integrated circuit device, which is configured by connecting each cell by a wiring segment passing on a wiring grid line set in advance on a substrate after the placement, A cut line setting step for setting a plurality of line segments each called a cut line for dividing the substrate along the horizontal direction and the horizontal direction, and integrating the entire substrate into a cell arrangement region by regarding the entire substrate as one cell arrangement region A pre-processing step of allocating all cells included in the circuit device; and selecting one cut line from a plurality of cut lines according to a predetermined processing order. An area dividing step of dividing each of the cell arrangement areas intersecting the cut line into two cell arrangement areas using the selected cut line as a dividing line, and (i) selecting each of the cell arrangement areas divided by the area dividing step Sum of weights calculated based on the ratio of the virtual delay value of the segment between cell pairs included in this signal line and the upper limit value of the delay time specified for the segment between cell pairs of the signal line intersecting the cut line (Ii) The virtual wiring length in the divided cell arrangement area of each signal line, which is obtained for all the signal lines expected to pass through the divided cell arrangement area at the time of wiring, so that The ratio between the sum of the weighted virtual wiring lengths multiplied by the line weights and the wiring grid lengths in the corresponding divided cell placement regions is equalized.
And (iii) in each of the divided arrangement areas, the sum of the areas of the cells allocated in the divided cell arrangement area does not exceed the cell area that can be arranged in the divided cell arrangement area. The method includes a cell allocating step of allocating cells to two related cell arrangement areas after the division, and a step of repeatedly executing the area dividing step and the cell allocating step for all of the plurality of cut lines.

By arranging the signal lines so as to minimize the number of signal lines intersecting the cut lines, that is, the number of cuts, the virtual wiring length can be shortened. Also, by arranging the cells so that the ratio between the virtual wiring length that seems to pass through the small area and the usable wiring grid line length in this small area is equal, the congestion degree of the virtual wiring in each small area is increased. Are equalized, the wiring grid line utilization rate in each small area becomes equal, and accordingly, wiring can be performed in all the small areas.

The signal lines are weighted according to the upper limit value of the delay time, and the cells are sorted so that the sum of the weights of the signal lines crossing the cut line is minimized.
A signal line having a large weight, that is, a signal line for which an upper limit value of the delay time is set can be suppressed from intersecting with the cut line, and a signal line having a severe condition for the delay time is arranged in one small region. A signal propagation delay of a signal line is reduced. In addition, in the divided placement region, the virtual wiring length was weighted in the divided cell placement region of the signal line, which was obtained for all signal lines expected to pass through the divided cell placement region. By equalizing the ratio between the sum of the weighted virtual wiring lengths and the wiring grid line length in the cell placement area after this division, the weighted virtual wiring length of the signal line with a severe delay time condition is increased. Peripheral wiring congestion is reduced,
It is possible to prevent a signal line from being routed adjacent to a critical path with severe delay time conditions, and to suppress an increase in signal propagation delay due to parasitic capacitance.

The weight calculated for the signal line intersecting the cut line based on the ratio between the virtual delay value of the segment between cell pairs included in the signal line and the upper limit value of the delay time specified for the segment between cell pairs. By arranging the cells so that the sum of is minimized, it is possible to prevent a signal line including a segment with a large weight from intersecting the cut line,
Cells requiring strict delay time can be arranged close to each other. In addition, the sum of the virtual wiring length in the cell placement area after the division of the signal line and the weighted virtual wiring length obtained by multiplying the weight of the signal line, which is obtained for all the signal lines in the cell placement area after the division, and By equalizing the ratio with the wiring grid lines in the cell arrangement area, the degree of wiring congestion can be equalized in each cell arrangement area, and the wiring is arranged adjacent to the wiring with severe delay time conditions Can be suppressed, and the weighted use values of the wiring grid lines become uniform in the cell arrangement region, so that the occurrence of unwiringable signal lines can be suppressed.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a flowchart showing a cell arrangement method for an integrated circuit device according to a first embodiment of the present invention. Hereinafter, the cell arrangement method according to the first embodiment of the present invention will be described with reference to FIG.

Now, as shown in FIG. 11A, the cell 8a
To 8j are arranged on the substrate 10a shown in FIG. Signal lines 9a to 9f sequentially connect the cells 8a to 8g in series. A signal line 9g connected to the cell 8h, a signal line 9i connected to the cell 8i, and 9h connected to the cell 8j are connected to the cell 8g. Cell 8h and cell 8j are connected by signal line 9j, and cell 8i and cell 8j are connected by signal line 9k.

First, as shown in FIG.
A plurality of cut lines 13a to 13e are set in a vertical direction and a horizontal direction for dividing 0a (step S).
1). Cut lines 13a to 13c are arranged at regular intervals in the vertical direction, and cut lines 13d and 13c are arranged in the horizontal direction.
e are arranged at predetermined intervals. At the time of division by this cut line, the minimum divided area divided by the cut line is 1
Cut line 13a so that three slots are arranged
13e is arranged. Slots 11a to 11l arranged on the substrate 10a indicate the cell area that can be arranged in each region. Here again, a plurality of cut lines 13
Regarding the processing order, that is, the selection order for a to 13e, it is set that the processing is performed in the order of the cut line 13b, the cut line 13d, the cut line 13e, the cut line 13a, and the cut line 13c.

The substrate 10a is regarded as one cell arrangement region, and all the cells 8a to 8j in the circuit are allocated to the cell arrangement region constituted by the entire substrate 10a (step S).
2). Next, a cut line number i indicating a cut line to be processed is set to 1 and a cut line to be selected is specified (step S3). In the processing order of the cut line,
The cut line processed first is cut line 13b
It is. Therefore, the first cut line 13b
Thereby, the cell arrangement region intersecting with the cut line 13b is divided into two cell arrangement regions using the cut line 13b as a dividing line (step S4). The division of the cell arrangement region allows the slot 11a on the left side of the cut line 13b to be divided.
Cell arrangement region including cut lines 13b to 11f
The cell arrangement area is divided into small areas including the slots 11g to 11l on the right side of FIG.

Next, cells allocated over the entire substrate 10a are allocated to small areas so as to satisfy the following conditions. This condition is as follows: (i) the number of signal lines intersecting the cut line 13b is minimized; and (ii) the virtual wiring grid line usage rate in each cell placement area after division (= in the cell placement area at the time of wiring). Length of wiring expected to pass through /
And (iii) the sum of the areas of the cells allocated to the two divided cell arrangement areas is arranged in the cell arrangement area after the corresponding division. Does not exceed the possible cell area.

The virtual wiring length is proportional to the number of connection points of the signal lines included in the divided cell arrangement region.
Only increase. That is, if there are N connection points of cells in the target cell placement area, the virtual wiring length in that cell placement area is N · L.

Now, consider the case where the cell allocation as shown in FIG. 2A is realized. That is, in FIG. 2A, the slots 13a to 13
In the cell arrangement region including the cell f, the cells 8a to 8f are arranged, and the slots 11g to 1g on the right side of the cut line 13b are arranged.
In the divided cell arrangement region including 1l, cells 8g to 8g
j is arranged. In the divided cell arrangement area on the left side of the cut line 13b, the number of connection points of the cells 8a to 8f is 11, and the virtual wiring length is 11L. Also, cells 8g to 8g in the divided cell arrangement area on the right side of the cut line 13b
The number of connection points of 8j is also 11, and the virtual wiring length is 11
L. The cut line 13b divides the substrate 10a in two in the horizontal direction, and the divided cell arrangement region on the right side of the cut line 13b and the divided cell arrangement region of the cut line 13b have the same size. The length of the wiring grid line 12a in the region is the same. Therefore, the usage rates of the virtual wiring grid lines in these two divided cell arrangement areas become equal, and the above-mentioned condition (ii) is satisfied.

The signal line crossing the cut line 13b is one signal line 9f, which satisfies the above condition (i). Further, the number of cells arranged in the divided cell arrangement region on the left side of the cut line 13b is 6, the number of slots included in the divided cell arrangement region is 6, and the number of cells in the divided cell arrangement region on the left side is six. The sum of the areas is
It does not exceed the cell area that can be arranged. Similarly, also in the divided cell arrangement region on the right side of the cut line 13b, the number of slots is 6, the number of allocated cells is 4, and the sum of the allocated cell areas is the cell area that can be arranged. Less than. Therefore, the above condition (iii) is satisfied. In this cell allocating step, cells are moved from a divided cell wiring area having a high virtual wiring grid line usage rate to a divided wiring area having a low virtual wiring grid line usage rate. This is because if the virtual wiring grid line usage rate is high,
This is because a large number of wiring grid lines are used in the divided cell arrangement region, indicating that the number of wirings is large. The cells are moved one by one, and the above-mentioned conditions (i) to (iii) are collated. When all of the conditions (i) to (iii) are satisfied, the processing for the first cut line 13b ends. I do.

Next, it is determined whether or not the cut line number i is the maximum value, and it is determined whether or not the processing for all the cut lines has been completed (step S).
6).

Now, since i = 1 and the processing for the first cut line 13b in the processing order has been performed, the flow advances to step S7, the cut line number i is incremented by 1, and the flow returns to step S4 with i = 2. . Step S4
In, the next cut line 13d is set according to the cut line number i = 2.

As shown in FIG. 2B, the cut line 13d intersects the cell arrangement regions SL and SR divided by the cut line 13b. Therefore, these cell arrangement regions SL and SR are again cut line 13d.
Divides the cut line 13d as a dividing line.
The cell arrangement area SL is divided into divided cell arrangement areas SLu and SL
d, and the cell placement region SR is divided into divided cell placement regions SRu and SRd. Divided cell placement area S
Cell allocation is performed again in Ru and SRd,
Cells are allocated in divided cell placement regions SRu and SRd.

In the state shown in FIG. 2B, in the cell arrangement region SL, there is only one signal line 9b intersecting with the cut line 13d. The number of connection points in the divided cell arrangement region SLu is 3, and the virtual wiring length is 3L. On the other hand, in the divided cell arrangement region SLd, the number of cell connection points is 7, and the virtual wiring length is 7L. Regarding the wiring grid lines, the divided cell placement area SLu is ／ of the divided cell placement area SLd, and therefore the virtual wiring grid line usage rate is equal. In the cell arrangement region SR, two signal lines intersecting the cut line 13d are the signal lines 9g and 9j. In the cell arrangement region SR, the cell connects at least two signal lines, and therefore, the number of signal lines (the number of cuts) intersecting with the cut line 13d is the minimum. Split cell placement area SR
The virtual wiring length of u is 2L because the number of connection points is two.
On the other hand, in the divided cell placement region SRd, the virtual wiring length is 9L. In this case, for the wiring grid lines, the divided cell placement region SRd is 7/3 of the divided cell placement region SRu.
And divided cell placement regions SRu and SR
The virtual wiring grid line usage rate of d is not equal. However, they are as uniform as possible. For example, when the cell 8i is allocated to the divided cell placement area SRu from the divided cell placement area SRd having a high virtual wiring grid line usage rate, the number of cuts increases. Therefore, the above conditions (i) to (ii)
i) is also determined to be satisfied in the divided cell placement regions SRu and SRd.

Thereafter, the process proceeds to step S6 shown in FIG.
It is determined whether or not the processing for all the cut lines has been completed, and the processing for the remaining cut lines 13a, 13c, and 13e is sequentially performed based on the determination result. When the process for the final cut line 13c is completed, as shown in FIG. 3, the cells 8a to 8j are stored in the slots 11d, 11a, 11b, 11c,
11f, 11e, 11h, 11j, 11k and 11l
Placed in

After arranging the cells, the wiring patterns 14a to 14k are arranged on the wiring grid lines 12b to realize connection between cells. As is clearly shown in FIG.
8j, the wiring patterns 14a to 14k can be arranged on the wiring grid lines corresponding to all the signal lines, respectively, and the wiring of all the signal lines becomes possible.

That is, the virtual wiring length is shortened by minimizing the number of cuts, and then the cells are arranged so as to make the virtual wiring grid line usage rate uniform, thereby achieving the congestion degree of the wiring in each cell arrangement area. Becomes the same, and the substrate 1
It is prevented that many signal lines are concentrated on a part of the area 0a, and all the signal lines can be surely wired in the wiring process performed after the cell arrangement.

[Modification] FIG. 4 is a diagram showing a flow of a cell arrangement method according to a modification of the first embodiment of the present invention. FIG. 4 shows processing steps corresponding to steps S4 and S5 shown in FIG. Hereinafter, a cell arrangement method according to a modification of the first embodiment of the present invention will be described with reference to FIG.

First, when a cut line is selected, the cell arrangement area is divided into two areas RA and RB according to the selected cut line (step S10).

Next, cell sets CA0 and CB0 are allocated to the two divided cell placement areas RA and RB, and a mark indicating that all of these sets CA0 and CB0 are movable is marked (step S11). In step S11, a mark indicating the corresponding divided cell arrangement area and a movable mark are attached to each cell according to the divided cell arrangement area.

Next, an initial value u0 of the maximum grid line utilization rate u in each of the areas RA and RB is calculated. The grid line usage rate is expressed by the ratio between the virtual wiring length and the wiring grid line length in the above embodiment, but in this modified example, the wiring grid line usage rate is represented by the following equation: Line usage rate = (virtual wiring length in the area + wiring grid line length covered by the internal pattern of the cell in the area) / wiring grid line length in the area The pattern in the cell becomes a wiring obstacle, and the cells are interconnected in this area. Wiring for connection cannot be arranged. By taking this wiring obstacle into consideration, the degree of wiring congestion is further reduced.

Next, the cell density D in the areas RA and RB is calculated (step S13). This cell density is different from the previous embodiment, and is determined here simply by the ratio of the number of slots occupied by cells in the area to the number of slots in the area.

The calculated cell density D is equal to the upper limit value Dul.
mt is determined (step S1).
4). When the cell density D exceeds the upper limit value Dulmt, a cell having the largest gain is selected from cells that can be moved from a region having a high cell density. Here, the gain is given by the amount of decrease in the number of cuts (step S1).
5). On the other hand, when the cell density D is equal to or less than the upper limit value Dulmt, the cell having the maximum gain is selected from the cells marked as movable that are included in the area where the grid line usage rate is high (step S16).

In steps S15 and S16, if the corresponding cell exists according to the result of the determination as to whether or not the corresponding cell exists (step S17), the selected cell is moved to the opposite area, and Mark as immovable. Next, after this cell movement, the maximum grid line utilization rate u in each area is calculated, and according to the cell movement,
The value of the virtual wiring length in the region and the value of the wiring grid line length closed by the pattern in the cell are updated, the grid line usage rate u is calculated according to the updated parameters, and the process returns to step S13. Here, the maximum grid line usage rate u indicates the higher one of the wiring grid line usage rates in the areas RA and RB.

On the other hand, if the corresponding cell does not exist, it is determined whether or not the minimum value min u of the maximum grid line utilization rate u obtained in step S18 is smaller than the initial value u0 (step S19). If the minimum value min u of the maximum grid line usage rate u is smaller than the initial value u0, the process returns to step S11 with the cell arrangement giving the minimum value min u as the initial cell allocation (step S20). By forming a loop returning from step S18 to step 13, cell allocation is realized such that the cell density in each cell arrangement region becomes uniform and the grid line usage rate becomes uniform. The return from the step S20 to the step S11 realizes the cell allocation that reduces the grid line utilization rate as much as possible (reduces the degree of wiring congestion), and detects the end of the cell allocation processing. That is, in step S19, the minimum value minu of the grid line usage rate u is equal to or greater than the initial value u0 (updated from the maximum grid line usage rate obtained in the previous processing (see step S12)). In this case, it is determined that the cell allocation that minimizes the cell density and the wiring usage rate has been given, and the processing for this cut line ends.

In the flow shown in FIG. 4, it is assumed that the virtual wiring length of the net (signal line) is different from that of the previous embodiment and is located at the center of the area where the cell is allocated.
The minimum rectangle including the cell connected to the signal line may be obtained, and the rectangle may be defined based on the half-perimeter and the number of fan-outs (for example, given by the product of the half-perimeter and the number of fan-outs). . The virtual wiring length in the cell placement area is
Instead of simply defining the sum of the virtual wiring lengths of the nets, the sum may be defined by the sum of {virtual wiring length × (area of overlapping part of minimum rectangle and cell placement area / area of minimum rectangular area)} of each net.

The wiring grid line length in the area is expressed by the usable wiring grid line length in the cell arrangement area, that is, the difference between the set wiring grid line length and the grid line length closed by the cell. You may.

According to the cell arranging method shown in FIG. 4, a cell is always selected from a region having a high grid line usage rate and is moved to the other region. In the source area of the cell, the length of the wiring grid line blocked by the pattern in the cell decreases. When the virtual wiring length in the area is calculated using the area where the minimum rectangle overlaps the cell arrangement area, the virtual wiring length in the cell movement source area also decreases as long as the number of cuts decreases. Therefore, the movement of the cell that reduces the number of cuts acts to lower the grid line usage rate in the area where the grid line usage rate is high, and the grid line usage rate in the two areas is the average grid line usage rate in the two cell arrangement areas. The value is close to the usage rate. Here, the movement of the cell that reduces the number of cuts reduces the sum of the virtual wiring lengths in the cell placement area, and therefore reduces the average grid line utilization rate (the sum of the wiring grid line lengths that block the pattern in the cell and the cell). The sum of the wiring grid line lengths in the arrangement area is constant.) Therefore, by moving the cells so as to reduce the number of cuts, the maximum grid line usage rate can be reduced.

As described above, according to the first embodiment of the present invention, the sum of the areas of the cells allocated to the cell arrangement region is minimized so that the number of cuts is minimized, the usage rate of the virtual wiring grid lines is equalized. Are allocated so that the cell area does not exceed the cell area that can be placed in the cell placement area, so that the cell density in each cell placement area becomes uniform and the degree of congestion of wiring (use rate) in the cell placement area And the concentration of many signal lines in a partial area on the substrate can be suppressed, and all the signal lines can be wired in a wiring process performed after cell placement.

[Second Embodiment] FIG. 5 is a flowchart showing a cell arrangement method according to a second embodiment of the present invention. Hereinafter, a cell arrangement method according to the second embodiment of the present invention will be described with reference to FIG.

Now, cells 8k to 8k as shown in FIG.
It is assumed that 8q is arranged on substrate 10b shown in FIG. Cells 8k to 8m are connected to signal lines 9l and 9m
Are sequentially connected in series. Cell 8m is
Connected to cells 8n, 8p and 8q via signal line 9n. Cell 8n and cell 8o are connected via signal line 9o. The upper limit of the delay time is specified for the signal line 9o, and the upper limit of the delay time is not specified for the remaining signal lines 9l to 9n.

First, as initial processing, a plurality of vertical and horizontal cut lines 13f to 13i for dividing the substrate 10b are set (step S30). In the cell arrangement area divided by the cut lines 13f to 13i, slots 11m to 11t are arranged on the substrate 10b such that one slot is arranged. In accordance with the settings of the cut lines 13f to 13i,
Regarding the processing order of f to 13i, the cut line 13g,
It is determined that the processing is performed in the order of the cut line 13i, the cut line 13f, and the cut line 13h. At that time, the slots 11
A wiring grid line 12b for interconnecting m to 11d is arranged.

Next, for each of the signal lines 9l to 9o, the weight of the signal line is determined according to the specified upper limit value of the delay (step S31). In the configuration shown in FIG. 13A, the upper limit of the delay time is set for the signal line 9o, the weight is set to 2, and the remaining signal lines 9l to 9n are set.
Is a normal signal line in which the upper limit of the delay time is not set, and has a weight of 1.

Next, as a pretreatment, the entire substrate 10b is
One cell arrangement area is regarded, and all the cells 8k to 8q included in the circuit are allocated to this cell arrangement area (step S32). Next, the processing number i of the cut line is set to 1 (step S33), and the i-th, that is, the first cut line 13g in this predetermined processing order is selected, and the cell arrangement area crossing this cut line 13g is selected. Is divided into two cell arrangement areas using this cut line as a division line. Therefore, 10b is divided into a cell arrangement area including the slots 11m to 11p of the cut line 13g and a cell arrangement area including the right slots 11q to 11t.

Next, for each of the cell arrangement areas divided in step S34, (i) the weight of the signal line intersecting with the cut line 13g is minimized.
(Ii) The weighted virtual wiring grid line usage rate in the divided cell arrangement area can be equalized, and (iii) the sum of the areas of the cells allocated to the divided cell arrangement area can be arranged in the area. The cells allocated to the cell arrangement region (substrate 10b) before the division are allocated to two cell arrangement regions generated by the division so as not to exceed the proper cell area. Here, the weighted virtual wiring grid line usage rate is given by the ratio of the weighted length of wiring that is expected to pass through the cell placement area during wiring and the length of the wiring grid line within the cell placement area. The virtual wire length for the weighted signal line 9o is twice the length of the virtual wire corresponding to the other signal lines 9l to 9n, that is, the virtual wire length for the weighted signal line is Therefore, the length of the virtual signal line corresponding to the weighted signal line is equal to the number of normal signal lines corresponding to the value of the weight. The length is twice the virtual wiring length, and wiring congestion near the weighted signal line is reduced.

Now, consider a case where cells are allocated as shown in FIG. That is, cut line 1
In the region CL on the left side of 3e, cells 8k to 8p are allocated, and the remaining cells 8n to 8q are assigned to the cut line 13b.
Is assigned to the area CR on the right side of. The virtual wiring length is proportional to the number of connection points of the signal lines included in the cell arrangement region, and the connection point 1
Let it increase by L per point. The weighted virtual wiring length is obtained by multiplying the length of the wiring expected to pass through the cell arrangement region by the weight of the corresponding signal line. Accordingly, the weighted virtual wiring length in the cell placement area CL is 6 L since the number of connection points is 6. On the other hand, in the cell arrangement region CR, the signal line 9o is given a weight of 2 and the number of connection points is 4. However, since the total wiring length for the signal line 9o is added by 2L due to the weight, a total of 6 is added.
L. The wiring grid line lengths of the two cell arrangement regions CL and CR are symmetrical with each other, so that the wiring grid line lengths of the regions CL and CR are also equal. Therefore, the weighted virtual wiring grid line usage rates of the two cell arrangement areas CL and CR become equal.

The signal line that intersects the cut line 13g is the signal line 9n, and the weight of the signal line 9n is 1, so that the number of cuts is 1, which is the minimum.
Also, the number of cells arranged in each of the cell 8 regions CL and CR is smaller than the number of slots in each region (all cells have the same size), and therefore all of the conditions (i) to (iii) are satisfied. I have. Therefore, the processing for this cut line 13g is completed, and it is determined whether or not the processing for all the cut lines is completed (step S36). Here, the cut line number i is 1, and only the first cut line is designated, and the cut line number i is incremented by 1 (step S37), and the process returns to step S34.

In the second processing order, the cut line 13
i is selected, the regions CL and CR intersect with the cut line 13i, and the region CL is the divided cell arrangement region C
It is divided into Lu and CLd, and the cell placement region CR is divided into divided cell placement regions CRu and CRd. In the divided areas CLu and CLd, the preceding areas CL and CR
Are performed, and regions CRu and CRd
, The same processing as described above is executed. Two wiring grid lines are provided along the horizontal direction, and the wiring corresponding to the signal line 9n is included in only one cell arrangement region so as to minimize the number of cuts.

In the regions CRu and CRd, the weighted virtual wiring grid line usage rates are not equal, but are equalized as much as possible. Therefore, this cut line 13i
Is completed, and the processing of the next cut line is executed. If it is determined in step S36 that the processing has been completed for all cut lines, a cell arrangement as shown in FIG. 7 is obtained.

In FIG. 7, the slots 11m to 11s
Cells 8l, 8k, 8m, 8p, 8n, 8q and 8o
Are respectively arranged. Cells 8l and 8k are connected to wiring pattern 14l, cells 8l and m are connected by wiring pattern 14m, and cells 8m, 8p, 8n and 8q are interconnected by wiring pattern 14n. The cells 8n and 8o are interconnected by a wiring pattern 14o. The wiring pattern 14o corresponds to the signal line 9o with the weight 2 shown in FIG. Therefore, no wiring is arranged adjacent to the signal line 9o, so that an increase in delay time due to line capacitance is prevented.

That is, in the second embodiment, the signal line 9o whose signal propagation delay is to be reduced is weighted, and the virtual wiring length is weighted according to the weight, whereby the upper limit of the delay time is specified. The congestion degree around the wiring 14o corresponding to the signal line 9o is reduced.

In the second embodiment, the cell arrangement according to the flowchart shown in FIG. 4 can be performed. By weighting the virtual wiring length of each signal line in the equation for calculating the grid line usage rate, it is possible to reduce the congestion degree of the signal in the signal line for which the upper limit of the delay time is specified.

As described above, according to the second embodiment of the present invention, a weight is assigned to a signal line for which the upper limit of the delay time is specified, and the weighted virtual wiring grid line usage rate is considered in consideration of the weight. The weighted virtual wiring grid line usage rate is made equal, and the sum of the weights of the signal lines intersecting the cut lines is minimized, and furthermore, the area of the allocated cells in the cell arrangement area is calculated. Are allocated such that the sum of the cells is smaller than the cell area that can be arranged, thereby equalizing the cell density of each cell arrangement area, shortening the virtual wiring length, and further adding a weighted signal. It is possible to suppress the congestion of the wiring in the vicinity of the wiring, to suppress the wiring from being arranged adjacent to the wiring corresponding to the signal line for which the upper limit of the delay time is specified. End of wiring Can be the actual delay of obtaining it tends arrangement results reduced.

[Third Embodiment] FIG. 8 is a flowchart showing an arrangement method according to a third embodiment of the present invention. Hereinafter, a cell arrangement method according to the third embodiment of the present invention will be described with reference to FIG. The cell arranging method according to the third embodiment is the same as steps S1 to S4 in the first embodiment from the setting of the cut line to the division of the cell arranging area, and only the step 40 of allocating cells will be described.

Now, as shown in FIG. 9A, the cell arrangement region 10c is divided into two regions AL and AR by a cut line 13g, and cells 8r to 8t are arranged in the divided cell arrangement regions AL and AR. Consider performing an assignment process. Now, it is assumed that the output terminal of the cell 8r is connected to the input terminals of the cells 8s and 8t by the signal line 9p, and that the upper limit of the delay time is specified between the cells 8r and 8t.

The area A is assigned by allocating another cell (not shown).
Consider a state in which it is necessary to allocate two cells to L and one cell to the area AR. In this cell allocation step S40, (i) the cell placement areas AL and AR
In each case, the sum of the weights of the signal lines determined based on the ratio of the estimated value of the delay time between the cell pairs in the signal line intersecting the cut line 13j and the specified upper limit value of the delay time is minimized. In addition, (ii) the weighted virtual wiring grid line usage rate in the divided cell arrangement area is made uniform, and (iii) the sum of the cell areas allocated to the divided cell arrangement area is equal to the sum in the divided cell arrangement area. Are divided into the divided cell arrangement areas AL and AR so as not to exceed the cell area that can be arranged. In general, the wiring delay between two cells increases in proportion to the distance between the two cells. The cell is assumed to be located at the center of the allocated cell placement area, the distance between the two cells is determined under this assumption, and the virtual delay time between the two cells is determined based on this distance.

That is, as shown in FIG. 9B, the cells 8r and 8s are arranged at the centers OL and OR of the cell arrangement areas AL and AR, respectively, and the cell 8t is positioned close to the center OL of the cell arrangement area AL. At the position (slot) to be used. In this state, the inter-cell virtual wiring length is obtained. now,
The distance between cells 8r and 8s is 11 and cell 8r
And the distance of 8t is l2. The upper limit value tdu of the delay time is specified between the cell 8r and the cell 8t. The virtual delay time (estimated value of the delay time) is a measurement distance 11 with a unit delay time per unit distance as τ.
And the product of l2 and the unit delay time τ. The weight of the signal line (segment) between each pair of cells is defined as the ratio of the virtual delay between the pair of cells to the upper limit value tdu of the delay time specified between the pair of cells, and the weight of the signal line is included in this signal line. To be added.

The weight w of the signal line 9p is therefore
The arrangement shown in (B) is represented by the following equation.

W = 1 + (12 · τ / tdu) Here, since no upper limit of the delay time is specified between the cells 8r and 8s, the weight is set to 1.
Therefore, by reducing the distance l2, the weight w of the signal line 9p is reduced. Therefore, as shown in FIG. 9A, it is preferable to arrange the cell 8t close to the cell 8r. .

In this cell allocation, the weight of the signal line 9p is smaller than the condition of minimizing the weight of the signal line intersecting the cut line 13j. This condition is satisfied. The condition that the usage rates of the weighted virtual wiring grid lines in the cell arrangement region become uniform is also determined by the cell 8r
And the distance between the cells 8t is reduced, the weighted virtual wiring length of the signal line 9p is reduced, and in conjunction with the allocation of other cells (not shown), it acts to equalize the degree of wiring congestion.
The reduction in the weight due to the close arrangement increases the number of available wirings and reliably reduces the degree of wiring congestion.

By selecting the cell allocation shown in FIG. 9A, the probability that cells 8r and 8t will be allocated to the same cell arrangement area in the subsequent division will be increased (the weight of the signal line will always be reduced). As a result, when the cell placement is completed, as shown in FIG.
r and the cell 8t are easily arranged close to each other. In this case, as shown in FIG. 9C, the wiring length of the wiring pattern 14p between the cell 8r and the cell 8t is reduced, and the wiring delay is reduced.

When the upper limit of the delay time is not added to the weight w of the signal line, the number of paths between the cell pairs (the number of segments) is set so that the weight of the signal line is always 1. A configuration for normalizing by (number) may be used. That is, in the case of FIG. 9A, the number of segments (signal lines between two cells) is two, and the number of segments is normalized by a coefficient of two.

[Modification 1] The weight w of a certain signal line may be expressed by the following equation.

W = Σ (Achievement of constraint on terminal pairs between cells included in the signal line) ^{2 The} summation is performed for all terminal pairs (segments). However, the terminal pair (between cell) constraint achievement degree S is expressed by the following equation.

S = 1; virtual delay value ≦ delay upper limit value S = virtual delay value / delay upper limit value: virtual delay value> delay upper limit value Also in this equation, the weight of the signal line becomes virtual when the length of the segment becomes shorter. Since the delay value is reduced and the weight of the signal line is reduced, the same effect is obtained.

Also in this case, a configuration may be used in which the summation 行 な わ is normalized according to the number of all terminal pairs.

[Modification 2] When a cell corresponds to a gate, the weight w of the signal line is set to the input terminal fanin (n) of the gate driving the signal line and the output terminal fanout (n) connected to the signal line n. ) Is obtained from the virtual delay t and the delay upper limit u of the path segment using the following equation.

W = h (ΣPij ² / (| fanin
(N) | × | fanout (n) |)) Here, i indicates an input terminal of the gate, and j indicates an output terminal of the gate. Pij is given by the following equation.

Pij = tij / a · Uij: tij> a · Uij = 1: tij ≦ a · Uij h (x) is a monotonically increasing function, and the constant a is a real number from 0 to 1 inclusive. This weight is updated each time the cell moves. The virtual delay value tij indicates a virtual delay of the path segment between the terminal i and the terminal j.

In Modifications 1 and 2, in cell placement areas AL and AR, cell 8t is located in this area A.
When it is allowed to arrange both the L and AR, it is determined that the cell 8t is best arranged near the cell 8r in consideration of the delay time, and the arrangement that minimizes the delay time is determined. Is achieved.

[0094]

As described above, according to the present invention, the cells are allocated using the virtual wiring grid line usage rate, so that the local concentration of the wiring and the layout and wiring of the wiring adjacent to the critical path can be achieved. The shortest critical path can be realized, and an efficient cell arrangement can be realized.

That is, according to the first aspect of the present invention,
It is possible to prevent the occurrence of local wiring congestion in which wiring is concentrated in a part of the area on the substrate, and to obtain an arrangement result in which all signal lines can be easily wired. Can be increased, and the processing time required for the wiring processing can be reduced.

According to the second aspect of the invention, it is possible to prevent the wiring from being crowded around the signal line whose delay time is to be reduced, to reduce the capacitance between adjacent wirings of the signal line, and to achieve accurate timing. A high-performance integrated circuit device that operates at high speed can be realized.

According to the third aspect of the present invention, an arrangement result of reducing the wiring delay between cells whose delay is to be reduced can be obtained, so that a cell connected to the same signal line has a signal propagation path between cells. A cell arrangement that satisfies the required delay amount can be realized, and an integrated circuit device that operates at high speed with accurate timing can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a cell arrangement method according to a first embodiment of the present invention.

FIGS. 2A and 2B are diagrams illustrating a cell arrangement method according to the first embodiment of the present invention.

FIG. 3 is a diagram showing cell placement / wiring in a cell placement method according to Embodiment 1 of the present invention;

FIG. 4 is a flowchart showing a cell arrangement method according to a modification of the first embodiment of the present invention.

FIG. 5 is a flowchart showing an operation of a cell placement method according to the second embodiment of the present invention.

FIGS. 6A and 6B are diagrams for explaining a cell arrangement method according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a cell arrangement / wiring by a cell arrangement method according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing a cell arrangement method according to Embodiment 3 of the present invention.

FIGS. 9A to 9C show a third embodiment of the present invention;
FIG. 6 is a diagram for explaining a cell arrangement method in FIG.

FIGS. 10A and 10B are diagrams exemplarily showing a division sequence of a cell arrangement region by a conventional mini-cut method.

FIGS. 11A and 11B are diagrams for explaining a cell arrangement method using a conventional mini-cut method.

FIG. 12 is a diagram showing an example of a cell arrangement obtained by a conventional mini-cut method.

FIGS. 13A and 13B are diagrams for explaining a conventional mini-cut method in consideration of a delay time of a signal line.

FIG. 14 is a diagram showing an example of a conventional cell arrangement by a mini-cut method in consideration of a delay time.

FIG. 15 is a diagram for explaining a problem of the cell arrangement shown in FIG. 12;

FIG. 16 is a diagram for explaining a problem of the cell arrangement shown in FIG. 14;

[Explanation of symbols]

8a-8t cell, 9a-9p signal line, 10a-10
c board, 11a-11t slot, 14a-14p
Wiring pattern.

Claims (3)

[Claims] 1. A cell for an integrated circuit device, comprising: arranging cells on a substrate and connecting the cells with wiring segments passing on wiring grid lines set in advance on the substrate. An arrangement method, comprising: a cut line setting step of setting a plurality of line segments each called a cut line for dividing the substrate along a vertical direction and a horizontal direction on the substrate; A pre-processing step of assigning all cells included in the integrated circuit device to the cell arrangement area as a cell arrangement area; selecting one cut line from the plurality of cut lines according to a predetermined processing order; Each of the cell arrangement regions intersecting with the selected cut line on the substrate is divided into two cell arrangement regions by using the selected cut line as a dividing line. (Ii) cell arrangement after dividing at the time of wiring so that (i) the number of signal lines intersecting with the selected cut line is minimized for each of the cell arrangement areas divided by the area dividing step. The ratio between the length of the wiring expected to pass through the region and the length of the wiring grid line in the divided cell placement region is equal, and (iii) To ensure that the sum of the allocated cell areas does not exceed the cell area that can be placed in the cell placement area after the division,
A cell allocating step of allocating cells in the divided cell arrangement area to each of the divided cell arrangement areas, and a step of repeatedly executing the area division step and the cell allocation step for all of the plurality of cut lines. A cell arrangement method for a circuit device. 2. An upper limit value of delay time is specified for a signal line connecting specific cells, and after a plurality of cells are arranged on a substrate so as to satisfy the specified upper limit value of delay time, A cell arrangement method for an integrated circuit device configured by connecting each cell by a wiring line segment passing on a wiring grid line set in advance on a substrate, the method comprising: A cut line setting step of setting a plurality of line segments, each of which is called a cut line, for dividing the substrate along a signal line having a specified upper limit value of the delay time. A weight determining step of determining a weight of the signal line according to an upper limit value; assuming the entire substrate as one cell arrangement region, and allocating all cells included in the integrated circuit device to the cell arrangement region Processing step, selecting one cut line from the plurality of cut lines in accordance with a predetermined processing order, and using each of the cell arrangement regions intersecting the selected cut line on the substrate with the selected cut line as a dividing line. An area division step of dividing the cell into two cell arrangement areas; and (i) for each cell arrangement area divided by the area division step, a sum of weights of signal lines intersecting the selected cut line is minimized. (Ii) weighting obtained by multiplying the wiring length of each signal line in the divided cell placement area by the weight obtained for all signal lines expected to pass through the divided cell placement area at the time of wiring (Iii) Allocating the sum of the virtual wiring length and the length of the wiring grid line in the divided cell arrangement area to each other in the divided cell arrangement area. The cells in the divided cell placement area are distributed to the divided cell placement areas so that the sum of the divided cell areas does not exceed the cell area that can be placed in the divided cell placement area. A cell layout method for an integrated circuit device, comprising: a cell allocating step; and a step of repeatedly performing the area dividing step and the cell allocating step for all of the plurality of cut lines. 3. An upper limit value of a delay time is specified for a signal line connecting specific cells, and after a plurality of cells are arranged on a substrate so as to satisfy the specified upper limit value of the delay time, A cell arrangement method for an integrated circuit device configured by connecting each of the plurality of cells by a wiring segment that passes on a wiring grid line set in advance on a substrate, the method comprising: A cut line setting step of setting a plurality of line segments each called a cut line to divide the substrate along a direction and a horizontal direction, assuming the entire substrate as one cell arrangement region, A pre-processing step of allocating all cells included in the integrated circuit device; selecting one cut line from the plurality of cut lines according to a predetermined processing order; An area dividing step of dividing each of the cell arrangement areas intersecting the selected cut line into two cell arrangement areas using the selected cut line as a dividing line; and for each of the cell arrangement areas divided by the area dividing step, (i Calculating based on the ratio between the virtual delay value of the segment between cell pairs included in the signal line and the upper limit value of the delay time specified for the segment between cell pairs, of the signal line crossing the selected cut line. (Ii) virtual wiring in the divided cell arrangement area of the signal line, which is obtained for all signal lines expected to pass through the divided cell arrangement area at the time of wiring, so that the sum of the weights becomes minimum. (Iii) the cell arrangement after the division so that the ratio of the sum of the weighted virtual wiring length obtained by multiplying the length of the signal line to the length and the wiring grid line in the cell arrangement area after the division is equal; The cells in the divided placement area are moved to the divided cell placement area so that the sum of the areas of the cells allocated in the area does not exceed the cell area that can be placed in the divided cell placement area. A cell arranging method for an integrated circuit device, comprising: a cell allocating step for dividing; and a step of repeatedly executing the area dividing step and the cell allocating step for all of the plurality of cut lines.